Searched +full:0 +full:xf0400000 (Results 1 – 7 of 7) sorted by relevance
14 #define CONFIG_FTSMC020_BASE 0xe040000016 #define CONFIG_FTDMAC020_BASE 0xf0c0000018 #define CONFIG_FTAPBBRG020S_01_BASE 0xf000000020 #define CONFIG_RESERVED_01_BASE 0xe050000022 #define CONFIG_RESERVED_02_BASE 0xf080000024 #define CONFIG_RESERVED_03_BASE 0xf090000026 #define CONFIG_FTMAC100_BASE 0xe010000028 #define CONFIG_RESERVED_04_BASE 0xf100000033 #define CONFIG_FTUART010_01_BASE 0xf020000035 #define CONFIG_FTUART010_02_BASE 0xf0300000[all …]
28 reg = <0xf0400000 0x1000>;
61 reg = <0xf0400000 0x800>;62 interrupts = <0>, <2>;64 brcm,gisb-arb-master-mask = <0x7>;
15 …/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug bootmem_debug mem…16 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";21 memory@0 {23 reg = <0x00000000 0x40000000>;27 #clock-cells = <0>;34 #size-cells = <0>;35 cpu@0 {37 reg = <0>;51 reg = <0xf0300000 0x1000>;61 reg = <0xf0400000 0x1000>;[all …]
21 #size-cells = <0>;23 CPU0: cpu@0 {25 reg = <0>;31 d-cache-size = <0x8000>;41 memory@0 {43 reg = <0x0 0x00000000 0x0 0x40000000>;57 reg = <0x0 0xe4000000 0x0 0x2000000>;67 reg = <0x0 0xe6400000 0x0 0x400000>;75 reg = <0x0 0xe6000000 0x0 0x100000>;80 #clock-cells = <0>;[all …]
21 #size-cells = <0>;23 CPU0: cpu@0 {25 reg = <0>;31 d-cache-size = <0x8000>;41 memory@0 {43 reg = <0x00000000 0x40000000>;57 reg = <0xe4000000 0x2000000>;67 reg = <0xe6400000 0x400000>;75 reg = <0xe6000000 0x100000>;80 #clock-cells = <0>;[all …]
36 #define NPCM7XX_MMIO_BA (0x80000000)37 #define NPCM7XX_MMIO_SZ (0x7ffd0000)40 #define NPCM7XX_OTP1_BA (0xf0189000)41 #define NPCM7XX_OTP2_BA (0xf018a000)44 #define NPCM7XX_L2C_BA (0xf03fc000)45 #define NPCM7XX_CPUP_BA (0xf03fe000)46 #define NPCM7XX_GCR_BA (0xf0800000)47 #define NPCM7XX_CLK_BA (0xf0801000)48 #define NPCM7XX_MC_BA (0xf0824000)49 #define NPCM7XX_RNG_BA (0xf000b000)[all …]