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/openbmc/linux/arch/parisc/kernel/
H A Dperf_images.h27 0x4c00c000, 0x00000000, 0x00060000, 0x00000000,
28 0xe0e0e0e0, 0x004e0004, 0x07ffffff, 0xffc01380,
29 0x0101ffff, 0xfffff104, 0xe000c07f, 0xfffffffc,
30 0x01380010, 0x1fffffff, 0xff000000, 0x00000000,
31 0x00000fff, 0xff00000f, 0xffff0000, 0x0fffff00,
32 0x000fffff, 0x00000000, 0x00000000, 0x00ffffff,
33 0xfffff000, 0x0000000f, 0xffffffff, 0xff000000,
34 0x0000ffff, 0xfffffff0, 0x00000000, 0x0fffffff,
35 0xffff0000, 0x00000000, 0x6fffffff, 0xffffffff,
36 0xfff55fff, 0xffffffff, 0xffffffff, 0xf0000000,
[all …]
/openbmc/linux/arch/arm/mach-ep93xx/
H A Dsoc.h20 * the synchronous boot mode is selected. When ASDO is "0" (i.e
24 * 0x00000000 and nCS0 is decoded starting at 0xf0000000. For asynchronous
25 * boot mode they are swapped with nCS0 decoded at 0x00000000 ann nSDCE3
26 * decoded at 0xf0000000.
35 #define EP93XX_CS0_PHYS_BASE_ASYNC 0x00000000 /* ASDO Pin = 0 */
36 #define EP93XX_SDCE3_PHYS_BASE_SYNC 0x00000000 /* ASDO Pin = 1 */
37 #define EP93XX_CS1_PHYS_BASE 0x10000000
38 #define EP93XX_CS2_PHYS_BASE 0x20000000
39 #define EP93XX_CS3_PHYS_BASE 0x30000000
40 #define EP93XX_PCMCIA_PHYS_BASE 0x40000000
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dehci-rmobile.c16 0xC6700000
20 0xEE080000, /* USB0 (EHCI) */
21 0xEE0A0000, /* USB1 */
22 0xEE0C0000, /* USB2 */
27 0xEE080000, /* USB0 (EHCI) */
28 0xEE0C0000, /* USB1 */
42 writel(0, &ahbcom_pci->ahb_bus_ctr); in ehci_hcd_stop()
46 for (i = 100; i > 0; i--) { in ehci_hcd_stop()
58 return 0; in ehci_hcd_stop()
75 if (index == 0) in ehci_hcd_init()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcwsr_trap_handler.h24 0xbf820001, 0xbf820121,
25 0xb8f4f802, 0x89748674,
26 0xb8f5f803, 0x8675ff75,
27 0x00000400, 0xbf850017,
28 0xc00a1e37, 0x00000000,
29 0xbf8c007f, 0x87777978,
30 0xbf840005, 0x8f728374,
31 0xb972e0c2, 0xbf800002,
32 0xb9740002, 0xbe801d78,
33 0xb8f5f803, 0x8675ff75,
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci-rcar-gen2.c16 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
18 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
19 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
20 #define RCAR_PCIAHB_PREFETCH0 0x0
21 #define RCAR_PCIAHB_PREFETCH4 0x1
22 #define RCAR_PCIAHB_PREFETCH8 0x2
23 #define RCAR_PCIAHB_PREFETCH16 0x3
25 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
26 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
32 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dmicrosoft,vmbus.yaml51 ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>;
/openbmc/openpower-proc-control/procedures/phal/
H A Dset_SPI_mux.cpp41 writeRegWithMask(t, P10_ROOT_CTRL8, 0xF0000000, 0xF0000000); in setSPIMux()
/openbmc/linux/arch/arc/boot/dts/
H A Dnsim_700.dts17 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 print-fatal-signal…
33 #clock-cells = <0>;
46 reg = <0xf0000000 0x2000>;
H A Dhaps_hs_idu.dts18 reg = <0x80000000 0x20000000>; /* 512 */
22 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 #clock-cells = <0>;
58 reg = <0xf0000000 0x2000>;
60 interrupts = <0>;
H A Dnsimosci.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
H A Dnsimosci_hs.dts18 /* bootargs = "console=tty0 consoleblank=0"; */
20 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
36 #clock-cells = <0>;
49 reg = <0xf0000000 0x2000>;
59 #clock-cells = <0>;
66 reg = <0xf9000000 0x400>;
73 reg = <0xf9000400 0x14>;
80 reg = <0xf0003000 0x44>;
H A Dhaps_hs.dts19 reg = <0x0 0x80000000 0x0 0x40000000 /* 1 GB low mem */
20 0x1 0x00000000 0x0 0x40000000>; /* 1 GB highmem */
24 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-…
38 ranges = <0x80000000 0x0 0x80000000 0x80000000>;
41 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
71 reg = <0xf0100000 0x2000>;
77 reg = <0xf0102000 0x2000>;
83 reg = <0xf0104000 0x2000>;
89 reg = <0xf0106000 0x2000>;
[all …]
H A Dnsimosci_hs_idu.dts18 …bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 conso…
34 #clock-cells = <0>;
54 reg = <0xf0000000 0x2000>;
56 interrupts = <0>;
65 #clock-cells = <0>;
72 reg = <0xf9000000 0x400>;
79 reg = <0xf9000400 0x14>;
87 reg = <0xf0003000 0x44>;
/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Ddma.h19 #define B43_DMA32_TXCTL 0x00
20 #define B43_DMA32_TXENABLE 0x00000001
21 #define B43_DMA32_TXSUSPEND 0x00000002
22 #define B43_DMA32_TXLOOPBACK 0x00000004
23 #define B43_DMA32_TXFLUSH 0x00000010
24 #define B43_DMA32_TXPARITYDISABLE 0x00000800
25 #define B43_DMA32_TXADDREXT_MASK 0x00030000
27 #define B43_DMA32_TXRING 0x04
28 #define B43_DMA32_TXINDEX 0x08
29 #define B43_DMA32_TXSTATUS 0x0C
[all …]
/openbmc/linux/arch/xtensa/include/asm/
H A Dkmem_layout.h23 #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000)
24 #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000)
28 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
29 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
30 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
31 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000)
37 #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000)
38 #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
39 #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000)
40 #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
[all …]
/openbmc/u-boot/board/xes/xpedite537x/
H A Dxpedite537x.c34 set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); in flash_cs_fixup()
35 set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); in flash_cs_fixup()
45 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); in board_early_init_r()
46 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); in board_early_init_r()
47 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); in board_early_init_r()
48 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); in board_early_init_r()
60 disable_tlb(0); in board_early_init_r()
61 set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
62 (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
64 0, 0, BOOKE_PAGESZ_256M, 1); in board_early_init_r()
[all …]
/openbmc/u-boot/board/xes/xpedite550x/
H A Dxpedite550x.c34 set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); in flash_cs_fixup()
35 set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); in flash_cs_fixup()
45 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); in board_early_init_r()
46 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); in board_early_init_r()
47 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0); in board_early_init_r()
48 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0); in board_early_init_r()
60 disable_tlb(0); in board_early_init_r()
61 set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
62 (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
64 0, 0, BOOKE_PAGESZ_256M, 1); in board_early_init_r()
[all …]
/openbmc/u-boot/board/xes/xpedite520x/
H A Dxpedite520x.c36 set_lbc_br(0, CONFIG_SYS_BR1_PRELIM); in flash_cs_fixup()
37 set_lbc_or(0, CONFIG_SYS_OR1_PRELIM); in flash_cs_fixup()
47 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0); in board_early_init_r()
48 pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0); in board_early_init_r()
60 disable_tlb(0); in board_early_init_r()
61 set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
62 (CONFIG_SYS_FLASH_BASE2 & 0xf0000000), in board_early_init_r()
64 0, 0, BOOKE_PAGESZ_256M, 1); in board_early_init_r()
68 return 0; in board_early_init_r()
79 return 0; in ft_board_setup()
/openbmc/linux/arch/sparc/lib/
H A Dfls.S16 mov 0, %o1
17 sethi %hi(0xffff0000), %g3
22 sethi %hi(0xff000000), %g3
25 sethi %hi(0xf0000000), %g3
29 sra %o0, 0, %o0
32 sethi %hi(0xf0000000), %g3
36 sethi %hi(0xc0000000), %g3
39 sra %o0, 0, %o0
51 sra %o1, 0, %o0
55 sra %o0, 0, %o0
[all …]
/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/openbmc/qemu/tests/tcg/openrisc/
H A Dtest_logic.c8 b = 0x9743; in main()
9 c = 0x2; in main()
10 result = 0x25d0c; in main()
12 ("l.sll %0, %1, %2\n\t" in main()
21 b = 0x9743; in main()
22 result = 0x25d0c; in main()
24 ("l.slli %0, %1, 0x2\n\t" in main()
33 b = 0x7654; in main()
34 c = 0x03; in main()
35 result = 0xeca; in main()
[all …]
/openbmc/linux/arch/arm/mach-spear/
H A Dspear.h18 #define SPEAR_ICM1_2_BASE UL(0xD0000000)
19 #define VA_SPEAR_ICM1_2_BASE IOMEM(0xFD000000)
20 #define SPEAR_ICM1_UART_BASE UL(0xD0000000)
22 #define SPEAR3XX_ICM1_SSP_BASE UL(0xD0100000)
25 #define SPEAR_ICM3_ML1_2_BASE UL(0xF0000000)
26 #define VA_SPEAR6XX_ML_CPU_BASE IOMEM(0xF0000000)
29 #define SPEAR_ICM3_SMI_CTRL_BASE UL(0xFC000000)
30 #define VA_SPEAR_ICM3_SMI_CTRL_BASE IOMEM(0xFC000000)
31 #define SPEAR_ICM3_DMA_BASE UL(0xFC400000)
32 #define SPEAR_ICM3_SYS_CTRL_BASE UL(0xFCA00000)
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-gp.dts13 * internal registers to 0xf1000000 (instead of the default
14 * 0xd0000000). The 0xf1000000 is the default used by the recent,
17 * left internal registers mapped at 0xd0000000. If you are in this
34 memory@0 {
41 * 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
45 reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
46 <0x00000001 0x00000000 0x00000001 0x00000000>;
58 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
59 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
60 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dmvebu-devbus.txt24 0 <physical address of mapping> <size>
46 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
53 ALE[0] to the cycle that the first read data is sampled
63 DEV_OEn assertion. If set to 0 (default),
72 de-assertion of DEV_CSn. If set to 0 (default),
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
90 A[2:0] and Data are kept valid as long as DEV_WEn
97 DEV_A[2:0] and Data are kept valid (do not toggle) for
105 0: False
115 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
[all …]
/openbmc/linux/net/netfilter/ipset/
H A Dpfxlen.c12 E(0x00000000, 0x00000000, 0x00000000, 0x00000000), \
13 E(0x80000000, 0x00000000, 0x00000000, 0x00000000), \
14 E(0xC0000000, 0x00000000, 0x00000000, 0x00000000), \
15 E(0xE0000000, 0x00000000, 0x00000000, 0x00000000), \
16 E(0xF0000000, 0x00000000, 0x00000000, 0x00000000), \
17 E(0xF8000000, 0x00000000, 0x00000000, 0x00000000), \
18 E(0xFC000000, 0x00000000, 0x00000000, 0x00000000), \
19 E(0xFE000000, 0x00000000, 0x00000000, 0x00000000), \
20 E(0xFF000000, 0x00000000, 0x00000000, 0x00000000), \
21 E(0xFF800000, 0x00000000, 0x00000000, 0x00000000), \
[all …]

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