1d2912cb1SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only
2a12ebe16SVineet Gupta/*
3a12ebe16SVineet Gupta * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
4a12ebe16SVineet Gupta */
5a12ebe16SVineet Gupta/dts-v1/;
6a12ebe16SVineet Gupta
72e8cd938SVineet Gupta/include/ "skeleton_hs_idu.dtsi"
8a12ebe16SVineet Gupta
9a12ebe16SVineet Gupta/ {
10618a9cd0SAlexey Brodkin	model = "snps,nsimosci_hs-smp";
11a12ebe16SVineet Gupta	compatible = "snps,nsimosci_hs";
12a12ebe16SVineet Gupta	#address-cells = <1>;
13a12ebe16SVineet Gupta	#size-cells = <1>;
14a12ebe16SVineet Gupta	interrupt-parent = <&core_intc>;
15a12ebe16SVineet Gupta
16a12ebe16SVineet Gupta	chosen {
17a12ebe16SVineet Gupta		/* this is for console on serial */
188ff3afc1SAlexey Brodkin		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=tty0 console=ttyS0,115200n8 consoleblan=0 debug video=640x480-24 print-fatal-signals=1";
19a12ebe16SVineet Gupta	};
20a12ebe16SVineet Gupta
21a12ebe16SVineet Gupta	aliases {
22a12ebe16SVineet Gupta		serial0 = &uart0;
23a12ebe16SVineet Gupta	};
24a12ebe16SVineet Gupta
25a12ebe16SVineet Gupta	fpga {
26a12ebe16SVineet Gupta		compatible = "simple-bus";
27a12ebe16SVineet Gupta		#address-cells = <1>;
28a12ebe16SVineet Gupta		#size-cells = <1>;
29a12ebe16SVineet Gupta
30a12ebe16SVineet Gupta		/* child and parent address space 1:1 mapped */
31a12ebe16SVineet Gupta		ranges;
32a12ebe16SVineet Gupta
33b3d6aba8SVineet Gupta		core_clk: core_clk {
34b3d6aba8SVineet Gupta			#clock-cells = <0>;
35b3d6aba8SVineet Gupta			compatible = "fixed-clock";
36b3d6aba8SVineet Gupta			clock-frequency = <5000000>;
37b3d6aba8SVineet Gupta		};
38b3d6aba8SVineet Gupta
39a12ebe16SVineet Gupta		core_intc: core-interrupt-controller {
40a12ebe16SVineet Gupta			compatible = "snps,archs-intc";
41a12ebe16SVineet Gupta			interrupt-controller;
42a12ebe16SVineet Gupta			#interrupt-cells = <1>;
43a12ebe16SVineet Gupta		};
44a12ebe16SVineet Gupta
45a12ebe16SVineet Gupta		idu_intc: idu-interrupt-controller {
46a12ebe16SVineet Gupta			compatible = "snps,archs-idu-intc";
47a12ebe16SVineet Gupta			interrupt-controller;
48a12ebe16SVineet Gupta			interrupt-parent = <&core_intc>;
49ec69b269SYuriy Kolerov			#interrupt-cells = <1>;
50a12ebe16SVineet Gupta		};
51a12ebe16SVineet Gupta
52a12ebe16SVineet Gupta		uart0: serial@f0000000 {
53a12ebe16SVineet Gupta			compatible = "ns8250";
54a12ebe16SVineet Gupta			reg = <0xf0000000 0x2000>;
55a12ebe16SVineet Gupta			interrupt-parent = <&idu_intc>;
56ec69b269SYuriy Kolerov			interrupts = <0>;
57a12ebe16SVineet Gupta			clock-frequency = <3686400>;
58a12ebe16SVineet Gupta			baud = <115200>;
59a12ebe16SVineet Gupta			reg-shift = <2>;
60a12ebe16SVineet Gupta			reg-io-width = <4>;
61a12ebe16SVineet Gupta			no-loopback-test = <1>;
62a12ebe16SVineet Gupta		};
63a12ebe16SVineet Gupta
64830c6578SAlexey Brodkin		pguclk: pguclk {
65830c6578SAlexey Brodkin			#clock-cells = <0>;
66830c6578SAlexey Brodkin			compatible = "fixed-clock";
67830c6578SAlexey Brodkin			clock-frequency = <25175000>;
68830c6578SAlexey Brodkin		};
69830c6578SAlexey Brodkin
70830c6578SAlexey Brodkin		pgu@f9000000 {
71830c6578SAlexey Brodkin			compatible = "snps,arcpgu";
72a12ebe16SVineet Gupta			reg = <0xf9000000 0x400>;
73830c6578SAlexey Brodkin			clocks = <&pguclk>;
74830c6578SAlexey Brodkin			clock-names = "pxlclk";
75a12ebe16SVineet Gupta		};
76a12ebe16SVineet Gupta
77a12ebe16SVineet Gupta		ps2: ps2@f9001000 {
78a12ebe16SVineet Gupta			compatible = "snps,arc_ps2";
79a12ebe16SVineet Gupta			reg = <0xf9000400 0x14>;
80ec69b269SYuriy Kolerov			interrupts = <3>;
81a12ebe16SVineet Gupta			interrupt-parent = <&idu_intc>;
82a12ebe16SVineet Gupta			interrupt-names = "arc_ps2_irq";
83a12ebe16SVineet Gupta		};
84a12ebe16SVineet Gupta
85a12ebe16SVineet Gupta		eth0: ethernet@f0003000 {
86df420fd6SLada Trimasova			compatible = "ezchip,nps-mgt-enet";
87a12ebe16SVineet Gupta			reg = <0xf0003000 0x44>;
88a12ebe16SVineet Gupta			interrupt-parent = <&idu_intc>;
89ec69b269SYuriy Kolerov			interrupts = <1>;
90a12ebe16SVineet Gupta		};
91a12ebe16SVineet Gupta
92a12ebe16SVineet Gupta		arcpct0: pct {
93a12ebe16SVineet Gupta			compatible = "snps,archs-pct";
94a12ebe16SVineet Gupta			#interrupt-cells = <1>;
95a12ebe16SVineet Gupta			interrupts = <20>;
96a12ebe16SVineet Gupta		};
97a12ebe16SVineet Gupta	};
98a12ebe16SVineet Gupta};
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