1f1883aa7SMax Filippov /* 2f1883aa7SMax Filippov * Kernel virtual memory layout definitions. 3f1883aa7SMax Filippov * 4f1883aa7SMax Filippov * This file is subject to the terms and conditions of the GNU General 5f1883aa7SMax Filippov * Public License. See the file "COPYING" in the main directory of 6f1883aa7SMax Filippov * this archive for more details. 7f1883aa7SMax Filippov * 8f1883aa7SMax Filippov * Copyright (C) 2016 Cadence Design Systems Inc. 9f1883aa7SMax Filippov */ 10f1883aa7SMax Filippov 11f1883aa7SMax Filippov #ifndef _XTENSA_KMEM_LAYOUT_H 12f1883aa7SMax Filippov #define _XTENSA_KMEM_LAYOUT_H 13f1883aa7SMax Filippov 146591685dSMax Filippov #include <asm/core.h> 15f1883aa7SMax Filippov #include <asm/types.h> 16f1883aa7SMax Filippov 17d39af902SMax Filippov #ifdef CONFIG_MMU 18d39af902SMax Filippov 19f1883aa7SMax Filippov /* 20f1883aa7SMax Filippov * Fixed TLB translations in the processor. 21f1883aa7SMax Filippov */ 22f1883aa7SMax Filippov 23d39af902SMax Filippov #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000) 24d39af902SMax Filippov #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000) 25d39af902SMax Filippov 26d39af902SMax Filippov #if defined(CONFIG_XTENSA_KSEG_MMU_V2) 27d39af902SMax Filippov 28f1883aa7SMax Filippov #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) 29f1883aa7SMax Filippov #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) 30f1883aa7SMax Filippov #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) 31d39af902SMax Filippov #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000) 32d39af902SMax Filippov #define XCHAL_KSEG_TLB_WAY 5 33a9f2fc62SMax Filippov #define XCHAL_KIO_TLB_WAY 6 34d39af902SMax Filippov 35d39af902SMax Filippov #elif defined(CONFIG_XTENSA_KSEG_256M) 36d39af902SMax Filippov 37d39af902SMax Filippov #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000) 38d39af902SMax Filippov #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) 39d39af902SMax Filippov #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000) 40d39af902SMax Filippov #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) 41d39af902SMax Filippov #define XCHAL_KSEG_TLB_WAY 6 42a9f2fc62SMax Filippov #define XCHAL_KIO_TLB_WAY 6 43d39af902SMax Filippov 44d39af902SMax Filippov #elif defined(CONFIG_XTENSA_KSEG_512M) 45d39af902SMax Filippov 46d39af902SMax Filippov #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xa0000000) 47d39af902SMax Filippov #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) 48d39af902SMax Filippov #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x20000000) 49d39af902SMax Filippov #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) 50d39af902SMax Filippov #define XCHAL_KSEG_TLB_WAY 6 51a9f2fc62SMax Filippov #define XCHAL_KIO_TLB_WAY 6 52d39af902SMax Filippov 53d39af902SMax Filippov #else 54d39af902SMax Filippov #error Unsupported KSEG configuration 55d39af902SMax Filippov #endif 56d39af902SMax Filippov 57d39af902SMax Filippov #ifdef CONFIG_KSEG_PADDR 58d39af902SMax Filippov #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(CONFIG_KSEG_PADDR) 59d39af902SMax Filippov #else 60f1883aa7SMax Filippov #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000) 61d39af902SMax Filippov #endif 62d39af902SMax Filippov 63d39af902SMax Filippov #if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1) 64d39af902SMax Filippov #error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT 65d39af902SMax Filippov #endif 66d39af902SMax Filippov 67d39af902SMax Filippov #endif 68f1883aa7SMax Filippov 696591685dSMax Filippov /* KIO definition */ 706591685dSMax Filippov 716591685dSMax Filippov #if XCHAL_HAVE_PTP_MMU 726591685dSMax Filippov #define XCHAL_KIO_CACHED_VADDR 0xe0000000 736591685dSMax Filippov #define XCHAL_KIO_BYPASS_VADDR 0xf0000000 746591685dSMax Filippov #define XCHAL_KIO_DEFAULT_PADDR 0xf0000000 756591685dSMax Filippov #else 766591685dSMax Filippov #define XCHAL_KIO_BYPASS_VADDR XCHAL_KIO_PADDR 776591685dSMax Filippov #define XCHAL_KIO_DEFAULT_PADDR 0x90000000 786591685dSMax Filippov #endif 796591685dSMax Filippov #define XCHAL_KIO_SIZE 0x10000000 806591685dSMax Filippov 81*d67ed251SRandy Dunlap #if (!XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY) && defined(CONFIG_USE_OF) 826591685dSMax Filippov #define XCHAL_KIO_PADDR xtensa_get_kio_paddr() 836591685dSMax Filippov #ifndef __ASSEMBLY__ 846591685dSMax Filippov extern unsigned long xtensa_kio_paddr; 856591685dSMax Filippov xtensa_get_kio_paddr(void)866591685dSMax Filippovstatic inline unsigned long xtensa_get_kio_paddr(void) 876591685dSMax Filippov { 886591685dSMax Filippov return xtensa_kio_paddr; 896591685dSMax Filippov } 906591685dSMax Filippov #endif 916591685dSMax Filippov #else 926591685dSMax Filippov #define XCHAL_KIO_PADDR XCHAL_KIO_DEFAULT_PADDR 936591685dSMax Filippov #endif 946591685dSMax Filippov 956591685dSMax Filippov /* KERNEL_STACK definition */ 966591685dSMax Filippov 97c633544aSMax Filippov #ifndef CONFIG_KASAN 98f4431396SMax Filippov #define KERNEL_STACK_SHIFT 13 99c633544aSMax Filippov #else 100c633544aSMax Filippov #define KERNEL_STACK_SHIFT 15 101c633544aSMax Filippov #endif 102f4431396SMax Filippov #define KERNEL_STACK_SIZE (1 << KERNEL_STACK_SHIFT) 103f4431396SMax Filippov 104f1883aa7SMax Filippov #endif 105