1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */
258619b14SKalle Valo #ifndef B43_DMA_H_
358619b14SKalle Valo #define B43_DMA_H_
458619b14SKalle Valo
558619b14SKalle Valo #include <linux/err.h>
658619b14SKalle Valo
758619b14SKalle Valo #include "b43.h"
858619b14SKalle Valo
958619b14SKalle Valo
1058619b14SKalle Valo /* DMA-Interrupt reasons. */
1158619b14SKalle Valo #define B43_DMAIRQ_FATALMASK ((1 << 10) | (1 << 11) | (1 << 12) \
1258619b14SKalle Valo | (1 << 14) | (1 << 15))
1358619b14SKalle Valo #define B43_DMAIRQ_RDESC_UFLOW (1 << 13)
1458619b14SKalle Valo #define B43_DMAIRQ_RX_DONE (1 << 16)
1558619b14SKalle Valo
1658619b14SKalle Valo /*** 32-bit DMA Engine. ***/
1758619b14SKalle Valo
1858619b14SKalle Valo /* 32-bit DMA controller registers. */
1958619b14SKalle Valo #define B43_DMA32_TXCTL 0x00
2058619b14SKalle Valo #define B43_DMA32_TXENABLE 0x00000001
2158619b14SKalle Valo #define B43_DMA32_TXSUSPEND 0x00000002
2258619b14SKalle Valo #define B43_DMA32_TXLOOPBACK 0x00000004
2358619b14SKalle Valo #define B43_DMA32_TXFLUSH 0x00000010
2458619b14SKalle Valo #define B43_DMA32_TXPARITYDISABLE 0x00000800
2558619b14SKalle Valo #define B43_DMA32_TXADDREXT_MASK 0x00030000
2658619b14SKalle Valo #define B43_DMA32_TXADDREXT_SHIFT 16
2758619b14SKalle Valo #define B43_DMA32_TXRING 0x04
2858619b14SKalle Valo #define B43_DMA32_TXINDEX 0x08
2958619b14SKalle Valo #define B43_DMA32_TXSTATUS 0x0C
3058619b14SKalle Valo #define B43_DMA32_TXDPTR 0x00000FFF
3158619b14SKalle Valo #define B43_DMA32_TXSTATE 0x0000F000
3258619b14SKalle Valo #define B43_DMA32_TXSTAT_DISABLED 0x00000000
3358619b14SKalle Valo #define B43_DMA32_TXSTAT_ACTIVE 0x00001000
3458619b14SKalle Valo #define B43_DMA32_TXSTAT_IDLEWAIT 0x00002000
3558619b14SKalle Valo #define B43_DMA32_TXSTAT_STOPPED 0x00003000
3658619b14SKalle Valo #define B43_DMA32_TXSTAT_SUSP 0x00004000
3758619b14SKalle Valo #define B43_DMA32_TXERROR 0x000F0000
3858619b14SKalle Valo #define B43_DMA32_TXERR_NOERR 0x00000000
3958619b14SKalle Valo #define B43_DMA32_TXERR_PROT 0x00010000
4058619b14SKalle Valo #define B43_DMA32_TXERR_UNDERRUN 0x00020000
4158619b14SKalle Valo #define B43_DMA32_TXERR_BUFREAD 0x00030000
4258619b14SKalle Valo #define B43_DMA32_TXERR_DESCREAD 0x00040000
4358619b14SKalle Valo #define B43_DMA32_TXACTIVE 0xFFF00000
4458619b14SKalle Valo #define B43_DMA32_RXCTL 0x10
4558619b14SKalle Valo #define B43_DMA32_RXENABLE 0x00000001
4658619b14SKalle Valo #define B43_DMA32_RXFROFF_MASK 0x000000FE
4758619b14SKalle Valo #define B43_DMA32_RXFROFF_SHIFT 1
4858619b14SKalle Valo #define B43_DMA32_RXDIRECTFIFO 0x00000100
4958619b14SKalle Valo #define B43_DMA32_RXPARITYDISABLE 0x00000800
5058619b14SKalle Valo #define B43_DMA32_RXADDREXT_MASK 0x00030000
5158619b14SKalle Valo #define B43_DMA32_RXADDREXT_SHIFT 16
5258619b14SKalle Valo #define B43_DMA32_RXRING 0x14
5358619b14SKalle Valo #define B43_DMA32_RXINDEX 0x18
5458619b14SKalle Valo #define B43_DMA32_RXSTATUS 0x1C
5558619b14SKalle Valo #define B43_DMA32_RXDPTR 0x00000FFF
5658619b14SKalle Valo #define B43_DMA32_RXSTATE 0x0000F000
5758619b14SKalle Valo #define B43_DMA32_RXSTAT_DISABLED 0x00000000
5858619b14SKalle Valo #define B43_DMA32_RXSTAT_ACTIVE 0x00001000
5958619b14SKalle Valo #define B43_DMA32_RXSTAT_IDLEWAIT 0x00002000
6058619b14SKalle Valo #define B43_DMA32_RXSTAT_STOPPED 0x00003000
6158619b14SKalle Valo #define B43_DMA32_RXERROR 0x000F0000
6258619b14SKalle Valo #define B43_DMA32_RXERR_NOERR 0x00000000
6358619b14SKalle Valo #define B43_DMA32_RXERR_PROT 0x00010000
6458619b14SKalle Valo #define B43_DMA32_RXERR_OVERFLOW 0x00020000
6558619b14SKalle Valo #define B43_DMA32_RXERR_BUFWRITE 0x00030000
6658619b14SKalle Valo #define B43_DMA32_RXERR_DESCREAD 0x00040000
6758619b14SKalle Valo #define B43_DMA32_RXACTIVE 0xFFF00000
6858619b14SKalle Valo
6958619b14SKalle Valo /* 32-bit DMA descriptor. */
7058619b14SKalle Valo struct b43_dmadesc32 {
7158619b14SKalle Valo __le32 control;
7258619b14SKalle Valo __le32 address;
7358619b14SKalle Valo } __packed;
7458619b14SKalle Valo #define B43_DMA32_DCTL_BYTECNT 0x00001FFF
7558619b14SKalle Valo #define B43_DMA32_DCTL_ADDREXT_MASK 0x00030000
7658619b14SKalle Valo #define B43_DMA32_DCTL_ADDREXT_SHIFT 16
7758619b14SKalle Valo #define B43_DMA32_DCTL_DTABLEEND 0x10000000
7858619b14SKalle Valo #define B43_DMA32_DCTL_IRQ 0x20000000
7958619b14SKalle Valo #define B43_DMA32_DCTL_FRAMEEND 0x40000000
8058619b14SKalle Valo #define B43_DMA32_DCTL_FRAMESTART 0x80000000
8158619b14SKalle Valo
8258619b14SKalle Valo /*** 64-bit DMA Engine. ***/
8358619b14SKalle Valo
8458619b14SKalle Valo /* 64-bit DMA controller registers. */
8558619b14SKalle Valo #define B43_DMA64_TXCTL 0x00
8658619b14SKalle Valo #define B43_DMA64_TXENABLE 0x00000001
8758619b14SKalle Valo #define B43_DMA64_TXSUSPEND 0x00000002
8858619b14SKalle Valo #define B43_DMA64_TXLOOPBACK 0x00000004
8958619b14SKalle Valo #define B43_DMA64_TXFLUSH 0x00000010
9058619b14SKalle Valo #define B43_DMA64_TXPARITYDISABLE 0x00000800
9158619b14SKalle Valo #define B43_DMA64_TXADDREXT_MASK 0x00030000
9258619b14SKalle Valo #define B43_DMA64_TXADDREXT_SHIFT 16
9358619b14SKalle Valo #define B43_DMA64_TXINDEX 0x04
9458619b14SKalle Valo #define B43_DMA64_TXRINGLO 0x08
9558619b14SKalle Valo #define B43_DMA64_TXRINGHI 0x0C
9658619b14SKalle Valo #define B43_DMA64_TXSTATUS 0x10
9758619b14SKalle Valo #define B43_DMA64_TXSTATDPTR 0x00001FFF
9858619b14SKalle Valo #define B43_DMA64_TXSTAT 0xF0000000
9958619b14SKalle Valo #define B43_DMA64_TXSTAT_DISABLED 0x00000000
10058619b14SKalle Valo #define B43_DMA64_TXSTAT_ACTIVE 0x10000000
10158619b14SKalle Valo #define B43_DMA64_TXSTAT_IDLEWAIT 0x20000000
10258619b14SKalle Valo #define B43_DMA64_TXSTAT_STOPPED 0x30000000
10358619b14SKalle Valo #define B43_DMA64_TXSTAT_SUSP 0x40000000
10458619b14SKalle Valo #define B43_DMA64_TXERROR 0x14
10558619b14SKalle Valo #define B43_DMA64_TXERRDPTR 0x0001FFFF
10658619b14SKalle Valo #define B43_DMA64_TXERR 0xF0000000
10758619b14SKalle Valo #define B43_DMA64_TXERR_NOERR 0x00000000
10858619b14SKalle Valo #define B43_DMA64_TXERR_PROT 0x10000000
10958619b14SKalle Valo #define B43_DMA64_TXERR_UNDERRUN 0x20000000
11058619b14SKalle Valo #define B43_DMA64_TXERR_TRANSFER 0x30000000
11158619b14SKalle Valo #define B43_DMA64_TXERR_DESCREAD 0x40000000
11258619b14SKalle Valo #define B43_DMA64_TXERR_CORE 0x50000000
11358619b14SKalle Valo #define B43_DMA64_RXCTL 0x20
11458619b14SKalle Valo #define B43_DMA64_RXENABLE 0x00000001
11558619b14SKalle Valo #define B43_DMA64_RXFROFF_MASK 0x000000FE
11658619b14SKalle Valo #define B43_DMA64_RXFROFF_SHIFT 1
11758619b14SKalle Valo #define B43_DMA64_RXDIRECTFIFO 0x00000100
11858619b14SKalle Valo #define B43_DMA64_RXPARITYDISABLE 0x00000800
11958619b14SKalle Valo #define B43_DMA64_RXADDREXT_MASK 0x00030000
12058619b14SKalle Valo #define B43_DMA64_RXADDREXT_SHIFT 16
12158619b14SKalle Valo #define B43_DMA64_RXINDEX 0x24
12258619b14SKalle Valo #define B43_DMA64_RXRINGLO 0x28
12358619b14SKalle Valo #define B43_DMA64_RXRINGHI 0x2C
12458619b14SKalle Valo #define B43_DMA64_RXSTATUS 0x30
12558619b14SKalle Valo #define B43_DMA64_RXSTATDPTR 0x00001FFF
12658619b14SKalle Valo #define B43_DMA64_RXSTAT 0xF0000000
12758619b14SKalle Valo #define B43_DMA64_RXSTAT_DISABLED 0x00000000
12858619b14SKalle Valo #define B43_DMA64_RXSTAT_ACTIVE 0x10000000
12958619b14SKalle Valo #define B43_DMA64_RXSTAT_IDLEWAIT 0x20000000
13058619b14SKalle Valo #define B43_DMA64_RXSTAT_STOPPED 0x30000000
13158619b14SKalle Valo #define B43_DMA64_RXSTAT_SUSP 0x40000000
13258619b14SKalle Valo #define B43_DMA64_RXERROR 0x34
13358619b14SKalle Valo #define B43_DMA64_RXERRDPTR 0x0001FFFF
13458619b14SKalle Valo #define B43_DMA64_RXERR 0xF0000000
13558619b14SKalle Valo #define B43_DMA64_RXERR_NOERR 0x00000000
13658619b14SKalle Valo #define B43_DMA64_RXERR_PROT 0x10000000
13758619b14SKalle Valo #define B43_DMA64_RXERR_UNDERRUN 0x20000000
13858619b14SKalle Valo #define B43_DMA64_RXERR_TRANSFER 0x30000000
13958619b14SKalle Valo #define B43_DMA64_RXERR_DESCREAD 0x40000000
14058619b14SKalle Valo #define B43_DMA64_RXERR_CORE 0x50000000
14158619b14SKalle Valo
14258619b14SKalle Valo /* 64-bit DMA descriptor. */
14358619b14SKalle Valo struct b43_dmadesc64 {
14458619b14SKalle Valo __le32 control0;
14558619b14SKalle Valo __le32 control1;
14658619b14SKalle Valo __le32 address_low;
14758619b14SKalle Valo __le32 address_high;
14858619b14SKalle Valo } __packed;
14958619b14SKalle Valo #define B43_DMA64_DCTL0_DTABLEEND 0x10000000
15058619b14SKalle Valo #define B43_DMA64_DCTL0_IRQ 0x20000000
15158619b14SKalle Valo #define B43_DMA64_DCTL0_FRAMEEND 0x40000000
15258619b14SKalle Valo #define B43_DMA64_DCTL0_FRAMESTART 0x80000000
15358619b14SKalle Valo #define B43_DMA64_DCTL1_BYTECNT 0x00001FFF
15458619b14SKalle Valo #define B43_DMA64_DCTL1_ADDREXT_MASK 0x00030000
15558619b14SKalle Valo #define B43_DMA64_DCTL1_ADDREXT_SHIFT 16
15658619b14SKalle Valo
15758619b14SKalle Valo struct b43_dmadesc_generic {
15858619b14SKalle Valo union {
15958619b14SKalle Valo struct b43_dmadesc32 dma32;
16058619b14SKalle Valo struct b43_dmadesc64 dma64;
16158619b14SKalle Valo } __packed;
16258619b14SKalle Valo } __packed;
16358619b14SKalle Valo
16458619b14SKalle Valo /* Misc DMA constants */
16558619b14SKalle Valo #define B43_DMA32_RINGMEMSIZE 4096
16658619b14SKalle Valo #define B43_DMA64_RINGMEMSIZE 8192
16758619b14SKalle Valo /* Offset of frame with actual data */
16858619b14SKalle Valo #define B43_DMA0_RX_FW598_FO 38
16958619b14SKalle Valo #define B43_DMA0_RX_FW351_FO 30
17058619b14SKalle Valo
17158619b14SKalle Valo /* DMA engine tuning knobs */
17258619b14SKalle Valo #define B43_TXRING_SLOTS 256
17358619b14SKalle Valo #define B43_RXRING_SLOTS 256
17458619b14SKalle Valo #define B43_DMA0_RX_FW598_BUFSIZE (B43_DMA0_RX_FW598_FO + IEEE80211_MAX_FRAME_LEN)
17558619b14SKalle Valo #define B43_DMA0_RX_FW351_BUFSIZE (B43_DMA0_RX_FW351_FO + IEEE80211_MAX_FRAME_LEN)
17658619b14SKalle Valo
17758619b14SKalle Valo /* Pointer poison */
17858619b14SKalle Valo #define B43_DMA_PTR_POISON ((void *)ERR_PTR(-ENOMEM))
17958619b14SKalle Valo #define b43_dma_ptr_is_poisoned(ptr) (unlikely((ptr) == B43_DMA_PTR_POISON))
18058619b14SKalle Valo
18158619b14SKalle Valo
18258619b14SKalle Valo struct sk_buff;
18358619b14SKalle Valo struct b43_private;
18458619b14SKalle Valo struct b43_txstatus;
18558619b14SKalle Valo
18658619b14SKalle Valo struct b43_dmadesc_meta {
18758619b14SKalle Valo /* The kernel DMA-able buffer. */
18858619b14SKalle Valo struct sk_buff *skb;
18958619b14SKalle Valo /* DMA base bus-address of the descriptor buffer. */
19058619b14SKalle Valo dma_addr_t dmaaddr;
19158619b14SKalle Valo /* ieee80211 TX status. Only used once per 802.11 frag. */
19258619b14SKalle Valo bool is_last_fragment;
19358619b14SKalle Valo };
19458619b14SKalle Valo
19558619b14SKalle Valo struct b43_dmaring;
19658619b14SKalle Valo
19758619b14SKalle Valo /* Lowlevel DMA operations that differ between 32bit and 64bit DMA. */
19858619b14SKalle Valo struct b43_dma_ops {
19958619b14SKalle Valo struct b43_dmadesc_generic *(*idx2desc) (struct b43_dmaring * ring,
20058619b14SKalle Valo int slot,
20158619b14SKalle Valo struct b43_dmadesc_meta **
20258619b14SKalle Valo meta);
20358619b14SKalle Valo void (*fill_descriptor) (struct b43_dmaring * ring,
20458619b14SKalle Valo struct b43_dmadesc_generic * desc,
20558619b14SKalle Valo dma_addr_t dmaaddr, u16 bufsize, int start,
20658619b14SKalle Valo int end, int irq);
20758619b14SKalle Valo void (*poke_tx) (struct b43_dmaring * ring, int slot);
20858619b14SKalle Valo void (*tx_suspend) (struct b43_dmaring * ring);
20958619b14SKalle Valo void (*tx_resume) (struct b43_dmaring * ring);
21058619b14SKalle Valo int (*get_current_rxslot) (struct b43_dmaring * ring);
21158619b14SKalle Valo void (*set_current_rxslot) (struct b43_dmaring * ring, int slot);
21258619b14SKalle Valo };
21358619b14SKalle Valo
21458619b14SKalle Valo enum b43_dmatype {
21558619b14SKalle Valo B43_DMA_30BIT = 30,
21658619b14SKalle Valo B43_DMA_32BIT = 32,
21758619b14SKalle Valo B43_DMA_64BIT = 64,
21858619b14SKalle Valo };
21958619b14SKalle Valo
22058619b14SKalle Valo enum b43_addrtype {
22158619b14SKalle Valo B43_DMA_ADDR_LOW,
22258619b14SKalle Valo B43_DMA_ADDR_HIGH,
22358619b14SKalle Valo B43_DMA_ADDR_EXT,
22458619b14SKalle Valo };
22558619b14SKalle Valo
22658619b14SKalle Valo struct b43_dmaring {
22758619b14SKalle Valo /* Lowlevel DMA ops. */
22858619b14SKalle Valo const struct b43_dma_ops *ops;
22958619b14SKalle Valo /* Kernel virtual base address of the ring memory. */
23058619b14SKalle Valo void *descbase;
23158619b14SKalle Valo /* Meta data about all descriptors. */
23258619b14SKalle Valo struct b43_dmadesc_meta *meta;
23358619b14SKalle Valo /* Cache of TX headers for each TX frame.
23458619b14SKalle Valo * This is to avoid an allocation on each TX.
23558619b14SKalle Valo * This is NULL for an RX ring.
23658619b14SKalle Valo */
23758619b14SKalle Valo u8 *txhdr_cache;
23858619b14SKalle Valo /* (Unadjusted) DMA base bus-address of the ring memory. */
23958619b14SKalle Valo dma_addr_t dmabase;
24058619b14SKalle Valo /* Number of descriptor slots in the ring. */
24158619b14SKalle Valo int nr_slots;
24258619b14SKalle Valo /* Number of used descriptor slots. */
24358619b14SKalle Valo int used_slots;
24458619b14SKalle Valo /* Currently used slot in the ring. */
24558619b14SKalle Valo int current_slot;
24658619b14SKalle Valo /* Frameoffset in octets. */
24758619b14SKalle Valo u32 frameoffset;
24858619b14SKalle Valo /* Descriptor buffer size. */
24958619b14SKalle Valo u16 rx_buffersize;
25058619b14SKalle Valo /* The MMIO base register of the DMA controller. */
25158619b14SKalle Valo u16 mmio_base;
25258619b14SKalle Valo /* DMA controller index number (0-5). */
25358619b14SKalle Valo int index;
25458619b14SKalle Valo /* Boolean. Is this a TX ring? */
25558619b14SKalle Valo bool tx;
25658619b14SKalle Valo /* The type of DMA engine used. */
25758619b14SKalle Valo enum b43_dmatype type;
25858619b14SKalle Valo /* Boolean. Is this ring stopped at ieee80211 level? */
25958619b14SKalle Valo bool stopped;
26058619b14SKalle Valo /* The QOS priority assigned to this ring. Only used for TX rings.
26158619b14SKalle Valo * This is the mac80211 "queue" value. */
26258619b14SKalle Valo u8 queue_prio;
26358619b14SKalle Valo struct b43_wldev *dev;
26458619b14SKalle Valo #ifdef CONFIG_B43_DEBUG
26558619b14SKalle Valo /* Maximum number of used slots. */
26658619b14SKalle Valo int max_used_slots;
26758619b14SKalle Valo /* Last time we injected a ring overflow. */
26858619b14SKalle Valo unsigned long last_injected_overflow;
26958619b14SKalle Valo /* Statistics: Number of successfully transmitted packets */
27058619b14SKalle Valo u64 nr_succeed_tx_packets;
27158619b14SKalle Valo /* Statistics: Number of failed TX packets */
27258619b14SKalle Valo u64 nr_failed_tx_packets;
27358619b14SKalle Valo /* Statistics: Total number of TX plus all retries. */
27458619b14SKalle Valo u64 nr_total_packet_tries;
27558619b14SKalle Valo #endif /* CONFIG_B43_DEBUG */
27658619b14SKalle Valo };
27758619b14SKalle Valo
b43_dma_read(struct b43_dmaring * ring,u16 offset)27858619b14SKalle Valo static inline u32 b43_dma_read(struct b43_dmaring *ring, u16 offset)
27958619b14SKalle Valo {
28058619b14SKalle Valo return b43_read32(ring->dev, ring->mmio_base + offset);
28158619b14SKalle Valo }
28258619b14SKalle Valo
b43_dma_write(struct b43_dmaring * ring,u16 offset,u32 value)28358619b14SKalle Valo static inline void b43_dma_write(struct b43_dmaring *ring, u16 offset, u32 value)
28458619b14SKalle Valo {
28558619b14SKalle Valo b43_write32(ring->dev, ring->mmio_base + offset, value);
28658619b14SKalle Valo }
28758619b14SKalle Valo
28858619b14SKalle Valo int b43_dma_init(struct b43_wldev *dev);
28958619b14SKalle Valo void b43_dma_free(struct b43_wldev *dev);
29058619b14SKalle Valo
29158619b14SKalle Valo void b43_dma_tx_suspend(struct b43_wldev *dev);
29258619b14SKalle Valo void b43_dma_tx_resume(struct b43_wldev *dev);
29358619b14SKalle Valo
29458619b14SKalle Valo int b43_dma_tx(struct b43_wldev *dev,
29558619b14SKalle Valo struct sk_buff *skb);
29658619b14SKalle Valo void b43_dma_handle_txstatus(struct b43_wldev *dev,
29758619b14SKalle Valo const struct b43_txstatus *status);
29858619b14SKalle Valo
29958619b14SKalle Valo void b43_dma_handle_rx_overflow(struct b43_dmaring *ring);
30058619b14SKalle Valo
30158619b14SKalle Valo void b43_dma_rx(struct b43_dmaring *ring);
30258619b14SKalle Valo
30358619b14SKalle Valo void b43_dma_direct_fifo_rx(struct b43_wldev *dev,
30458619b14SKalle Valo unsigned int engine_index, bool enable);
30558619b14SKalle Valo
30658619b14SKalle Valo #endif /* B43_DMA_H_ */
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