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/openbmc/linux/drivers/s390/char/
H A Ddefkeymap.c15 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
16 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
17 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
18 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
19 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
20 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
21 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
22 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000, 0xf000,
23 0xf020, 0xf000, 0xf0e2, 0xf0e4, 0xf0e0, 0xf0e1, 0xf0e3, 0xf0e5,
24 0xf0e7, 0xf0f1, 0xf0a2, 0xf02e, 0xf03c, 0xf028, 0xf02b, 0xf07c,
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm5102.c41 static DECLARE_TLV_DB_SCALE(ana_tlv, 0, 100, 0);
42 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
43 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
44 static DECLARE_TLV_DB_SCALE(noise_tlv, -13200, 600, 0);
45 static DECLARE_TLV_DB_SCALE(ng_tlv, -10200, 600, 0);
48 { .type = WMFW_ADSP2_PM, .base = 0x100000 },
49 { .type = WMFW_ADSP2_ZM, .base = 0x180000 },
50 { .type = WMFW_ADSP2_XM, .base = 0x190000 },
51 { .type = WMFW_ADSP2_YM, .base = 0x1a8000 },
55 { 0x3000, 0x2225 },
[all …]
/openbmc/qemu/disas/
H A Dm68k.c35 fields is contiguous. We number the bits with 0 being the most significant
67 /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
74 very large number (e.g., given the exp_bias of 0x3fff and a 64
143 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
165 #define _m68k_undef 0
166 #define m68000 0x001
168 #define m68010 0x002
169 #define m68020 0x004
170 #define m68030 0x008
173 #define m68040 0x010
[all …]
/openbmc/linux/arch/s390/kernel/
H A Drelocate_kernel.S25 * 0xf000 is a page_mask
30 basr %r13,0 # base address
34 lg %r5,0(%r2) # read another word for indirection page
36 tml %r5,0x1 # is it a destination page?
39 nill %r6,0xf000 # mask it out and...
42 tml %r5,0x2 # is it a indirection page?
44 nill %r5,0xf000 # YES, mask out,
48 tml %r5,0x4 # is it the done indicator?
52 tml %r5,0x8 # it should be a source indicator...
55 nill %r8,0xf000 # masking
[all …]
/openbmc/linux/fs/nls/
H A Dnls_ucs2_utils.h36 #define UNI_ASTERISK ((__u16)('*' + 0xF000))
37 #define UNI_QUESTION ((__u16)('?' + 0xF000))
38 #define UNI_COLON ((__u16)(':' + 0xF000))
39 #define UNI_GRTRTHAN ((__u16)('>' + 0xF000))
40 #define UNI_LESSTHAN ((__u16)('<' + 0xF000))
41 #define UNI_PIPE ((__u16)('|' + 0xF000))
42 #define UNI_SLASH ((__u16)('\\' + 0xF000))
83 * < 0: First string is less than second
84 * = 0: Strings are equal
85 * > 0: First string is greater than second
[all …]
/openbmc/qemu/docs/specs/
H A Dppc-spapr-hcalls.rst17 All those hypercalls start at hcall number 0xf000 which correspond
20 ``H_RTAS (0xf000)``
35 ``r3``: ``H_RTAS (0xf000)``
46 ``H_LOGICAL_MEMOP (0xf001)``
70 ``r3 ``: ``H_LOGICAL_MEMOP (0xf001)``
79 ``0`` = 1 byte
91 ``0``: copy
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_DynamicBBPowerSaving.c19 pDM_PSTable->Rssi_val_min = 0; in odm_DynamicBBPowerSavingInit()
20 pDM_PSTable->initialize = 0; in odm_DynamicBBPowerSavingInit()
35 if (pDM_PSTable->initialize == 0) { in ODM_RF_Saving()
37 pDM_PSTable->Reg874 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x874, bMaskDWord)&0x1CC000)>>14; in ODM_RF_Saving()
38 pDM_PSTable->RegC70 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xc70, bMaskDWord)&BIT3)>>3; in ODM_RF_Saving()
39 pDM_PSTable->Reg85C = (PHY_QueryBBReg(pDM_Odm->Adapter, 0x85c, bMaskDWord)&0xFF000000)>>24; in ODM_RF_Saving()
40 pDM_PSTable->RegA74 = (PHY_QueryBBReg(pDM_Odm->Adapter, 0xa74, bMaskDWord)&0xF000)>>12; in ODM_RF_Saving()
41 /* Reg818 = PHY_QueryBBReg(padapter, 0x818, bMaskDWord); */ in ODM_RF_Saving()
46 if (pDM_Odm->RSSI_Min != 0xFF) { in ODM_RF_Saving()
65 PHY_SetBBReg(pDM_Odm->Adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */ in ODM_RF_Saving()
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dmach-crag6410-module.c41 [0] = {
44 .bus_num = 0,
45 .chip_select = 0,
53 [0] = {
56 .bus_num = 0,
57 .chip_select = 0,
78 { WM5100_MICDET_MICBIAS3, 0, 0 },
83 0,
84 0,
85 0,
[all …]
/openbmc/linux/include/linux/mfd/wm8350/
H A Dgpio.h16 #define WM8350_GPIO_DEBOUNCE 0x80
17 #define WM8350_GPIO_PIN_PULL_UP_CONTROL 0x81
18 #define WM8350_GPIO_PULL_DOWN_CONTROL 0x82
19 #define WM8350_GPIO_INT_MODE 0x83
20 #define WM8350_GPIO_CONTROL 0x85
21 #define WM8350_GPIO_CONFIGURATION_I_O 0x86
22 #define WM8350_GPIO_PIN_POLARITY_TYPE 0x87
23 #define WM8350_GPIO_FUNCTION_SELECT_1 0x8C
24 #define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
25 #define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
[all …]
/openbmc/linux/drivers/mfd/
H A Dcs47l90-tables.c18 { 0x8A, 0x5555 },
19 { 0x8A, 0xAAAA },
20 { 0x4CF, 0x0700 },
21 { 0x171, 0x0003 },
22 { 0x101, 0x0444 },
23 { 0x159, 0x0002 },
24 { 0x120, 0x0444 },
25 { 0x1D1, 0x0004 },
26 { 0x1E0, 0xC084 },
27 { 0x159, 0x0000 },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c78 return (rptr & 0x3fffc) >> 2; in cik_sdma_get_rptr()
99 return (RREG32(reg) & 0x3fffc) >> 2; in cik_sdma_get_wptr()
120 WREG32(reg, (ring->wptr << 2) & 0x3fffc); in cik_sdma_set_wptr()
136 u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf; in cik_sdma_ring_ib_execute()
143 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); in cik_sdma_ring_ib_execute()
144 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_sdma_ring_ib_execute()
152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); in cik_sdma_ring_ib_execute()
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); in cik_sdma_ring_ib_execute()
154 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ in cik_sdma_ring_ib_execute()
181 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); in cik_sdma_hdp_flush_ring_emit()
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dhwtstamp.h19 /* Offset 0x00: PTP EtherType */
20 #define MV88E6XXX_PTP_ETHERTYPE 0x00
22 /* Offset 0x01: Message Type Timestamp Enables */
23 #define MV88E6XXX_PTP_MSGTYPE 0x01
24 #define MV88E6XXX_PTP_MSGTYPE_SYNC 0x0001
25 #define MV88E6XXX_PTP_MSGTYPE_DELAY_REQ 0x0002
26 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_REQ 0x0004
27 #define MV88E6XXX_PTP_MSGTYPE_PDLAY_RES 0x0008
28 #define MV88E6XXX_PTP_MSGTYPE_ALL_EVENT 0x000f
30 /* Offset 0x02: Timestamp Arrival Capture Pointers */
[all …]
H A Dglobal1.h16 /* Offset 0x00: Switch Global Status Register */
17 #define MV88E6XXX_G1_STS 0x00
18 #define MV88E6352_G1_STS_PPU_STATE 0x8000
19 #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000
20 #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000
21 #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000
22 #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000
23 #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000
24 #define MV88E6XXX_G1_STS_INIT_READY 0x0800
34 #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0
[all …]
/openbmc/u-boot/arch/m68k/cpu/mcf547x_8x/
H A Dcpu_init.c35 out_be32(&xlbarb->adrto, 0x2000); in cpu_init_f()
36 out_be32(&xlbarb->datto, 0x2500); in cpu_init_f()
37 out_be32(&xlbarb->busto, 0x3000); in cpu_init_f()
42 out_be32(&xlbarb->prien, 0xff); in cpu_init_f()
43 out_be32(&xlbarb->pri, 0); in cpu_init_f()
98 return (0); in cpu_init_r()
104 u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40); in uart_port_conf()
108 case 0: in uart_port_conf()
122 clrbits_8(pscsicr, 0x07); in uart_port_conf()
133 setbits_be16(&gpio->par_feci2cirq, 0xf000); in fecpin_setclear()
[all …]
/openbmc/linux/include/uapi/linux/surface_aggregator/
H A Ddtx.h19 #define SDTX_CATEGORY_STATUS 0x0000
20 #define SDTX_CATEGORY_RUNTIME_ERROR 0x1000
21 #define SDTX_CATEGORY_HARDWARE_ERROR 0x2000
22 #define SDTX_CATEGORY_UNKNOWN 0xf000
24 #define SDTX_CATEGORY_MASK 0xf000
35 #define SDTX_LATCH_CLOSED SDTX_STATUS(0x00)
36 #define SDTX_LATCH_OPENED SDTX_STATUS(0x01)
39 #define SDTX_BASE_DETACHED SDTX_STATUS(0x00)
40 #define SDTX_BASE_ATTACHED SDTX_STATUS(0x01)
43 #define SDTX_DETACH_NOT_FEASIBLE SDTX_ERR_RT(0x01)
[all …]
/openbmc/linux/arch/x86/realmode/rm/
H A Dreboot.S17 * This code is called with the restart type (0 = BIOS, 1 = APM) in
87 * actual BIOS entry point, anyway (that is at 0xfffffff0).
99 andl $0x00000011, %edx
100 orl $0x60000000, %edx
104 testl $0x60000000, %edx /* If no cache bits -> no wbinvd */
108 andb $0x10, %dl
116 movw $0x1000, %ax
118 movw $0xf000, %sp
119 movw $0x5307, %ax
120 movw $0x0001, %bx
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-armada8k/
H A Dcache_llc.h12 #define MVEBU_A8K_REGS_BASE_MSB 0xf000
13 #define LLC_BASE_ADDR 0x8000
14 #define LLC_CACHE_SYNC 0x700
15 #define LLC_CACHE_SYNC_COMPLETE 0x730
16 #define LLC_FLUSH_BY_WAY 0x7fc
17 #define LLC_WAY_MASK 0xffffffff
18 #define LLC_CACHE_SYNC_MASK 0x1
/openbmc/linux/drivers/tty/serial/
H A Dmux.c9 ** This Driver currently only supports the console (port 0) on the MUX.
31 #define MUX_OFFSET 0x800
32 #define MUX_LINE_OFFSET 0x80
37 #define IO_DATA_REG_OFFSET 0x3c
38 #define IO_DCOUNT_REG_OFFSET 0x40
40 #define MUX_EOFIFO(status) ((status & 0xF000) == 0xF000)
41 #define MUX_STATUS(status) ((status & 0xF000) == 0x8000)
42 #define MUX_BREAK(status) ((status & 0xF000) == 0x2000)
57 .minor = 0,
86 if(dev->id.hversion == 0x15) in get_mux_port_count()
[all …]
/openbmc/linux/drivers/input/touchscreen/
H A Dmk712.c48 static unsigned int mk712_io = 0x260; /* Also 0x200, 0x208, 0x300 */
49 module_param_hw_named(io, mk712_io, uint, ioport, 0);
53 module_param_hw_named(irq, mk712_irq, uint, irq, 0);
57 #define MK712_STATUS 0
64 #define MK712_STATUS_TOUCH 0x10
65 #define MK712_CONVERSION_COMPLETE 0x80
68 #define MK712_ENABLE_INT 0x01
69 #define MK712_INT_ON_CONVERSION_COMPLETE 0x02
70 #define MK712_INT_ON_CHANGE_IN_TOUCH_STATUS 0x04
71 #define MK712_ENABLE_PERIODIC_CONVERSIONS 0x10
[all …]
/openbmc/u-boot/arch/arm/include/asm/
H A Dopcodes-virt.h12 0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \
13 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \
17 0xE160006E, \
18 0xF3DE8F00 \
22 0xE12EF300 | regnum, \
23 0xF3808E30 | (regnum << 16) \
/openbmc/linux/arch/arm/include/asm/
H A Dopcodes-virt.h12 0xE1400070 | (((imm16) & 0xFFF0) << 4) | ((imm16) & 0x000F), \
13 0xF7E08000 | (((imm16) & 0xF000) << 4) | ((imm16) & 0x0FFF) \
17 0xE160006E, \
18 0xF3DE8F00 \
22 0xE12EF300 | regnum, \
23 0xF3808E30 | (regnum << 16) \
/openbmc/linux/include/linux/
H A Dsw842.h5 #define SW842_MEM_COMPRESS (0xf000)
/openbmc/qemu/tests/tcg/aarch64/system/
H A Dsemiconsole.c12 #define SYS_READC 0x7
18 asm("hlt 0xf000" in __semi_call()
33 c = __semi_call(SYS_READC, 0); in main()
37 return 0; in main()

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