12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 2a935c052SVivien Didelot /* 3a935c052SVivien Didelot * Marvell 88E6xxx Switch Global (1) Registers support 4a935c052SVivien Didelot * 5a935c052SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 6a935c052SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 9a935c052SVivien Didelot */ 10a935c052SVivien Didelot 11a935c052SVivien Didelot #ifndef _MV88E6XXX_GLOBAL1_H 12a935c052SVivien Didelot #define _MV88E6XXX_GLOBAL1_H 13a935c052SVivien Didelot 144d5f2ba7SVivien Didelot #include "chip.h" 15a935c052SVivien Didelot 1682466921SVivien Didelot /* Offset 0x00: Switch Global Status Register */ 1782466921SVivien Didelot #define MV88E6XXX_G1_STS 0x00 1882466921SVivien Didelot #define MV88E6352_G1_STS_PPU_STATE 0x8000 1982466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_MASK 0xc000 2082466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST 0x0000 2182466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING 0x4000 2282466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_DISABLED 0x8000 2382466921SVivien Didelot #define MV88E6185_G1_STS_PPU_STATE_POLLING 0xc000 2482466921SVivien Didelot #define MV88E6XXX_G1_STS_INIT_READY 0x0800 25de776d0dSPavana Sharma #define MV88E6393X_G1_STS_IRQ_DEVICE_2 9 2682466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_AVB 8 2782466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_DEVICE 7 2882466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_STATS 6 2962eb1162SAndrew Lunn #define MV88E6XXX_G1_STS_IRQ_VTU_PROB 5 3082466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_VTU_DONE 4 310977644cSAndrew Lunn #define MV88E6XXX_G1_STS_IRQ_ATU_PROB 3 3282466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_ATU_DONE 2 3382466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE 1 3482466921SVivien Didelot #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE 0 3582466921SVivien Didelot 364b0c4817SVivien Didelot /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1 374b0c4817SVivien Didelot * Offset 0x02: Switch MAC Address Register Bytes 2 & 3 384b0c4817SVivien Didelot * Offset 0x03: Switch MAC Address Register Bytes 4 & 5 394b0c4817SVivien Didelot */ 404b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_01 0x01 414b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_23 0x02 424b0c4817SVivien Didelot #define MV88E6XXX_G1_MAC_45 0x03 434b0c4817SVivien Didelot 4427c0e600SVivien Didelot /* Offset 0x01: ATU FID Register */ 4527c0e600SVivien Didelot #define MV88E6352_G1_ATU_FID 0x01 4627c0e600SVivien Didelot 477ec60d6eSVivien Didelot /* Offset 0x02: VTU FID Register */ 487ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_FID 0x02 49bb03b280STobias Waldekranz #define MV88E6352_G1_VTU_FID_VID_POLICY 0x1000 507ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_FID_MASK 0x0fff 517ec60d6eSVivien Didelot 527ec60d6eSVivien Didelot /* Offset 0x03: VTU SID Register */ 537ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_SID 0x03 547ec60d6eSVivien Didelot #define MV88E6352_G1_VTU_SID_MASK 0x3f 557ec60d6eSVivien Didelot 56d77f4321SVivien Didelot /* Offset 0x04: Switch Global Control Register */ 57d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1 0x04 58d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_SW_RESET 0x8000 59d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_PPU_ENABLE 0x4000 60d77f4321SVivien Didelot #define MV88E6352_G1_CTL1_DISCARD_EXCESS 0x2000 61d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_SCHED_PRIO 0x0800 62d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_MAX_FRAME_1632 0x0400 63d77f4321SVivien Didelot #define MV88E6185_G1_CTL1_RELOAD_EEPROM 0x0200 64de776d0dSPavana Sharma #define MV88E6393X_G1_CTL1_DEVICE2_EN 0x0200 65d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_DEVICE_EN 0x0080 66d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_STATS_DONE_EN 0x0040 67d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN 0x0020 68d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_VTU_DONE_EN 0x0010 69d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN 0x0008 70d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_ATU_DONE_EN 0x0004 71d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_TCAM_EN 0x0002 72d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN 0x0001 737ec60d6eSVivien Didelot 747ec60d6eSVivien Didelot /* Offset 0x05: VTU Operation Register */ 757ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP 0x05 767ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_BUSY 0x8000 777ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_MASK 0x7000 787ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL 0x1000 797ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_NOOP 0x2000 807ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE 0x3000 817ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT 0x4000 827ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE 0x5000 837ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT 0x6000 8462eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION 0x7000 8562eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION BIT(6) 8662eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION BIT(5) 8762eb1162SAndrew Lunn #define MV88E6XXX_G1_VTU_OP_SPID_MASK 0xf 887ec60d6eSVivien Didelot 897ec60d6eSVivien Didelot /* Offset 0x06: VTU VID Register */ 907ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID 0x06 917ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID_MASK 0x0fff 927ec60d6eSVivien Didelot #define MV88E6390_G1_VTU_VID_PAGE 0x2000 937ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_VID_VALID 0x1000 947ec60d6eSVivien Didelot 957ec60d6eSVivien Didelot /* Offset 0x07: VTU/STU Data Register 1 967ec60d6eSVivien Didelot * Offset 0x08: VTU/STU Data Register 2 977ec60d6eSVivien Didelot * Offset 0x09: VTU/STU Data Register 3 987ec60d6eSVivien Didelot */ 997ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA1 0x07 1007ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA2 0x08 1017ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA3 0x09 1027ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_STU_DATA_MASK 0x0003 1037ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED 0x0000 1047ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED 0x0001 1057ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED 0x0002 1067ec60d6eSVivien Didelot #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER 0x0003 1077ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED 0x0000 1087ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING 0x0001 1097ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING 0x0002 1107ec60d6eSVivien Didelot #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING 0x0003 11127c0e600SVivien Didelot 11227c0e600SVivien Didelot /* Offset 0x0A: ATU Control Register */ 11327c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_CTL 0x0a 11427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL 0x0008 11523e8b470SAndrew Lunn #define MV88E6161_G1_ATU_CTL_HASH_MASK 0x0003 11627c0e600SVivien Didelot 11727c0e600SVivien Didelot /* Offset 0x0B: ATU Operation Register */ 11827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP 0x0b 11927c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_BUSY 0x8000 12027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_MASK 0x7000 12127c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_NOOP 0x0000 12227c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL 0x1000 12327c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC 0x2000 12427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_LOAD_DB 0x3000 12527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB 0x4000 12627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB 0x5000 12727c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB 0x6000 12827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION 0x7000 1290977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION BIT(7) 1300977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION BIT(6) 131ddca24dfSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION BIT(5) 1320977644cSAndrew Lunn #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION BIT(4) 13327c0e600SVivien Didelot 13427c0e600SVivien Didelot /* Offset 0x0C: ATU Data Register */ 13527c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA 0x0c 13627c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_TRUNK 0x8000 13727c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK 0x00f0 13827c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK 0x3ff0 13927c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MASK 0x000f 140d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED 0x0000 141d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST 0x0001 142d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2 0x0002 143d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3 0x0003 144d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4 0x0004 145d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5 0x0005 146d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6 0x0006 147d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST 0x0007 148d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY 0x0008 149d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO 0x0009 150d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL 0x000a 151d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO 0x000b 152d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT 0x000c 153d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO 0x000d 15427c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC 0x000e 155d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO 0x000f 156d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED 0x0000 157d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY 0x0004 158d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL 0x0005 159d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT 0x0006 16027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC 0x0007 161d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO 0x000c 162d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO 0x000d 163d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO 0x000e 164d8291a95SVivien Didelot #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO 0x000f 16527c0e600SVivien Didelot 16627c0e600SVivien Didelot /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1 16727c0e600SVivien Didelot * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3 16827c0e600SVivien Didelot * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5 16927c0e600SVivien Didelot */ 17027c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC01 0x0d 17127c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC23 0x0e 17227c0e600SVivien Didelot #define MV88E6XXX_G1_ATU_MAC45 0x0f 17327c0e600SVivien Didelot 174ccba8f3aSVivien Didelot /* Offset 0x10: IP-PRI Mapping Register 0 175ccba8f3aSVivien Didelot * Offset 0x11: IP-PRI Mapping Register 1 176ccba8f3aSVivien Didelot * Offset 0x12: IP-PRI Mapping Register 2 177ccba8f3aSVivien Didelot * Offset 0x13: IP-PRI Mapping Register 3 178ccba8f3aSVivien Didelot * Offset 0x14: IP-PRI Mapping Register 4 179ccba8f3aSVivien Didelot * Offset 0x15: IP-PRI Mapping Register 5 180ccba8f3aSVivien Didelot * Offset 0x16: IP-PRI Mapping Register 6 181ccba8f3aSVivien Didelot * Offset 0x17: IP-PRI Mapping Register 7 182ccba8f3aSVivien Didelot */ 183ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_0 0x10 184ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_1 0x11 185ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_2 0x12 186ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_3 0x13 187ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_4 0x14 188ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_5 0x15 189ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_6 0x16 190ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IP_PRI_7 0x17 191ccba8f3aSVivien Didelot 192ccba8f3aSVivien Didelot /* Offset 0x18: IEEE-PRI Register */ 193ccba8f3aSVivien Didelot #define MV88E6XXX_G1_IEEE_PRI 0x18 194ccba8f3aSVivien Didelot 195ccba8f3aSVivien Didelot /* Offset 0x19: Core Tag Type */ 196ccba8f3aSVivien Didelot #define MV88E6185_G1_CORE_TAG_TYPE 0x19 197101515c8SVivien Didelot 198101515c8SVivien Didelot /* Offset 0x1A: Monitor Control */ 199101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL 0x1a 200101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK 0xf000 201101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK 0x0f00 202101515c8SVivien Didelot #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK 0x00f0 203101515c8SVivien Didelot #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK 0x00f0 204101515c8SVivien Didelot #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK 0x000f 205101515c8SVivien Didelot 206101515c8SVivien Didelot /* Offset 0x1A: Monitor & MGMT Control Register */ 207101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL 0x1a 208101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE 0x8000 209101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK 0x3f00 210989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO 0x0000 211989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI 0x0100 212989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO 0x0200 213989f405aSRasmus Villemoes #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI 0x0300 214101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST 0x2000 215101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST 0x2100 216101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST 0x3000 2179627c981SKurt Kanzenbach #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_PTP_CPU_DEST 0x3200 218d8dc2c96SAndrew Lunn #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI 0x00e0 219101515c8SVivien Didelot #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK 0x00ff 220d77f4321SVivien Didelot 221d77f4321SVivien Didelot /* Offset 0x1C: Global Control 2 */ 222d77f4321SVivien Didelot #define MV88E6XXX_G1_CTL2 0x1c 22302317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK 0xf000 22402317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE 0xe000 22502317e68SVivien Didelot #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI 0xf000 226408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK 0xc000 227408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG 0x0000 228408d2debSVivien Didelot #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT 0x4000 229408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG 0x8000 2309e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_MASK 0x3000 2319e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED 0x0000 2329e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4 0x1000 2339e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5 0x2000 2349e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6 0x3000 2359e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_DA_CHECK 0x4000 2369e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_P10RM 0x2000 2379e5baf9bSVivien Didelot #define MV88E6085_G1_CTL2_RM_ENABLE 0x1000 2389e5baf9bSVivien Didelot #define MV88E6352_G1_CTL2_DA_CHECK 0x0800 2399e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_MASK 0x0700 2409e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0 0x0000 2419e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1 0x0100 2429e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9 0x0200 2439e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10 0x0300 2449e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA 0x0600 2459e5baf9bSVivien Didelot #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED 0x0700 246408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_MASK 0x00c0 247408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_RX 0x0040 248408d2debSVivien Didelot #define MV88E6390_G1_CTL2_HIST_MODE_TX 0x0080 249408d2debSVivien Didelot #define MV88E6352_G1_CTL2_CTR_MODE_MASK 0x0060 250408d2debSVivien Didelot #define MV88E6390_G1_CTL2_CTR_MODE 0x0020 25123c98919SVivien Didelot #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK 0x001f 252d77f4321SVivien Didelot 25357d1ef38SVivien Didelot /* Offset 0x1D: Stats Operation Register */ 25457d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP 0x1d 25557d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BUSY 0x8000 25657d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_NOP 0x0000 25757d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL 0x1000 25857d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT 0x2000 25957d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED 0x4000 26057d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT 0x5000 26157d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_RX 0x0400 26257d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_TX 0x0800 26357d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX 0x0c00 26457d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9 0x0200 26557d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10 0x0400 26657d1ef38SVivien Didelot 26757d1ef38SVivien Didelot /* Offset 0x1E: Stats Counter Register Bytes 3 & 2 26857d1ef38SVivien Didelot * Offset 0x1F: Stats Counter Register Bytes 1 & 0 26957d1ef38SVivien Didelot */ 27057d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_COUNTER_32 0x1e 27157d1ef38SVivien Didelot #define MV88E6XXX_G1_STATS_COUNTER_01 0x1f 272e097097bSVivien Didelot 273a935c052SVivien Didelot int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val); 274a935c052SVivien Didelot int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val); 27519fb7f69SVivien Didelot int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int 27619fb7f69SVivien Didelot bit, int val); 277683f2244SVivien Didelot int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg, 278683f2244SVivien Didelot u16 mask, u16 val); 27917e708baSVivien Didelot 2804b0c4817SVivien Didelot int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr); 2814b0c4817SVivien Didelot 28217e708baSVivien Didelot int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip); 28317e708baSVivien Didelot int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip); 2841f71836fSRasmus Villemoes int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip); 285a4702791SMatthias Schiffer int mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip); 286a4702791SMatthias Schiffer int mv88e6250_g1_wait_eeprom_done_prereset(struct mv88e6xxx_chip *chip); 28717e708baSVivien Didelot 288a199d8b6SVivien Didelot int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip); 289a199d8b6SVivien Didelot int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip); 290a199d8b6SVivien Didelot 2911baf0facSChris Packham int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu); 2921baf0facSChris Packham 293a605a0feSAndrew Lunn int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 294a605a0feSAndrew Lunn int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 29579523473SAndrew Lunn int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port); 29640cff8fcSAndrew Lunn int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 297de227387SAndrew Lunn int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip); 2987f9ef3afSAndrew Lunn void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val); 29940cff8fcSAndrew Lunn int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip); 3005c74c54cSIwan R Timmer int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 3015c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 3025c74c54cSIwan R Timmer int port); 3035c74c54cSIwan R Timmer int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 3045c74c54cSIwan R Timmer enum mv88e6xxx_egress_direction direction, 3055c74c54cSIwan R Timmer int port); 30633641994SAndrew Lunn int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 30733641994SAndrew Lunn int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port); 3089627c981SKurt Kanzenbach int mv88e6390_g1_set_ptp_cpu_port(struct mv88e6xxx_chip *chip, int port); 3096e55f698SAndrew Lunn int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 310a935c052SVivien Didelot 31193e18d61SVivien Didelot int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip); 312df63b0d9SRasmus Villemoes 31393e18d61SVivien Didelot int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); 314df63b0d9SRasmus Villemoes int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip); 31593e18d61SVivien Didelot 31602317e68SVivien Didelot int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port); 31702317e68SVivien Didelot 3189e5baf9bSVivien Didelot int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip); 3199e5baf9bSVivien Didelot int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip); 3209e5baf9bSVivien Didelot int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip); 3219e5baf9bSVivien Didelot 32223c98919SVivien Didelot int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index); 32323c98919SVivien Didelot 324c3a7d4adSVivien Didelot int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all); 325720c6343SVivien Didelot int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip, 326720c6343SVivien Didelot unsigned int msecs); 327dabc1a96SVivien Didelot int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 328dabc1a96SVivien Didelot struct mv88e6xxx_atu_entry *entry); 3299c13c026SVivien Didelot int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid, 3309c13c026SVivien Didelot struct mv88e6xxx_atu_entry *entry); 331daefc943SVivien Didelot int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all); 332e606ca36SVivien Didelot int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port, 333e606ca36SVivien Didelot bool all); 3340977644cSAndrew Lunn int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip); 3350977644cSAndrew Lunn void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip); 33623e8b470SAndrew Lunn int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash); 33723e8b470SAndrew Lunn int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash); 338720c6343SVivien Didelot 339ca4d632aSTobias Waldekranz int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 340ca4d632aSTobias Waldekranz struct mv88e6xxx_vtu_entry *entry); 341f1394b78SVivien Didelot int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 342f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 3430ad5daf6SVivien Didelot int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 3440ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 345f1394b78SVivien Didelot int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 346f1394b78SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 3470ad5daf6SVivien Didelot int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 3480ad5daf6SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 349931d1822SVivien Didelot int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip, 350931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 351931d1822SVivien Didelot int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip, 352931d1822SVivien Didelot struct mv88e6xxx_vtu_entry *entry); 353b486d7c9SVivien Didelot int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip); 35449c98c1dSTobias Waldekranz int mv88e6xxx_g1_stu_getnext(struct mv88e6xxx_chip *chip, 35549c98c1dSTobias Waldekranz struct mv88e6xxx_stu_entry *entry); 35649c98c1dSTobias Waldekranz int mv88e6352_g1_stu_getnext(struct mv88e6xxx_chip *chip, 35749c98c1dSTobias Waldekranz struct mv88e6xxx_stu_entry *entry); 35849c98c1dSTobias Waldekranz int mv88e6352_g1_stu_loadpurge(struct mv88e6xxx_chip *chip, 35949c98c1dSTobias Waldekranz struct mv88e6xxx_stu_entry *entry); 36049c98c1dSTobias Waldekranz int mv88e6390_g1_stu_getnext(struct mv88e6xxx_chip *chip, 36149c98c1dSTobias Waldekranz struct mv88e6xxx_stu_entry *entry); 36249c98c1dSTobias Waldekranz int mv88e6390_g1_stu_loadpurge(struct mv88e6xxx_chip *chip, 36349c98c1dSTobias Waldekranz struct mv88e6xxx_stu_entry *entry); 36462eb1162SAndrew Lunn int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip); 36562eb1162SAndrew Lunn void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip); 366c5f299d5SAndrew Lunn int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid); 367332aa5ccSVivien Didelot 368a935c052SVivien Didelot #endif /* _MV88E6XXX_GLOBAL1_H */ 369