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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmsi.txt86 reg = <0xa 0xf00>;
93 reg = <0xb 0xf00>;
101 reg = <0xc 0xf00>;
108 dev@0 {
109 reg = <0x0 0xf00>;
117 reg = <0x1 0xf00>;
123 msi-parent = <&msi_a>, <&msi_b 0x17>;
127 reg = <0x2 0xf00>;
133 msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
/openbmc/qemu/tests/tcg/ppc64/
H A Dbcdsub.c9 #define CRF_SO (1 << 0)
10 #define UNDEF 0
28 int cr = 0; \
41 BCDSUB(0, 0, 1, PS) \
42 "mfocrf %0, 0b10\n\t" \
54 } while (0)
58 * sign = (PS) ? 0b1111 : 0b1100
59 * CR6 = 0b0010
64 TEST(0x9999999999999999, 0x999999999999999c, in test_bcdsub_eq()
65 0x9999999999999999, 0x999999999999999c, in test_bcdsub_eq()
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt2701.c38 /* 0E4E8SR 4/8/12/16 */
40 /* 0E2E4SR 2/4/6/8 */
43 MTK_DRV_GRP(2, 16, 0, 2, 2)
47 MTK_PIN_DRV_GRP(0, 0xf50, 0, 1),
48 MTK_PIN_DRV_GRP(1, 0xf50, 0, 1),
49 MTK_PIN_DRV_GRP(2, 0xf50, 0, 1),
50 MTK_PIN_DRV_GRP(3, 0xf50, 0, 1),
51 MTK_PIN_DRV_GRP(4, 0xf50, 0, 1),
52 MTK_PIN_DRV_GRP(5, 0xf50, 0, 1),
53 MTK_PIN_DRV_GRP(6, 0xf50, 0, 1),
[all …]
/openbmc/linux/drivers/regulator/
H A Dmt6358-regulator.c16 #define MT6358_BUCK_MODE_AUTO 0
56 .enable_mask = BIT(0), \
60 .qi = BIT(0), \
108 .enable_mask = BIT(0), \
113 .qi = BIT(0), \
152 .enable_mask = BIT(0), \
156 .qi = BIT(0), \
204 .enable_mask = BIT(0), \
209 .qi = BIT(0), \
280 0, 12,
[all …]
H A Dmt6357-regulator.c53 .enable_mask = BIT(0), \
75 .enable_mask = BIT(0), \
96 .enable_mask = BIT(0), \
99 .da_vsel_mask = 0x7f00, \
114 .enable_mask = BIT(0), \
134 if (ret != 0) { in mt6357_get_buck_voltage_sel()
178 0,
186 0,
188 0,
189 0,
[all …]
/openbmc/linux/drivers/net/ethernet/moxa/
H A Dmoxart_ether.h18 #define TX_REG_OFFSET_DESC0 0
23 #define RX_REG_OFFSET_DESC0 0
28 #define TX_DESC0_PKT_LATE_COL 0x1 /* abort, late collision */
29 #define TX_DESC0_RX_PKT_EXS_COL 0x2 /* abort, >16 collisions */
30 #define TX_DESC0_DMA_OWN 0x80000000 /* owned by controller */
31 #define TX_DESC1_BUF_SIZE_MASK 0x7ff
32 #define TX_DESC1_LTS 0x8000000 /* last TX packet */
33 #define TX_DESC1_FTS 0x10000000 /* first TX packet */
34 #define TX_DESC1_FIFO_COMPLETE 0x20000000
35 #define TX_DESC1_INTR_COMPLETE 0x40000000
[all …]
/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S23 mov r5, #0
28 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
29 orr r0, r0, #0x0
34 ldr r1, =0x9
38 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
40 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
43 mvn r3, #0x0
44 str r3, [r0, #0x14] @INTENCLEAR
45 str r3, [r1, #0x14] @INTENCLEAR
[all …]
/openbmc/u-boot/include/
H A Dfsl_sec_mon.h31 u8 reserved0[0x04];
32 u32 hp_com; /* 0x04 SEC_MON_HP Command Register */
33 u8 reserved2[0x0c];
34 u32 hp_stat; /* 0x08 SEC_MON_HP Status Register */
37 #define HPCOMR_SW_SV 0x100 /* Security Violation bit */
38 #define HPCOMR_SW_FSV 0x200 /* Fatal Security Violation bit */
39 #define HPCOMR_SSM_ST 0x1 /* SSM_ST field in SEC_MON command */
40 #define HPCOMR_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */
41 #define HPCOMR_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */
42 #define HPSR_SSM_ST_CHECK 0x900 /* SEC_MON is in check state */
[all …]
/openbmc/linux/arch/arm/mm/
H A Dtlb-v4wbi.S34 mov r3, #0
35 mcr p15, 0, r3, c7, c10, 4 @ drain WB
37 bic r0, r0, #0x0ff
38 bic r0, r0, #0xf00
40 mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry
41 mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
48 mov r3, #0
49 mcr p15, 0, r3, c7, c10, 4 @ drain WB
50 bic r0, r0, #0x0ff
51 bic r0, r0, #0xf00
[all …]
H A Dtlb-v4wb.S36 mcr p15, 0, r3, c7, c10, 4 @ drain WB
38 mcrne p15, 0, r3, c8, c5, 0 @ invalidate I TLB
39 bic r0, r0, #0x0ff
40 bic r0, r0, #0xf00
41 1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry
57 mov r3, #0
58 mcr p15, 0, r3, c7, c10, 4 @ drain WB
59 bic r0, r0, #0x0ff
60 bic r0, r0, #0xf00
61 mcr p15, 0, r3, c8, c5, 0 @ invalidate I TLB
[all …]
H A Dtlb-fa.S39 mov r3, #0
40 mcr p15, 0, r3, c7, c10, 4 @ drain WB
41 bic r0, r0, #0x0ff
42 bic r0, r0, #0xf00
43 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry
47 mcr p15, 0, r3, c7, c10, 4 @ data write barrier
52 mov r3, #0
53 mcr p15, 0, r3, c7, c10, 4 @ drain WB
54 bic r0, r0, #0x0ff
55 bic r0, r0, #0xf00
[all …]
/openbmc/qemu/tests/functional/
H A Dtest_arm_aspeed_rainier.py35 self.wait_for_console_pattern('Booting Linux on physical CPU 0xf00')
40 …bian.org/archive/debian/20220606T211338Z/pool/main/l/linux/linux-image-5.17.0-2-armmp_5.17.6-1%2Bb…
48 kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.17.0-2-armmp')
50 '/usr/lib/linux-image-5.17.0-2-armmp/aspeed-bmc-ibm-rainier.dtb')
58 self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00")
/openbmc/linux/drivers/media/pci/ddbridge/
H A Dddbridge-hw.c16 .base = 0x200,
17 .num = 0x08,
18 .size = 0x10,
22 .base = 0x280,
23 .num = 0x08,
24 .size = 0x10,
28 .base = 0x300,
29 .num = 0x08,
30 .size = 0x10,
34 .base = 0x2000,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/openbmc/qemu/hw/display/
H A Dedid-generate.c31 { .xres = 1920, .yres = 1200, .xtra3 = 10, .bit = 0 },
47 { .xres = 800, .yres = 600, .byte = 35, .bit = 0 },
82 dta[0] = 0x02; in edid_ext_dta()
83 dta[1] = 0x03; in edid_ext_dta()
84 dta[2] = 0x05; in edid_ext_dta()
85 dta[3] = 0x00; in edid_ext_dta()
88 dta[4] = 0x40; in edid_ext_dta()
102 if (xres == 0 || yres == 0) { in edid_std_mode()
103 mode[0] = 0x01; in edid_std_mode()
104 mode[1] = 0x01; in edid_std_mode()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_sh_mask.h27 #define IH_VMID_0_LUT__PASID_MASK 0xffff
28 #define IH_VMID_0_LUT__PASID__SHIFT 0x0
29 #define IH_VMID_1_LUT__PASID_MASK 0xffff
30 #define IH_VMID_1_LUT__PASID__SHIFT 0x0
31 #define IH_VMID_2_LUT__PASID_MASK 0xffff
32 #define IH_VMID_2_LUT__PASID__SHIFT 0x0
33 #define IH_VMID_3_LUT__PASID_MASK 0xffff
34 #define IH_VMID_3_LUT__PASID__SHIFT 0x0
35 #define IH_VMID_4_LUT__PASID_MASK 0xffff
36 #define IH_VMID_4_LUT__PASID__SHIFT 0x0
[all …]
/openbmc/u-boot/doc/device-tree-bindings/
H A Dchosen.txt21 reg = <0xf00 0x10>;
41 reg = <0xf00 0x10>;
61 bootcount-rv3029: bootcount@0 {
64 offset = <0x38>;
70 reg = <0x56>;
131 fs_loader0: fs-loader@0 {
/openbmc/linux/arch/powerpc/sysdev/
H A Dindirect_pci.c23 u8 cfg_type = 0; in __indirect_read_config()
29 if (devfn != 0) in __indirect_read_config()
45 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in __indirect_read_config()
47 reg = offset & 0xfc; in __indirect_read_config()
50 out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in __indirect_read_config()
53 out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | in __indirect_read_config()
89 u8 cfg_type = 0; in indirect_write_config()
95 if (devfn != 0) in indirect_write_config()
111 reg = ((offset & 0xf00) << 16) | (offset & 0xfc); in indirect_write_config()
113 reg = offset & 0xfc; in indirect_write_config()
[all …]
/openbmc/u-boot/configs/
H A Dstm32f429-discovery_defconfig3 CONFIG_SYS_TEXT_BASE=0x08000000
4 CONFIG_SYS_MALLOC_F_LEN=0xF00
11 CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 ignore_loglevel"
H A Dstm32f469-discovery_defconfig3 CONFIG_SYS_TEXT_BASE=0x08000000
4 CONFIG_SYS_MALLOC_F_LEN=0xF00
H A Dstm32f429-evaluation_defconfig3 CONFIG_SYS_TEXT_BASE=0x08000000
4 CONFIG_SYS_MALLOC_F_LEN=0xF00
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dnxp,lpc3220-usb-clk.txt15 ranges = <0x0 0x31020000 0x00001000>;
19 reg = <0xf00 0x100>;

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