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/openbmc/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dr8a7794.h14 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
17 #define MSTP0_BITS 0x00440801
18 #define MSTP1_BITS 0x936899DA
19 #define MSTP2_BITS 0x100D21FC
20 #define MSTP3_BITS 0xE084D810
21 #define MSTP4_BITS 0x800001C4
22 #define MSTP5_BITS 0x40C00044
23 #define MSTP7_BITS 0x013FE618
24 #define MSTP8_BITS 0x40803C05
25 #define MSTP9_BITS 0xFB879FEE
[all …]
H A Dr8a7790.h14 #define CONFIG_SYS_I2C_SH_BASE2 0xE6520000
15 #define CONFIG_SYS_I2C_SH_BASE3 0xE60B0000
18 #define MSTP0_BITS 0x00640801
19 #define MSTP1_BITS 0xDB6E9BDF
20 #define MSTP2_BITS 0x300DA1FC
21 #define MSTP3_BITS 0xF08CF831
22 #define MSTP4_BITS 0x80000184
23 #define MSTP5_BITS 0x44C00046
24 #define MSTP7_BITS 0x07F30718
25 #define MSTP8_BITS 0x01F0FF84
[all …]
H A Dr8a7791.h17 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
20 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
21 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
24 #define DBSC3_1_QOS_R0_BASE 0xE67A1000
25 #define DBSC3_1_QOS_R1_BASE 0xE67A1100
26 #define DBSC3_1_QOS_R2_BASE 0xE67A1200
27 #define DBSC3_1_QOS_R3_BASE 0xE67A1300
28 #define DBSC3_1_QOS_R4_BASE 0xE67A1400
29 #define DBSC3_1_QOS_R5_BASE 0xE67A1500
30 #define DBSC3_1_QOS_R6_BASE 0xE67A1600
[all …]
H A Dr8a7793.h18 #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
21 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
22 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
25 #define DBSC3_1_QOS_R0_BASE 0xE67A1000
26 #define DBSC3_1_QOS_R1_BASE 0xE67A1100
27 #define DBSC3_1_QOS_R2_BASE 0xE67A1200
28 #define DBSC3_1_QOS_R3_BASE 0xE67A1300
29 #define DBSC3_1_QOS_R4_BASE 0xE67A1400
30 #define DBSC3_1_QOS_R5_BASE 0xE67A1500
31 #define DBSC3_1_QOS_R6_BASE 0xE67A1600
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Drenesas,sdhi.yaml103 pinctrl-0:
228 reg = <0xee100000 0x328>;
231 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
240 reg = <0xee120000 0x328>;
243 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
252 reg = <0xee140000 0x100>;
255 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
264 reg = <0xee160000 0x100>;
267 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a73a4.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
77 #size-cells = <0>;
79 reg = <0 0xe60b0000 0 0x428>;
89 reg = <0 0xe6130000 0 0x1004>;
108 reg = <0 0xe61c0000 0 0x200>;
[all …]
H A Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
H A Dr8a7742.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
30 #clock-cells = <0>;
31 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
44 clock-frequency = <0>;
49 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a7743.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
H A Dr8a7744.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
37 #clock-cells = <0>;
38 clock-frequency = <0>;
44 #clock-cells = <0>;
46 clock-frequency = <0>;
51 #size-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77995.dtsi21 #clock-cells = <0>;
22 clock-frequency = <0>;
27 #size-cells = <0>;
29 a53_0: cpu@0 {
31 reg = <0x0>;
48 #clock-cells = <0>;
50 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
79 reg = <0 0xe6020000 0 0x0c>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77965.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #size-cells = <0>;
[all …]
H A Dr8a7790.dtsi41 * The external audio clocks are configured as 0 Hz fixed frequency
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
57 #clock-cells = <0>;
58 clock-frequency = <0>;
64 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/mmc/host/
H A Drenesas_sdhi_core.c42 #define CTL_HOST_MODE 0xe4
43 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0)
44 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0)
45 #define HOST_MODE_GEN3_WMODE BIT(0)
50 #define HOST_MODE_GEN3_64BIT 0
52 #define SDHI_VER_GEN2_SDR50 0x490c
53 #define SDHI_VER_RZ_A1 0x820b
54 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
55 #define SDHI_VER_GEN2_SDR104 0xcb0d
56 #define SDHI_VER_GEN3_SD 0xcc10
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77970.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
69 clock-frequency = <0>;
87 #clock-cells = <0>;
[all …]
H A Dr8a779f0.dtsi17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]
H A Dr8a77980.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77995.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #size-cells = <0>;
46 a53_0: cpu@0 {
48 reg = <0x0>;
[all …]

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