1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 27a7d246dSNobuhiro Iwamatsu /* 37a7d246dSNobuhiro Iwamatsu * arch/arm/include/asm/arch-rmobile/r8a7793.h 47a7d246dSNobuhiro Iwamatsu * 57a7d246dSNobuhiro Iwamatsu * Copyright (C) 2014 Renesas Electronics Corporation 67a7d246dSNobuhiro Iwamatsu */ 77a7d246dSNobuhiro Iwamatsu 87a7d246dSNobuhiro Iwamatsu #ifndef __ASM_ARCH_R8A7793_H 97a7d246dSNobuhiro Iwamatsu #define __ASM_ARCH_R8A7793_H 107a7d246dSNobuhiro Iwamatsu 117a7d246dSNobuhiro Iwamatsu #include "rcar-base.h" 127a7d246dSNobuhiro Iwamatsu 137a7d246dSNobuhiro Iwamatsu /* 147a7d246dSNobuhiro Iwamatsu * R8A7793 I/O Addresses 157a7d246dSNobuhiro Iwamatsu */ 167a7d246dSNobuhiro Iwamatsu 177a7d246dSNobuhiro Iwamatsu /* SH-I2C */ 187a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000 197a7d246dSNobuhiro Iwamatsu 207a7d246dSNobuhiro Iwamatsu /* SDHI */ 217a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000 227a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000 237a7d246dSNobuhiro Iwamatsu #define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3 247a7d246dSNobuhiro Iwamatsu 257a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R0_BASE 0xE67A1000 267a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R1_BASE 0xE67A1100 277a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R2_BASE 0xE67A1200 287a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R3_BASE 0xE67A1300 297a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R4_BASE 0xE67A1400 307a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R5_BASE 0xE67A1500 317a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R6_BASE 0xE67A1600 327a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R7_BASE 0xE67A1700 337a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R8_BASE 0xE67A1800 347a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R9_BASE 0xE67A1900 357a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R10_BASE 0xE67A1A00 367a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R11_BASE 0xE67A1B00 377a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R12_BASE 0xE67A1C00 387a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R13_BASE 0xE67A1D00 397a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R14_BASE 0xE67A1E00 407a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_R15_BASE 0xE67A1F00 417a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W0_BASE 0xE67A2000 427a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W1_BASE 0xE67A2100 437a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W2_BASE 0xE67A2200 447a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W3_BASE 0xE67A2300 457a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W4_BASE 0xE67A2400 467a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W5_BASE 0xE67A2500 477a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W6_BASE 0xE67A2600 487a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W7_BASE 0xE67A2700 497a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W8_BASE 0xE67A2800 507a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W9_BASE 0xE67A2900 517a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W10_BASE 0xE67A2A00 527a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W11_BASE 0xE67A2B00 537a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W12_BASE 0xE67A2C00 547a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W13_BASE 0xE67A2D00 557a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W14_BASE 0xE67A2E00 567a7d246dSNobuhiro Iwamatsu #define DBSC3_1_QOS_W15_BASE 0xE67A2F00 577a7d246dSNobuhiro Iwamatsu 587a7d246dSNobuhiro Iwamatsu #define DBSC3_1_DBADJ2 0xE67A00C8 597a7d246dSNobuhiro Iwamatsu 607a7d246dSNobuhiro Iwamatsu /* 617a7d246dSNobuhiro Iwamatsu * R8A7793 I/O Product Information 627a7d246dSNobuhiro Iwamatsu */ 637a7d246dSNobuhiro Iwamatsu 647a7d246dSNobuhiro Iwamatsu /* Module stop control/status register bits */ 657a7d246dSNobuhiro Iwamatsu #define MSTP0_BITS 0x00640801 667a7d246dSNobuhiro Iwamatsu #define MSTP1_BITS 0x9B6C9B5A 677a7d246dSNobuhiro Iwamatsu #define MSTP2_BITS 0x100D21FC 687a7d246dSNobuhiro Iwamatsu #define MSTP3_BITS 0xF08CD810 697a7d246dSNobuhiro Iwamatsu #define MSTP4_BITS 0x800001C4 707a7d246dSNobuhiro Iwamatsu #define MSTP5_BITS 0x44C00046 717a7d246dSNobuhiro Iwamatsu #define MSTP7_BITS 0x05BFE618 727a7d246dSNobuhiro Iwamatsu #define MSTP8_BITS 0x40C0FE85 737a7d246dSNobuhiro Iwamatsu #define MSTP9_BITS 0xFF979FFF 747a7d246dSNobuhiro Iwamatsu #define MSTP10_BITS 0xFFFEFFE0 757a7d246dSNobuhiro Iwamatsu #define MSTP11_BITS 0x000001C0 767a7d246dSNobuhiro Iwamatsu 777a7d246dSNobuhiro Iwamatsu #define R8A7793_CUT_ES2X 2 787a7d246dSNobuhiro Iwamatsu #define IS_R8A7793_ES2() \ 797a7d246dSNobuhiro Iwamatsu (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X) 807a7d246dSNobuhiro Iwamatsu 817a7d246dSNobuhiro Iwamatsu #endif /* __ASM_ARCH_R8A7793_H */ 82