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/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi13 emc-timings-0 {
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
21 nvidia,emc-zcal-cnt-long = <0x00000040>;
25 0x0000001f /* EMC_RC */
26 0x00000069 /* EMC_RFC */
27 0x00000017 /* EMC_RAS */
28 0x00000007 /* EMC_RP */
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
12 0x00020001 /* MC_EMEM_ARB_CFG */
13 0xc0000020 /* MC_EMEM_ARB_OUTSTANDING_REQ */
14 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
15 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
16 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
17 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
18 0x00000001 /* MC_EMEM_ARB_TIMING_FAW */
19 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
[all …]
H A Dtegra30-ouya.dts32 tlm,version-major = <0x0>;
33 tlm,version-minor = <0x0>;
38 reg = <0x80000000 0x40000000>;
48 alloc-ranges = <0x80000000 0x30000000>;
49 size = <0x10000000>; /* 256MiB */
56 reg = <0xbfdf0000 0x10000>; /* 64kB */
57 console-size = <0x8000>; /* 32kB */
58 record-size = <0x400>; /* 1kB */
63 reg = <0xbfe00000 0x200000>;
81 pinctrl-0 = <&state_default>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Daardvark-pci.txt39 reg = <0 0xd0070000 0 0x20000>;
42 bus-range = <0x00 0xff>;
47 ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
48 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
49 interrupt-map-mask = <0 0 0 7>;
50 interrupt-map = <0 0 0 1 &pcie_intc 0>,
51 <0 0 0 2 &pcie_intc 1>,
52 <0 0 0 3 &pcie_intc 2>,
53 <0 0 0 4 &pcie_intc 3>;
54 phys = <&comphy1 0>;
/openbmc/u-boot/include/configs/
H A Dqemu-ppce500.h27 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
28 #define CONFIG_SYS_MEMTEST_END 0x00400000
33 #define CONFIG_SYS_CCSRBAR 0xe0000000
40 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
45 #define CONFIG_SYS_PCI_MAP_START 0x80000000
46 #define CONFIG_SYS_PCI_MAP_END 0xe8000000
49 #define CONFIG_SYS_TMPVIRT 0xe8000000
55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
58 #define CONFIG_CHIP_SELECTS_PER_CTRL 0
62 #define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
[all …]
/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dcpu.h12 #define S5PC1XX_ADDR_BASE 0xE0000000
15 #define S5PC100_PRO_ID 0xE0000000
16 #define S5PC100_CLOCK_BASE 0xE0100000
17 #define S5PC100_GPIO_BASE 0xE0300000
18 #define S5PC100_VIC0_BASE 0xE4000000
19 #define S5PC100_VIC1_BASE 0xE4100000
20 #define S5PC100_VIC2_BASE 0xE4200000
21 #define S5PC100_DMC_BASE 0xE6000000
22 #define S5PC100_SROMC_BASE 0xE7000000
23 #define S5PC100_ONENAND_BASE 0xE7100000
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-37xx.dtsi35 reg = <0 0x4000000 0 0x200000>;
40 reg = <0 0x4400000 0 0x1000000>;
47 #size-cells = <0>;
48 cpu0: cpu@0 {
51 reg = <0>;
85 /* 32M internal register @ 0xd000_0000 */
86 ranges = <0x0 0x0 0xd0000000 0x2000000>;
90 reg = <0x8300 0x40>;
98 reg = <0xd000 0x1000>;
104 #size-cells = <0>;
[all …]
H A Darmada-ap810-ap0.dtsi39 ranges = <0x0 0x0 0xe8000000 0x4000000>;
51 reg = <0x3000000 0x10000>, /* GICD */
52 <0x3060000 0x100000>, /* GICR */
53 <0x00c0000 0x2000>, /* GICC */
54 <0x00d0000 0x1000>, /* GICH */
55 <0x00e0000 0x2000>; /* GICV */
61 reg = <0x3040000 0x20000>;
75 reg = <0x400000 0x1000>,
76 <0x410000 0x1000>;
77 msi-parent = <&gic_its_ap0 0xa0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/bus/
H A Dmvebu-mbus.txt65 pcie-mem-aperture = <0xe0000000 0x8000000>;
66 pcie-io-aperture = <0xe8000000 0x100000>;
73 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
87 0xSIAA0000 0x00oooooo
91 S = 0x0 for a MBus valid window
92 S = 0xf for a non-valid window (see below)
94 If S = 0x0, then:
99 If S = 0xf, then:
105 (S = 0x0), an address decoding window is allocated. On the other side,
106 entries for translation that do not correspond to valid windows (S = 0xf)
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp2020ds.dts19 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
20 0x1 0x0 0x0 0xe0000000 0x08000000
21 0x2 0x0 0x0 0xffa00000 0x00040000
22 0x3 0x0 0x0 0xffdf0000 0x00008000
23 0x4 0x0 0x0 0xffa40000 0x00040000
24 0x5 0x0 0x0 0xffa80000 0x00040000
25 0x6 0x0 0x0 0xffac0000 0x00040000>;
26 reg = <0 0xffe05000 0 0x1000>;
30 ranges = <0x0 0x0 0xffe00000 0x100000>;
34 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
[all …]
H A Dmpc8572ds.dts19 reg = <0 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
22 0x1 0x0 0x0 0xe0000000 0x08000000
23 0x2 0x0 0x0 0xffa00000 0x00040000
24 0x3 0x0 0x0 0xffdf0000 0x00008000
25 0x4 0x0 0x0 0xffa40000 0x00040000
26 0x5 0x0 0x0 0xffa80000 0x00040000
27 0x6 0x0 0x0 0xffac0000 0x00040000>;
31 ranges = <0x0 0 0xffe00000 0x100000>;
35 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8572ds_36b.dts19 reg = <0xf 0xffe05000 0 0x1000>;
21 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
22 0x1 0x0 0xf 0xe0000000 0x08000000
23 0x2 0x0 0xf 0xffa00000 0x00040000
24 0x3 0x0 0xf 0xffdf0000 0x00008000
25 0x4 0x0 0xf 0xffa40000 0x00040000
26 0x5 0x0 0xf 0xffa80000 0x00040000
27 0x6 0x0 0xf 0xffac0000 0x00040000>;
31 ranges = <0x0 0xf 0xffe00000 0x100000>;
35 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8536ds_36b.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0xf 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
35 0x2 0x0 0xf 0xffa00000 0x00040000
36 0x3 0x0 0xf 0xffdf0000 0x00008000>;
40 ranges = <0x0 0xf 0xffe00000 0x100000>;
44 reg = <0xf 0xffe08000 0 0x1000>;
[all …]
H A Dmpc8536ds.dts17 #size-cells = <0>;
19 PowerPC,8536@0 {
21 reg = <0>;
28 reg = <0 0 0 0>; // Filled by U-Boot
32 reg = <0 0xffe05000 0 0x1000>;
34 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
35 0x2 0x0 0x0 0xffa00000 0x00040000
36 0x3 0x0 0x0 0xffdf0000 0x00008000>;
40 ranges = <0x0 0 0xffe00000 0x100000>;
44 reg = <0 0xffe08000 0 0x1000>;
[all …]
H A Dp1022ds_32b.dts45 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
46 0x1 0x0 0x0 0xe0000000 0x08000000
47 0x2 0x0 0x0 0xff800000 0x00040000
48 0x3 0x0 0x0 0xffdf0000 0x00008000>;
49 reg = <0x0 0xffe05000 0 0x1000>;
53 ranges = <0x0 0x0 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0 0xa0000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
59 reg = <0x0 0xffe09000 0 0x1000>;
60 pcie@0 {
[all …]
H A Dp1022ds_36b.dts45 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
46 0x1 0x0 0xf 0xe0000000 0x08000000
47 0x2 0x0 0xf 0xff800000 0x00040000
48 0x3 0x0 0xf 0xffdf0000 0x00008000>;
49 reg = <0xf 0xffe05000 0 0x1000>;
53 ranges = <0x0 0xf 0xffe00000 0x100000>;
57 ranges = <0x2000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
58 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
59 reg = <0xf 0xffe09000 0 0x1000>;
60 pcie@0 {
[all …]
H A Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-37xx.dtsi64 #size-cells = <0>;
65 cpu@0 {
68 reg = <0>;
100 /* 32M internal register @ 0xd000_0000 */
101 ranges = <0x0 0x0 0xd0000000 0x2000000>;
105 reg = <0x12000 0x400>;
112 reg = <0xd064 0x4>,
113 <0x8300 0x40>;
118 reg = <0x13000 0x100>;
119 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
[all …]
/openbmc/u-boot/include/configs/km/
H A Dkm8321-common.h32 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
70 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
76 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
78 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
79 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
86 #define CONFIG_SYS_DDR_MODE 0x47860242
87 #define CONFIG_SYS_DDR_MODE2 0x8080c000
93 (0 << TIMING_CFG0_WWT_SHIFT) | \
94 (0 << TIMING_CFG0_RRT_SHIFT) | \
95 (0 << TIMING_CFG0_WRT_SHIFT) | \
[all …]
H A Dkm8309-common.h20 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
29 #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
35 /* 0x14000180 SICR_1 */
36 #define CONFIG_SYS_SICRL (0 \
53 /* 0x00080400 SICR_2 */
54 #define CONFIG_SYS_SICRH (0 \
70 #define CONFIG_SYS_GPR1 0x50008060
72 #define CONFIG_SYS_GP1DIR 0x00000000
73 #define CONFIG_SYS_GP1ODR 0x00000000
74 #define CONFIG_SYS_GP2DIR 0xFF000000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Da3m071.dts26 ranges = <0 0xf0000000 0x0000c000>;
27 reg = <0xf0000000 0x00000100>;
28 bus-frequency = <0>; /* From boot loader */
29 system-frequency = <0>; /* From boot loader */
41 reg = <0x2000 0x100>;
42 interrupts = <2 1 0>;
63 reg = <0x2c00 0x100>;
64 interrupts = <2 4 0>;
73 reg = <0x03>;
94 ranges = <0 0 0xfc000000 0x02000000
[all …]
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dcpu.h19 ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c)
21 #define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
22 #define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
23 #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
24 #define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
26 #define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
49 KWCPU_ATTR_SASRAM = 0x01,
50 KWCPU_ATTR_DRAM_CS0 = 0x0e,
51 KWCPU_ATTR_DRAM_CS1 = 0x0d,
52 KWCPU_ATTR_DRAM_CS2 = 0x0b,
[all …]

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