Lines Matching +full:0 +full:xe8000000
20 #define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0"
29 #define CONFIG_SYS_QE_FW_ADDR 0xF00C0000
35 /* 0x14000180 SICR_1 */
36 #define CONFIG_SYS_SICRL (0 \
53 /* 0x00080400 SICR_2 */
54 #define CONFIG_SYS_SICRH (0 \
70 #define CONFIG_SYS_GPR1 0x50008060
72 #define CONFIG_SYS_GP1DIR 0x00000000
73 #define CONFIG_SYS_GP1ODR 0x00000000
74 #define CONFIG_SYS_GP2DIR 0xFF000000
75 #define CONFIG_SYS_GP2ODR 0x00000000
105 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
111 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
113 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
114 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
122 #define CONFIG_SYS_DDR_MODE 0x47860242
123 #define CONFIG_SYS_DDR_MODE2 0x8080c000
129 (0 << TIMING_CFG0_WWT_SHIFT) | \
130 (0 << TIMING_CFG0_RRT_SHIFT) | \
131 (0 << TIMING_CFG0_WRT_SHIFT) | \
132 (0 << TIMING_CFG0_RWT_SHIFT))
148 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
151 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
153 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
162 #define CONFIG_SYS_LCRR_DBYP 0x80000000
163 #define CONFIG_SYS_LCRR_EADC 0x00010000
164 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
166 #define CONFIG_SYS_LBC_LBCR 0x00000000
171 #define CONFIG_SYS_IBAT7L (0)
172 #define CONFIG_SYS_IBAT7U (0)