Lines Matching +full:0 +full:xe8000000
32 #define CONFIG_KM_DEF_ARCH "arch=ppc_8xx\0"
70 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
76 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
78 #define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
79 (0x200 << SDRAM_INTERVAL_REFINT_SHIFT))
86 #define CONFIG_SYS_DDR_MODE 0x47860242
87 #define CONFIG_SYS_DDR_MODE2 0x8080c000
93 (0 << TIMING_CFG0_WWT_SHIFT) | \
94 (0 << TIMING_CFG0_RRT_SHIFT) | \
95 (0 << TIMING_CFG0_WRT_SHIFT) | \
96 (0 << TIMING_CFG0_RWT_SHIFT))
112 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
115 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
117 #define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
126 #define CONFIG_SYS_LCRR_DBYP 0x80000000
127 #define CONFIG_SYS_LCRR_EADC 0x00010000
128 #define CONFIG_SYS_LCRR_CLKDIV 0x00000002
130 #define CONFIG_SYS_LBC_LBCR 0x00000000
135 #define CONFIG_SYS_IBAT7L (0)
136 #define CONFIG_SYS_IBAT7U (0)