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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-div6-clock.yaml36 "<0>".
39 const: 0
57 reg = <0xe6150000 0x10000>;
68 reg = <0xe615007c 4>;
69 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>,
71 #clock-cells = <0>;
H A Drenesas,cpg-mssr.yaml85 const: 0
118 reg = <0xe6150000 0x1000>;
122 #power-domain-cells = <0>;
H A Drenesas,cpg-clocks.yaml45 minimum: 0
49 const: 0
234 reg = <0xe6150000 0x10000>;
240 renesas,mode = <0x05>;
/openbmc/u-boot/arch/arm/mach-rmobile/include/mach/
H A Dr8a7740.h13 #define MERAM_BASE 0xE5580000
14 #define DDRP_BASE 0xC12A0000
15 #define HPB_BASE 0xE6000000
16 #define RWDT0_BASE 0xE6020000
17 #define RWDT1_BASE 0xE6030000
18 #define GPIO_BASE 0xE6050000
19 #define CMT1_BASE 0xE6138000
20 #define CPG_BASE 0xE6150000
21 #define SYSC_BASE 0xE6180000
22 #define SDHI0_BASE 0xE6850000
[all …]
H A Dsh73a0.h5 #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
6 #define MERAM_BASE (0xE5580000)
9 #define GIC_BASE (0xF0000100)
13 #define LIFEC_SEC_SRC (0xE6110008)
16 #define RWDT_BASE (0xE6020000)
19 #define HPB_BASE (0xE6001010)
22 #define HPBSCR_BASE (0xE6001600)
25 #define SBSC1_BASE (0xFE400000)
26 #define SDMRA1A (SBSC1_BASE + 0x100000)
27 #define SDMRA2A (SBSC1_BASE + 0x1C0000)
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a77990.dtsi19 #size-cells = <0>;
21 a53_0: cpu@0 {
23 reg = <0>;
39 L2_CA53: cache-controller-0 {
49 #clock-cells = <0>;
51 clock-frequency = <0>;
76 reg = <0 0xe6020000 0 0x0c>;
86 reg = <0 0xe6050000 0 0x50>;
90 gpio-ranges = <&pfc 0 0 18>;
101 reg = <0 0xe6051000 0 0x50>;
[all …]
H A Dr8a7792.dtsi39 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
69 L2_CA15: cache-controller-0 {
80 #clock-cells = <0>;
82 clock-frequency = <0>;
95 #clock-cells = <0>;
97 clock-frequency = <0>;
[all …]
H A Dr8a77970.dtsi29 #size-cells = <0>;
31 a53_0: cpu@0 {
34 reg = <0>;
61 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
70 clock-frequency = <0>;
88 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77995.dtsi21 #clock-cells = <0>;
22 clock-frequency = <0>;
27 #size-cells = <0>;
29 a53_0: cpu@0 {
31 reg = <0x0>;
48 #clock-cells = <0>;
50 clock-frequency = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
79 reg = <0 0xe6020000 0 0x0c>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7791.dtsi40 * The external audio clocks are configured as 0 Hz fixed frequency
46 #clock-cells = <0>;
47 clock-frequency = <0>;
51 #clock-cells = <0>;
52 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
65 clock-frequency = <0>;
70 #size-cells = <0>;
[all …]
H A Dr8a77965.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
46 #clock-cells = <0>;
47 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
60 clock-frequency = <0>;
65 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
[all …]
H A Dr8a73a4.dtsi21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0>;
33 L2_CA15: cache-controller-0 {
65 reg = <0 0xe6790000 0 0x10000>;
71 reg = <0 0xe67a0000 0 0x10000>;
77 #size-cells = <0>;
79 reg = <0 0xe60b0000 0 0x428>;
89 reg = <0 0xe6130000 0 0x1004>;
108 reg = <0 0xe61c0000 0 0x200>;
[all …]
H A Dr8a7792.dtsi40 #clock-cells = <0>;
42 clock-frequency = <0>;
47 #size-cells = <0>;
49 cpu0: cpu@0 {
52 reg = <0>;
71 L2_CA15: cache-controller-0 {
82 #clock-cells = <0>;
84 clock-frequency = <0>;
97 #clock-cells = <0>;
99 clock-frequency = <0>;
[all …]
H A Dsh73a0.dtsi20 #size-cells = <0>;
22 cpu0: cpu@0 {
25 reg = <0>;
44 reg = <0xf0000200 0x100>;
51 reg = <0xf0000600 0x20>;
60 reg = <0xf0001000 0x1000>,
61 <0xf0000100 0x100>;
66 reg = <0xf0100000 0x1000>;
78 reg = <0xfb400000 0x400>;
87 reg = <0xfe400000 0x400>;
[all …]
H A Dr8a77470.dtsi27 #size-cells = <0>;
29 cpu0: cpu@0 {
32 reg = <0>;
51 L2_CA7: cache-controller-0 {
62 #clock-cells = <0>;
64 clock-frequency = <0>;
77 #clock-cells = <0>;
79 clock-frequency = <0>;
93 reg = <0 0xe6020000 0 0x0c>;
104 reg = <0 0xe6050000 0 0x50>;
[all …]
H A Dr8a7794.dtsi34 * The external audio clocks are configured as 0 Hz fixed frequency
40 #clock-cells = <0>;
41 clock-frequency = <0>;
45 #clock-cells = <0>;
46 clock-frequency = <0>;
50 #clock-cells = <0>;
51 clock-frequency = <0>;
57 #clock-cells = <0>;
59 clock-frequency = <0>;
64 #size-cells = <0>;
[all …]
H A Dr8a7793.dtsi32 * The external audio clocks are configured as 0 Hz fixed frequency
38 #clock-cells = <0>;
39 clock-frequency = <0>;
43 #clock-cells = <0>;
44 clock-frequency = <0>;
48 #clock-cells = <0>;
49 clock-frequency = <0>;
55 #clock-cells = <0>;
57 clock-frequency = <0>;
62 #size-cells = <0>;
[all …]
H A Dr8a7745.dtsi36 * The external audio clocks are configured as 0 Hz fixed
42 #clock-cells = <0>;
43 clock-frequency = <0>;
47 #clock-cells = <0>;
48 clock-frequency = <0>;
52 #clock-cells = <0>;
53 clock-frequency = <0>;
59 #clock-cells = <0>;
61 clock-frequency = <0>;
66 #size-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77970.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
60 #clock-cells = <0>;
62 clock-frequency = <0>;
67 #clock-cells = <0>;
69 clock-frequency = <0>;
87 #clock-cells = <0>;
[all …]
H A Dr8a779f0.dtsi17 cluster01_opp: opp-table-0 {
73 #size-cells = <0>;
113 a55_0: cpu@0 {
115 reg = <0>;
127 reg = <0x100>;
139 reg = <0x10000>;
151 reg = <0x10100>;
163 reg = <0x20000>;
175 reg = <0x20100>;
187 reg = <0x30000>;
[all …]
H A Dr8a77980.dtsi22 #clock-cells = <0>;
23 clock-frequency = <0>;
28 #size-cells = <0>;
30 a53_0: cpu@0 {
33 reg = <0>;
80 #clock-cells = <0>;
82 clock-frequency = <0>;
87 #clock-cells = <0>;
89 clock-frequency = <0>;
95 #clock-cells = <0>;
[all …]
H A Dr8a77995.dtsi19 * The external audio clocks are configured as 0 Hz fixed frequency
25 #clock-cells = <0>;
26 clock-frequency = <0>;
31 #clock-cells = <0>;
32 clock-frequency = <0>;
38 #clock-cells = <0>;
39 clock-frequency = <0>;
44 #size-cells = <0>;
46 a53_0: cpu@0 {
48 reg = <0x0>;
[all …]

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