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Searched +full:0 +full:xe2800000 (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/staging/board/
H A Dkzm9d.c9 DEFINE_RES_MEM(0xe2800000, 0x2000),
/openbmc/u-boot/include/configs/
H A D3c120_devboard.h29 #define CONFIG_SYS_RX_ETH_BUFFER 0
48 #define CONFIG_SYS_SDRAM_BASE 0xD0000000
49 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
51 #define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
55 #define CONFIG_SYS_MALLOC_LEN 0x20000
65 #define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */
67 #define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN)
72 #define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */
78 0x10000)
H A DMPC8568MDS.h40 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
41 #define CONFIG_SYS_MEMTEST_END 0x00400000
43 #define CONFIG_SYS_CCSRBAR 0xe0000000
51 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
60 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
76 * Boot from BR0/OR0 bank at 0xff00_0000
77 * Alternate BR1/OR1 bank at 0xff80_0000
80 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
81 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
[all …]
H A DMPC8569MDS.h52 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
53 #define CONFIG_SYS_MEMTEST_END 0x00400000
58 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
63 #define CONFIG_SYS_CCSRBAR 0xe0000000
75 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
85 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
89 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
90 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
91 #define CONFIG_SYS_DDR_TIMING_3 0x00020000
[all …]
H A Dsbc8548.h79 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
80 #define CONFIG_SYS_MEMTEST_END 0x00400000
82 #define CONFIG_SYS_CCSRBAR 0xe0000000
93 * for a device at 0x53.
99 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
110 * SPD at 0x53, but if we are running on an older board w/o the
111 * fix, it will still be at 0x51. We check 0x53 1st.
113 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
114 #define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */
[all …]
H A DMPC8313ERDB.h30 #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
32 #define CONFIG_SPL_PAD_TO 0x4000
35 #define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
36 #define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
38 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
39 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
73 #define CONFIG_SYS_IMMR 0xE0000000
79 #define CONFIG_SYS_MEMTEST_START 0x00001000
80 #define CONFIG_SYS_MEMTEST_END 0x07f00000
88 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
[all …]
/openbmc/qemu/bsd-user/arm/
H A Dtarget_arch_sigtramp.h30 /* 1 */ 0xE1A0000D, /* mov r0, sp */ in setup_sigtramp()
31 /* 2 */ 0xE2800000 + sigf_uc, /* add r0, r0, #SIGF_UC */ in setup_sigtramp()
32 /* 3 */ 0xE59F700C, /* ldr r7, [pc, #12] */ in setup_sigtramp()
33 /* 4 */ 0xEF000000 + sys_sigreturn, /* swi (SYS_sigreturn) */ in setup_sigtramp()
34 /* 5 */ 0xE59F7008, /* ldr r7, [pc, #8] */ in setup_sigtramp()
35 /* 6 */ 0xEF000000 + sys_exit, /* swi (SYS_exit)*/ in setup_sigtramp()
36 /* 7 */ 0xEAFFFFFA, /* b . -16 */ in setup_sigtramp()
43 for (i = 0; i < 9; i++) { in setup_sigtramp()
/openbmc/u-boot/board/sbc8548/
H A Dtlb.c13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
19 MAS3_SX|MAS3_SW|MAS3_SR, 0,
20 0, 0, BOOKE_PAGESZ_4K, 0),
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
[all …]
/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S23 mov r5, #0
28 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
29 orr r0, r0, #0x0
34 ldr r1, =0x9
38 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
40 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
43 mvn r3, #0x0
44 str r3, [r0, #0x14] @INTENCLEAR
45 str r3, [r1, #0x14] @INTENCLEAR
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear1340.dtsi17 reg = <0xe0700000 0x1000>;
18 st-spics,peripcfg-reg = <0x42c>;
30 reg = <0xeb800000 0x4000>;
38 reg = <0xb1000000 0x10000>;
39 interrupts = <0 72 0x4>;
40 phys = <&miphy0 0>;
47 reg = <0xb1000000 0x4000>, <0x80000000 0x20000>;
49 interrupts = <0 68 0x4>;
56 ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
57 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml137 enum: [0, 1]
158 enum: [0, 1, 2]
159 default: 0
185 reg = <0xe0100000 0x1000>;
189 interrupts = <0 24 4>;
195 reg = <0xe2800000 0x1000>;
199 interrupts = <0 24 4>;
210 reg = <0xfe330000 0x10000>;
220 #clock-cells = <0>;
227 interrupts = <0 48 4>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
H A Dmpc8569mds.dts30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc8313erdb.dts26 #size-cells = <0>;
28 PowerPC,8313@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210.dtsi46 #size-cells = <0>;
48 cpu@0 {
51 reg = <0>;
55 xxti: oscillator-0 {
57 clock-frequency = <0>;
59 #clock-cells = <0>;
64 clock-frequency = <0>;
66 #clock-cells = <0>;
77 reg = <0xb0600000 0x2000>,
78 <0xb0000000 0x20000>,
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
88 hysteresis = <0>;
94 hysteresis = <0>;
100 hysteresis = <0>;
122 #clock-cells = <0>;
127 #clock-cells = <0>;
132 #clock-cells = <0>;
151 reg = <0x100000 0x20000>;
[all …]