Lines Matching +full:0 +full:xe2800000
40 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
41 #define CONFIG_SYS_MEMTEST_END 0x00400000
43 #define CONFIG_SYS_CCSRBAR 0xe0000000
51 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
60 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
76 * Boot from BR0/OR0 bank at 0xff00_0000
77 * Alternate BR1/OR1 bank at 0xff80_0000
80 * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
81 * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
86 * 0 4 8 12 16 20 24 28
91 * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
99 * 0 4 8 12 16 20 24 28
102 #define CONFIG_SYS_BCSR_BASE 0xf8000000
104 #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */
106 /*Chip select 0 - Flash*/
107 #define CONFIG_SYS_BR0_PRELIM 0xfe001001
108 #define CONFIG_SYS_OR0_PRELIM 0xfe006ff7
111 #define CONFIG_SYS_BR1_PRELIM 0xf8000801
112 #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7
114 /*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */
128 #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
132 #define CONFIG_SYS_BR2_PRELIM 0xf0001861
133 #define CONFIG_SYS_OR2_PRELIM 0xfc006901
135 #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
136 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
137 #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
138 #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
157 * The new memory map places bcsr at 0xf8000000.
160 * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
166 * 0 4 8 12 16 20 24 28
170 * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
171 * disable buffer ctrl OR[19] = 0
176 * SETA OR[28] = 0
181 * 0 4 8 12 16 20 24 28
184 #define CONFIG_SYS_BCSR (0xf8000000)
187 #define CONFIG_SYS_BR4_PRELIM 0xf8008801
188 #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7
191 #define CONFIG_SYS_BR5_PRELIM 0xf8010801
192 #define CONFIG_SYS_OR5_PRELIM 0xffff69f7
195 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
196 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
212 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
213 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
221 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
222 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
224 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
225 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
226 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
227 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
231 * Memory Addresses are mapped 1-1. I/O is mapped from 0
233 #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
234 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
235 #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
236 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
237 #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
238 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
239 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
240 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
243 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
244 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
245 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
246 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
247 #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
248 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
249 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
250 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
252 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000
253 #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000
255 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
269 #define CONFIG_MIIM_ADDRESS 0xE0024520
275 #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
302 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
316 #define TSEC1_PHYIDX 0
317 #define TSEC2_PHYIDX 0
322 /* Options are: eTSEC[0-1] */
330 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
331 #define CONFIG_ENV_SIZE 0x2000
347 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
386 "netdev=eth0\0" \
387 "consoledev=ttyS0\0" \
388 "ramdiskaddr=600000\0" \
389 "ramdiskfile=your.ramdisk.u-boot\0" \
390 "fdtaddr=400000\0" \
391 "fdtfile=your.fdt.dtb\0" \
395 "console=$consoledev,$baudrate $othbootargs\0" \
397 "console=$consoledev,$baudrate $othbootargs\0" \