Lines Matching +full:0 +full:xe2800000
23 mov r5, #0
28 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
29 orr r0, r0, #0x0
34 ldr r1, =0x9
38 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
40 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
43 mvn r3, #0x0
44 str r3, [r0, #0x14] @INTENCLEAR
45 str r3, [r1, #0x14] @INTENCLEAR
46 str r3, [r2, #0x14] @INTENCLEAR
49 str r5, [r0, #0xc] @INTSELECT
50 str r5, [r1, #0xc] @INTSELECT
51 str r5, [r2, #0xc] @INTSELECT
54 str r5, [r0, #0xf00] @INTADDRESS
55 str r5, [r1, #0xf00] @INTADDRESS
56 str r5, [r2, #0xf00] @INTADDRESS
73 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
76 ldr r1, =0x00011110
77 str r1, [r8, #0x304]
78 ldr r1, =0x1
79 str r1, [r8, #0x308]
80 ldr r1, =0x00011301
81 str r1, [r8, #0x300]
84 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
85 str r1, [r8, #0x000] @ APLL_LOCK
86 str r1, [r8, #0x004] @ MPLL_LOCK
87 str r1, [r8, #0x008] @ EPLL_LOCK
88 str r1, [r8, #0x00C] @ HPLL_LOCK
91 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
92 str r1, [r8, #0x100]
94 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
95 str r1, [r8, #0x104]
97 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
98 str r1, [r8, #0x108]
100 ldr r1, =0x80600603
101 str r1, [r8, #0x10C]
104 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
105 str r1, [r8, #0x200] @ CLK_SRC0
107 ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
108 str r1, [r8, #0x204] @ CLK_SRC1
110 ldr r1, =0x9000 @ ARMCLK/4
111 str r1, [r8, #0x400] @ CLK_OUT
114 mov r2, #0x10000
125 ldr r1, =0x22222222
126 str r1, [r0, #0x0] @ GPA0_CON
127 ldr r1, =0x00022222
128 str r1, [r0, #0x20] @ GPA1_CON
136 ldr r0, =0xE3800000
137 mov r1, #0x0
139 mov r1, #0xff
140 str r1, [r0, #0x804]
141 str r1, [r0, #0x810]
143 ldr r0, =0xE2800000
144 str r1, [r0, #0x804]
145 str r1, [r0, #0x810]
146 str r1, [r0, #0x81C]
148 ldr r0, =0xE2900000
149 str r1, [r0, #0x804]
150 str r1, [r0, #0x810]