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/openbmc/u-boot/arch/arm/mach-rockchip/
H A Drk3128-board.c22 return 0; in rk_board_late_init()
34 int ret = 0; in board_init()
44 return 0; in board_init()
49 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
50 gd->bd->bi_dram[0].size = 0x8400000; in dram_init_banksize()
51 /* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */ in dram_init_banksize()
53 + gd->bd->bi_dram[0].size + 0xe00000; in dram_init_banksize()
54 gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start in dram_init_banksize()
57 return 0; in dram_init_banksize()
89 while (node > 0) { in board_usb_init()
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D179.out11 2 MiB (0x200000) bytes not allocated at offset 0 bytes (0x0)
12 2 MiB (0x200000) bytes allocated at offset 2 MiB (0x200000)
13 2 MiB (0x200000) bytes not allocated at offset 4 MiB (0x400000)
14 2 MiB (0x200000) bytes allocated at offset 6 MiB (0x600000)
15 56 MiB (0x3800000) bytes not allocated at offset 8 MiB (0x800000)
16 [{ "start": 0, "length": 2097152, "depth": 0, "present": false, "zero": true, "data": false, "compr…
17 { "start": 2097152, "length": 2097152, "depth": 0, "present": true, "zero": true, "data": false, "c…
18 { "start": 4194304, "length": 2097152, "depth": 0, "present": false, "zero": true, "data": false, "…
19 { "start": 6291456, "length": 2097152, "depth": 0, "present": true, "zero": true, "data": false, "c…
20 { "start": 8388608, "length": 58720256, "depth": 0, "present": false, "zero": true, "data": false, …
[all …]
/openbmc/u-boot/include/configs/
H A Dls1088aqds.h18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_ENV_SIZE 0x20000
21 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
28 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #define CONFIG_SYS_MMC_ENV_DEV 0
32 #define CONFIG_ENV_SIZE 0x2000
34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
35 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dpm9g45.h53 #define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */
64 #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
68 #define PHYS_SDRAM 0x70000000
69 #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
74 #define CONFIG_SYS_NAND_BASE 0x40000000
96 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */
101 #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
103 #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */
109 #define CONFIG_ENV_OFFSET 0x60000
110 #define CONFIG_ENV_OFFSET_REDUND 0x80000
[all …]
H A Dls1088ardb.h12 #define CONFIG_SYS_MMC_ENV_DEV 0
14 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
15 #define CONFIG_ENV_OFFSET 0x500000
18 #define CONFIG_ENV_SECT_SIZE 0x40000
21 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
22 #define CONFIG_ENV_SECT_SIZE 0x40000
25 #define CONFIG_SYS_MMC_ENV_DEV 0
26 #define CONFIG_ENV_SIZE 0x2000
29 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
30 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-7040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
33 regulator-name = "cp0-usb3-0-current-regulator";
38 states = <500000 0x0
39 900000 0x1>;
41 gpios-states = <0>;
51 states = <500000 0x0
52 900000 0x1>;
54 gpios-states = <0>;
57 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
[all …]
H A Dcn9130-db.dtsi28 memory@0 {
30 reg = <0x0 0x0 0x0 0x80000000>;
33 ap0_reg_sd_vccq: ap0_sd_vccq@0 {
39 states = <1800000 0x1 3300000 0x0>;
42 cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
48 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
51 cp0_usb3_0_phy0: cp0_usb3_phy@0 {
70 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
76 states = <1800000 0x1
77 3300000 0x0>;
[all …]
H A Dcn9131-db.dtsi21 cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
24 pinctrl-0 = <&cp1_xhci0_vbus_pins>;
45 pinctrl-0 = <&cp1_sfp_pins>;
61 #define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
62 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
90 phys = <&cp1_comphy4 0>;
106 pinctrl-0 = <&cp1_i2c0_pins>;
113 pinctrl-0 = <&cp1_pcie_reset_pins>;
116 marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
119 phys = <&cp1_comphy0 0
[all …]
H A Darmada-8040-db.dts20 memory@0 {
22 reg = <0x0 0x0 0x0 0x80000000>;
34 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
40 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
52 cp0_usb3_0_phy: cp0-usb3-0-phy {
57 cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
63 gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
66 cp1_usb3_0_phy: cp1-usb3-0-phy {
75 flash@0 {
77 reg = <0>;
[all …]
H A Dcn9130-crb.dtsi24 memory@0 {
26 reg = <0x0 0x0 0x0 0x80000000>;
29 ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
35 states = <1800000 0x1
36 3300000 0x0>;
57 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
63 states = <1800000 0x1
64 3300000 0x0>;
67 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
106 cp0_i2c0_pins: cp0-i2c-pins-0 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/partitions/
H A Dnvmem-cells.yaml44 reg = <0x1200000 0x0140000>;
50 macaddr_gmac1: macaddr_gmac1@0 {
51 reg = <0x0 0x6>;
55 reg = <0x6 0x6>;
59 reg = <0x1000 0x2f20>;
63 reg = <0x5000 0x2f20>;
72 partition@0 {
74 reg = <0x000000 0x100000>;
81 reg = <0x100000 0xe00000>;
87 reg = <0xf00000 0x100000>;
[all …]
H A Dfixed-partitions.yaml33 "@[0-9a-f]+$":
59 partition@0 {
61 reg = <0x0000000 0x100000>;
66 reg = <0x0100000 0x200000>;
77 partition@0 {
79 reg = <0x00000000 0x1 0x00000000>;
91 partition@0 {
93 reg = <0x0 0x00000000 0x2 0x00000000>;
99 reg = <0x2 0x00000000 0x1 0x00000000>;
109 partition@0 {
[all …]
/openbmc/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-hdmi.c25 /* REG: 0x00 */
26 #define RK3228_PRE_PLL_REFCLK_SEL_PCLK BIT(0)
27 /* REG: 0x01 */
30 #define RK3228_BYPASS_PLLPD_EN BIT(0)
31 /* REG: 0x02 */
33 #define RK3228_PDATAEN_DISABLE BIT(0)
34 /* REG: 0x03 */
36 #define RK3228_AUTO_TERM_RES_CAL_SPEED_14_8(x) UPDATE(x, 6, 0)
37 /* REG: 0x04 */
38 #define RK3228_AUTO_TERM_RES_CAL_SPEED_7_0(x) UPDATE(x, 7, 0)
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-7040-db-nand.dts45 * Boot device: NAND, 0xE (SW3)
67 reg = <0x0 0x0 0x0 0x80000000>;
73 * SDIO [0-5]
76 /* 0 1 2 3 4 5 6 7 8 9 */
77 pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
78 0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
92 pinctrl-0 = <&cpm_i2c0_pins>;
99 * AUDIO [0-5]
115 /* 0 1 2 3 4 5 6 7 8 9 */
116 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
[all …]
H A Darmada-7040-db.dts45 * Boot device: SPI NOR, 0x32 (SW3)
66 reg = <0x0 0x0 0x0 0x80000000>;
72 * SDIO [0-5]
75 /* 0 1 2 3 4 5 6 7 8 9 */
76 pin-func = < 1 1 1 1 1 1 0 0 0 0
77 0 3 0 0 0 0 0 0 0 3 >;
91 pinctrl-0 = <&cpm_i2c0_pins>;
98 * TDM [0-11]
108 /* 0 1 2 3 4 5 6 7 8 9 */
110 4 4 0 3 3 3 3 0 0 0
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-dir665.dts18 reg = <0x00000000 0x8000000>; /* 128 MB */
28 pinctrl-0 =< &pmx_led_usb
81 flash@0 {
86 reg = <0>;
88 partition@0 {
90 reg = <0x0 0x30000>;
96 reg = <0x30000 0x10000>;
102 reg = <0x40000 0x180000>;
107 reg = <0x1c0000 0xe00000>;
112 reg = <0xfc0000 0x10000>;
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dgoya_masks.h180 ) & 0x7FFFFF)
191 #define GOYA_IRQ_HBW_ID_MASK 0x1FFF
192 #define GOYA_IRQ_HBW_ID_SHIFT 0
193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000
195 #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000
197 #define GOYA_IRQ_HBW_Y_MASK 0xE00000
199 #define GOYA_IRQ_HBW_X_MASK 0x7000000
201 #define GOYA_IRQ_LBW_ID_MASK 0xFF
202 #define GOYA_IRQ_LBW_ID_SHIFT 0
203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700
[all …]
/openbmc/qemu/include/hw/arm/
H A Draspi_platform.h67 #define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
68 #define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
69 #define INTE_OFFSET 0x2000 /* VC Interrupt controller */
70 #define ST_OFFSET 0x3000 /* System Timer */
71 #define TXP_OFFSET 0x4000 /* Transposer */
72 #define JPEG_OFFSET 0x5000
73 #define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
74 #define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
75 #define ARBA_OFFSET 0x9000
76 #define BRDG_OFFSET 0xa000 /* RPiVid ASB for BCM2838 (BCM2711) */
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp43x-gateworks-gw2358.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
66 reg = <0x56>;
73 reg = <0x57>;
81 flash@0,0 {
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dm5307sim.h27 #define MCFSIM_RSR (MCF_MBAR + 0x00) /* Reset Status reg */
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
29 #define MCFSIM_SWIVR (MCF_MBAR + 0x02) /* SW Watchdog intr */
30 #define MCFSIM_SWSR (MCF_MBAR + 0x03) /* SW Watchdog service*/
31 #define MCFSIM_PAR (MCF_MBAR + 0x04) /* Pin Assignment */
32 #define MCFSIM_IRQPAR (MCF_MBAR + 0x06) /* Itr Assignment */
33 #define MCFSIM_PLLCR (MCF_MBAR + 0x08) /* PLL Ctrl Reg */
34 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
35 #define MCFSIM_IPR (MCF_MBAR + 0x40) /* Interrupt Pend */
36 #define MCFSIM_IMR (MCF_MBAR + 0x44) /* Interrupt Mask */
[all …]
/openbmc/linux/arch/csky/kernel/probes/
H A Dsimulate-insn.c18 *ptr = *(&regs->exregs[0] + index - 16); in csky_insn_reg_get_val()
47 *(&regs->exregs[0] + index - 16) = val; in csky_insn_reg_set_val()
72 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_br16()
79 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_br32()
87 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bt16()
97 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bt32()
107 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bf16()
117 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bf32()
125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16()
[all …]
/openbmc/linux/drivers/remoteproc/
H A Dti_k3_dsp_remoteproc.c118 dev_dbg(dev, "mbox msg: 0x%x\n", msg); in k3_dsp_rproc_mbox_callback()
136 dev_dbg(dev, "dropping unknown message 0x%x", msg); in k3_dsp_rproc_mbox_callback()
160 if (ret < 0) in k3_dsp_rproc_kick()
232 kproc->mbox = mbox_request_channel(client, 0); in k3_dsp_rproc_request_mbox()
248 if (ret < 0) { in k3_dsp_rproc_request_mbox()
254 return 0; in k3_dsp_rproc_request_mbox()
324 dev_err(dev, "invalid boot address 0x%x, must be aligned on a 0x%x boundary\n", in k3_dsp_rproc_start()
330 dev_err(dev, "booting DSP core using boot addr = 0x%x\n", boot_addr); in k3_dsp_rproc_start()
331 ret = ti_sci_proc_set_config(kproc->tsp, boot_addr, 0, 0); in k3_dsp_rproc_start()
339 return 0; in k3_dsp_rproc_start()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/openbmc/linux/net/ipv6/
H A Dioam6_iptunnel.c25 #define IOAM6_MASK_SHORT_FIELDS 0xff100000
26 #define IOAM6_MASK_WIDE_FIELDS 0xe00000
91 trace->nodelen = 0; in ioam6_validate_trace_hdr()
121 if (err < 0) in ioam6_build_state()
175 atomic_set(&ilwt->pkt_cnt, 0); in ioam6_build_state()
185 tuninfo->pad[0] = IPV6_TLV_PADN; in ioam6_build_state()
203 return 0; in ioam6_build_state()
219 return 0; in ioam6_do_fill()
362 memset(&fl6, 0, sizeof(fl6)); in ioam6_output()

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