1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay #ifndef ASIC_REG_GOYA_MASKS_H_ 9*e65e175bSOded Gabbay #define ASIC_REG_GOYA_MASKS_H_ 10*e65e175bSOded Gabbay 11*e65e175bSOded Gabbay #include "goya_regs.h" 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay /* Useful masks for bits in various registers */ 14*e65e175bSOded Gabbay #define QMAN_DMA_ENABLE (\ 15*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT) | \ 16*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT) | \ 17*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT) | \ 18*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT)) 19*e65e175bSOded Gabbay 20*e65e175bSOded Gabbay #define QMAN_DMA_FULLY_TRUSTED (\ 21*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \ 22*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \ 23*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \ 24*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT) | \ 25*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ 26*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ 27*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ 28*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT)) 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay #define QMAN_DMA_PARTLY_TRUSTED (\ 31*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \ 32*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \ 33*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \ 34*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ 35*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ 36*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ 37*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT)) 38*e65e175bSOded Gabbay 39*e65e175bSOded Gabbay #define QMAN_DMA_STOP (\ 40*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT) | \ 41*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT) | \ 42*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT) | \ 43*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT)) 44*e65e175bSOded Gabbay 45*e65e175bSOded Gabbay #define QMAN_DMA_IS_STOPPED (\ 46*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT) | \ 47*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT) | \ 48*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT) | \ 49*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT)) 50*e65e175bSOded Gabbay 51*e65e175bSOded Gabbay #define QMAN_DMA_ERR_MSG_EN (\ 52*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ 53*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ 54*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ 55*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ 56*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ 57*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ 58*e65e175bSOded Gabbay (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT)) 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define QMAN_MME_ENABLE (\ 61*e65e175bSOded Gabbay (1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 62*e65e175bSOded Gabbay (1 << MME_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 63*e65e175bSOded Gabbay (1 << MME_QM_GLBL_CFG0_CP_EN_SHIFT)) 64*e65e175bSOded Gabbay 65*e65e175bSOded Gabbay #define CMDQ_MME_ENABLE (\ 66*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \ 67*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT)) 68*e65e175bSOded Gabbay 69*e65e175bSOded Gabbay #define QMAN_MME_STOP (\ 70*e65e175bSOded Gabbay (1 << MME_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \ 71*e65e175bSOded Gabbay (1 << MME_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \ 72*e65e175bSOded Gabbay (1 << MME_QM_GLBL_CFG1_CP_STOP_SHIFT)) 73*e65e175bSOded Gabbay 74*e65e175bSOded Gabbay #define CMDQ_MME_STOP (\ 75*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \ 76*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT)) 77*e65e175bSOded Gabbay 78*e65e175bSOded Gabbay #define QMAN_MME_ERR_MSG_EN (\ 79*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ 80*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ 81*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ 82*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ 83*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ 84*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ 85*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ 86*e65e175bSOded Gabbay (1 << MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define CMDQ_MME_ERR_MSG_EN (\ 89*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ 90*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ 91*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ 92*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ 93*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ 94*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ 95*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ 96*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay #define QMAN_MME_ERR_PROT (\ 99*e65e175bSOded Gabbay (1 << MME_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ 100*e65e175bSOded Gabbay (1 << MME_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ 101*e65e175bSOded Gabbay (1 << MME_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ 102*e65e175bSOded Gabbay (1 << MME_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT)) 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay #define CMDQ_MME_ERR_PROT (\ 105*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ 106*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ 107*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ 108*e65e175bSOded Gabbay (1 << MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT)) 109*e65e175bSOded Gabbay 110*e65e175bSOded Gabbay #define QMAN_TPC_ENABLE (\ 111*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 112*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 113*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT)) 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define CMDQ_TPC_ENABLE (\ 116*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \ 117*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT)) 118*e65e175bSOded Gabbay 119*e65e175bSOded Gabbay #define QMAN_TPC_STOP (\ 120*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \ 121*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \ 122*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT)) 123*e65e175bSOded Gabbay 124*e65e175bSOded Gabbay #define CMDQ_TPC_STOP (\ 125*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \ 126*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT)) 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay #define QMAN_TPC_ERR_MSG_EN (\ 129*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ 130*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ 131*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ 132*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ 133*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ 134*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ 135*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ 136*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay #define CMDQ_TPC_ERR_MSG_EN (\ 139*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ 140*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ 141*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \ 142*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \ 143*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ 144*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ 145*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ 146*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT)) 147*e65e175bSOded Gabbay 148*e65e175bSOded Gabbay #define QMAN_TPC_ERR_PROT (\ 149*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ 150*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ 151*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ 152*e65e175bSOded Gabbay (1 << TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT)) 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay #define CMDQ_TPC_ERR_PROT (\ 155*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \ 156*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \ 157*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \ 158*e65e175bSOded Gabbay (1 << TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT)) 159*e65e175bSOded Gabbay 160*e65e175bSOded Gabbay /* RESETS */ 161*e65e175bSOded Gabbay #define DMA_MME_TPC_RESET (\ 162*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\ 163*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\ 164*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT) 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay #define RESET_ALL (\ 167*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\ 168*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\ 169*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT |\ 170*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT |\ 171*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT |\ 172*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT |\ 173*e65e175bSOded Gabbay PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK |\ 174*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT |\ 175*e65e175bSOded Gabbay 1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT) 176*e65e175bSOded Gabbay 177*e65e175bSOded Gabbay #define CA53_RESET (\ 178*e65e175bSOded Gabbay (~\ 179*e65e175bSOded Gabbay (1 << PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT)\ 180*e65e175bSOded Gabbay ) & 0x7FFFFF) 181*e65e175bSOded Gabbay 182*e65e175bSOded Gabbay #define CPU_RESET_ASSERT (\ 183*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) 184*e65e175bSOded Gabbay 185*e65e175bSOded Gabbay #define CPU_RESET_CORE0_DEASSERT (\ 186*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\ 187*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\ 188*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\ 189*e65e175bSOded Gabbay 1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT) 190*e65e175bSOded Gabbay 191*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_ID_MASK 0x1FFF 192*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_ID_SHIFT 0 193*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_INTERNAL_ID_MASK 0xE000 194*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_INTERNAL_ID_SHIFT 13 195*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_AGENT_ID_MASK 0x1F0000 196*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_AGENT_ID_SHIFT 16 197*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_Y_MASK 0xE00000 198*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_Y_SHIFT 21 199*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_X_MASK 0x7000000 200*e65e175bSOded Gabbay #define GOYA_IRQ_HBW_X_SHIFT 24 201*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_ID_MASK 0xFF 202*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_ID_SHIFT 0 203*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_INTERNAL_ID_MASK 0x700 204*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_INTERNAL_ID_SHIFT 8 205*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_AGENT_ID_MASK 0xF800 206*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_AGENT_ID_SHIFT 11 207*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_Y_MASK 0x70000 208*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_Y_SHIFT 16 209*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_X_MASK 0x380000 210*e65e175bSOded Gabbay #define GOYA_IRQ_LBW_X_SHIFT 19 211*e65e175bSOded Gabbay 212*e65e175bSOded Gabbay #define DMA_QM_IDLE_MASK (DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK | \ 213*e65e175bSOded Gabbay DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK | \ 214*e65e175bSOded Gabbay DMA_QM_0_GLBL_STS0_CP_IDLE_MASK | \ 215*e65e175bSOded Gabbay DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK) 216*e65e175bSOded Gabbay 217*e65e175bSOded Gabbay #define TPC_QM_IDLE_MASK (TPC0_QM_GLBL_STS0_PQF_IDLE_MASK | \ 218*e65e175bSOded Gabbay TPC0_QM_GLBL_STS0_CQF_IDLE_MASK | \ 219*e65e175bSOded Gabbay TPC0_QM_GLBL_STS0_CP_IDLE_MASK) 220*e65e175bSOded Gabbay 221*e65e175bSOded Gabbay #define TPC_CMDQ_IDLE_MASK (TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \ 222*e65e175bSOded Gabbay TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK) 223*e65e175bSOded Gabbay 224*e65e175bSOded Gabbay #define TPC_CFG_IDLE_MASK (TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \ 225*e65e175bSOded Gabbay TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \ 226*e65e175bSOded Gabbay TPC0_CFG_STATUS_IQ_EMPTY_MASK | \ 227*e65e175bSOded Gabbay TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK) 228*e65e175bSOded Gabbay 229*e65e175bSOded Gabbay #define MME_QM_IDLE_MASK (MME_QM_GLBL_STS0_PQF_IDLE_MASK | \ 230*e65e175bSOded Gabbay MME_QM_GLBL_STS0_CQF_IDLE_MASK | \ 231*e65e175bSOded Gabbay MME_QM_GLBL_STS0_CP_IDLE_MASK) 232*e65e175bSOded Gabbay 233*e65e175bSOded Gabbay #define MME_CMDQ_IDLE_MASK (MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \ 234*e65e175bSOded Gabbay MME_CMDQ_GLBL_STS0_CP_IDLE_MASK) 235*e65e175bSOded Gabbay 236*e65e175bSOded Gabbay #define MME_ARCH_IDLE_MASK (MME_ARCH_STATUS_SB_A_EMPTY_MASK | \ 237*e65e175bSOded Gabbay MME_ARCH_STATUS_SB_B_EMPTY_MASK | \ 238*e65e175bSOded Gabbay MME_ARCH_STATUS_SB_CIN_EMPTY_MASK | \ 239*e65e175bSOded Gabbay MME_ARCH_STATUS_SB_COUT_EMPTY_MASK) 240*e65e175bSOded Gabbay 241*e65e175bSOded Gabbay #define MME_SHADOW_IDLE_MASK (MME_SHADOW_0_STATUS_A_MASK | \ 242*e65e175bSOded Gabbay MME_SHADOW_0_STATUS_B_MASK | \ 243*e65e175bSOded Gabbay MME_SHADOW_0_STATUS_CIN_MASK | \ 244*e65e175bSOded Gabbay MME_SHADOW_0_STATUS_COUT_MASK | \ 245*e65e175bSOded Gabbay MME_SHADOW_0_STATUS_TE_MASK | \ 246*e65e175bSOded Gabbay MME_SHADOW_0_STATUS_LD_MASK | \ 247*e65e175bSOded Gabbay MME_SHADOW_0_STATUS_ST_MASK) 248*e65e175bSOded Gabbay 249*e65e175bSOded Gabbay #define TPC1_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT 250*e65e175bSOded Gabbay #define TPC2_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT 251*e65e175bSOded Gabbay #define TPC3_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT 252*e65e175bSOded Gabbay #define TPC4_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT 253*e65e175bSOded Gabbay #define TPC5_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT 254*e65e175bSOded Gabbay #define TPC6_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT 255*e65e175bSOded Gabbay #define TPC7_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT 256*e65e175bSOded Gabbay 257*e65e175bSOded Gabbay #define DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT 258*e65e175bSOded Gabbay #define DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT 259*e65e175bSOded Gabbay #define DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT 260*e65e175bSOded Gabbay #define DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT 261*e65e175bSOded Gabbay 262*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 263*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 264*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 265*e65e175bSOded Gabbay #define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 266*e65e175bSOded Gabbay 267*e65e175bSOded Gabbay #endif /* ASIC_REG_GOYA_MASKS_H_ */ 268