1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b5d289fcSAsen Dimov /* 3b5d289fcSAsen Dimov * (C) Copyright 2010 4b5d289fcSAsen Dimov * Ilko Iliev <iliev@ronetix.at> 5b5d289fcSAsen Dimov * Asen Dimov <dimov@ronetix.at> 6b5d289fcSAsen Dimov * Ronetix GmbH <www.ronetix.at> 7b5d289fcSAsen Dimov * 8b5d289fcSAsen Dimov * (C) Copyright 2007-2008 9c9e798d3SStelian Pop * Stelian Pop <stelian@popies.net> 10b5d289fcSAsen Dimov * Lead Tech Design <www.leadtechdesign.com> 11b5d289fcSAsen Dimov * 12b5d289fcSAsen Dimov * Configuation settings for the PM9G45 board. 13b5d289fcSAsen Dimov */ 14b5d289fcSAsen Dimov 15b5d289fcSAsen Dimov #ifndef __CONFIG_H 16b5d289fcSAsen Dimov #define __CONFIG_H 17b5d289fcSAsen Dimov 18eb6e608bSAsen Dimov /* 19eb6e608bSAsen Dimov * SoC must be defined first, before hardware.h is included. 20eb6e608bSAsen Dimov * In this case SoC is defined in boards.cfg. 21eb6e608bSAsen Dimov */ 22eb6e608bSAsen Dimov #include <asm/hardware.h> 23eb6e608bSAsen Dimov 24eb6e608bSAsen Dimov #define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45" 25b5d289fcSAsen Dimov 26a3e09cc2SAsen Dimov #define CONFIG_MACH_TYPE MACH_TYPE_PM9G45 27a3e09cc2SAsen Dimov 28b5d289fcSAsen Dimov /* ARM asynchronous clock */ 29b5d289fcSAsen Dimov #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 30eb6e608bSAsen Dimov #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ 31b5d289fcSAsen Dimov 32b5d289fcSAsen Dimov #define CONFIG_ARCH_CPU_INIT 33b5d289fcSAsen Dimov 34b5d289fcSAsen Dimov #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 35b5d289fcSAsen Dimov #define CONFIG_SETUP_MEMORY_TAGS 1 36b5d289fcSAsen Dimov #define CONFIG_INITRD_TAG 1 37b5d289fcSAsen Dimov 38b5d289fcSAsen Dimov #define CONFIG_SKIP_LOWLEVEL_INIT 39b5d289fcSAsen Dimov 40b5d289fcSAsen Dimov /* 41b5d289fcSAsen Dimov * Hardware drivers 42b5d289fcSAsen Dimov */ 43b5d289fcSAsen Dimov #define CONFIG_AT91_GPIO 1 44b5d289fcSAsen Dimov #define CONFIG_ATMEL_USART 1 45eb6e608bSAsen Dimov #define CONFIG_USART_BASE ATMEL_BASE_DBGU 46eb6e608bSAsen Dimov #define CONFIG_USART_ID ATMEL_ID_SYS 47b5d289fcSAsen Dimov 48b5d289fcSAsen Dimov #define CONFIG_SYS_USE_NANDFLASH 1 49b5d289fcSAsen Dimov 50b5d289fcSAsen Dimov /* LED */ 51b5d289fcSAsen Dimov #define CONFIG_AT91_LED 52bcf9fe37SAndreas Bießmann #define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */ 53bcf9fe37SAndreas Bießmann #define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */ 54b5d289fcSAsen Dimov 55b5d289fcSAsen Dimov 56b5d289fcSAsen Dimov /* 57b5d289fcSAsen Dimov * BOOTP options 58b5d289fcSAsen Dimov */ 59b5d289fcSAsen Dimov #define CONFIG_BOOTP_BOOTFILESIZE 1 60b5d289fcSAsen Dimov 61b5d289fcSAsen Dimov #define CONFIG_JFFS2_CMDLINE 1 62b5d289fcSAsen Dimov #define CONFIG_JFFS2_NAND 1 63b5d289fcSAsen Dimov #define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */ 64b5d289fcSAsen Dimov #define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ 65b5d289fcSAsen Dimov #define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */ 66b5d289fcSAsen Dimov 67b5d289fcSAsen Dimov /* SDRAM */ 68b5d289fcSAsen Dimov #define PHYS_SDRAM 0x70000000 69b5d289fcSAsen Dimov #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ 70b5d289fcSAsen Dimov 71b5d289fcSAsen Dimov /* NAND flash */ 72b5d289fcSAsen Dimov #ifdef CONFIG_CMD_NAND 73b5d289fcSAsen Dimov #define CONFIG_SYS_MAX_NAND_DEVICE 1 74b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_BASE 0x40000000 75b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_DBW_8 1 76b5d289fcSAsen Dimov /* our ALE is AD21 */ 77b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 78b5d289fcSAsen Dimov /* our CLE is AD22 */ 79b5d289fcSAsen Dimov #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 80ac45bb16SAndreas Bießmann #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) 81ac45bb16SAndreas Bießmann #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3) 82b5d289fcSAsen Dimov 83b5d289fcSAsen Dimov #endif 84b5d289fcSAsen Dimov 85b5d289fcSAsen Dimov /* Ethernet */ 86b5d289fcSAsen Dimov #define CONFIG_MACB 1 87b5d289fcSAsen Dimov #define CONFIG_RMII 1 88b5d289fcSAsen Dimov #define CONFIG_NET_RETRY_COUNT 20 89b5d289fcSAsen Dimov #define CONFIG_RESET_PHY_R 1 90b5d289fcSAsen Dimov 91b5d289fcSAsen Dimov /* USB */ 92b5d289fcSAsen Dimov #define CONFIG_USB_ATMEL 93dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL 94b5d289fcSAsen Dimov #define CONFIG_USB_OHCI_NEW 1 95b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 96b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ 97b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" 98b5d289fcSAsen Dimov #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 99b5d289fcSAsen Dimov 100b5d289fcSAsen Dimov /* board specific(not enough SRAM) */ 101b5d289fcSAsen Dimov #define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000 102b5d289fcSAsen Dimov 103b5d289fcSAsen Dimov #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */ 104b5d289fcSAsen Dimov 105b5d289fcSAsen Dimov #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 106b5d289fcSAsen Dimov #define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE 107b5d289fcSAsen Dimov 108b5d289fcSAsen Dimov /* bootstrap + u-boot + env + linux in nandflash */ 109b5d289fcSAsen Dimov #define CONFIG_ENV_OFFSET 0x60000 110b5d289fcSAsen Dimov #define CONFIG_ENV_OFFSET_REDUND 0x80000 111b5d289fcSAsen Dimov #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 112b5d289fcSAsen Dimov #define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm" 113b5d289fcSAsen Dimov 114b5d289fcSAsen Dimov /* 115b5d289fcSAsen Dimov * Size of malloc() pool 116b5d289fcSAsen Dimov */ 117b5d289fcSAsen Dimov #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\ 118b5d289fcSAsen Dimov 0x1000) 119b5d289fcSAsen Dimov 120510f794cSAsen Dimov #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 121510f794cSAsen Dimov #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 122510f794cSAsen Dimov GENERATED_GBL_DATA_SIZE) 123510f794cSAsen Dimov 124b5d289fcSAsen Dimov #endif 125