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/openbmc/linux/drivers/mtd/maps/
H A Dsbc_gxx.c15 16 KiB memory window at 0xdc000-0xdffff
19 0x258
20 bit 0-7: address bit 14-21
21 0x259
22 bit 0-1: address bit 22-23
23 bit 7: 0 - reset/powered down
48 #define WINDOW_START 0xdc000
56 #define PAGE_IO 0x258
59 /* bit 7 of 0x259 must be 1 to enable device. */
60 #define DEVICE_ENABLE 0x8000
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dsdhci-pxa.yaml73 pinctrl-0:
99 reg = <0xd4280800 0x800>;
111 reg = <0xd8000 0x1000>,
112 <0xdc000 0x100>,
113 <0x18454 0x4>;
114 interrupts = <0 25 0x4>;
117 mrvl,clk-delay-cycles = <0x1F>;
/openbmc/qemu/include/hw/pci-host/
H A Dpam.h35 * 0xa0000 - 0xbffff compatible SMRAM
37 * 0xc0000 - 0xc3fff Expansion area memory segments
38 * 0xc4000 - 0xc7fff
39 * 0xc8000 - 0xcbfff
40 * 0xcc000 - 0xcffff
41 * 0xd0000 - 0xd3fff
42 * 0xd4000 - 0xd7fff
43 * 0xd8000 - 0xdbfff
44 * 0xdc000 - 0xdffff
45 * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
[all …]
/openbmc/linux/Documentation/networking/
H A Dgeneric-hdlc.rst140 insmod n2 hw=0x300,10,0xD0000,01
148 insmod c101 hw=9,0xdc000
/openbmc/u-boot/arch/x86/include/asm/arch-quark/acpi/
H A Dsouthcluster.asl11 Name(_ADR, 0)
12 Name(_BBN, 0)
18 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
20 /* IO Region 0 */
22 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
25 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
29 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
31 /* VGA memory (0xa0000-0xbffff) */
34 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
35 0x00020000, , , ASEG)
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/acpi/
H A Dsouthcluster.asl14 Name(_ADR, 0)
15 Name(_BBN, 0)
21 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00)
23 /* IO Region 0 */
25 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00)
28 IO(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
32 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01)
34 /* VGA memory (0xa0000-0xbffff) */
37 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
38 0x00020000, , , ASEG)
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c35 .para1 = 0, /* not used (only used when tpr13 bit 31 is set */
36 .para2 = 0, /* not used (only used when tpr13 bit 31 is set */
40 .mr3 = 0,
42 .tpr0 = 0x2ab83def,
43 .tpr1 = 0x18082356,
44 .tpr2 = 0x00034156,
45 .tpr3 = 0x448c5533,
46 .tpr4 = 0x08010d00,
47 .tpr5 = 0x0340b20f,
48 .tpr6 = 0x20d118cc,
[all …]
/openbmc/qemu/tests/qtest/
H A Di440fx-test.c52 dev = qpci_device_find(bus, QPCI_DEVFN(0, 0)); in test_i440fx_defaults()
56 g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086); in test_i440fx_defaults()
58 g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237); in test_i440fx_defaults()
61 g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006); in test_i440fx_defaults()
63 g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280); in test_i440fx_defaults()
66 g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00); in test_i440fx_defaults()
67 g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600); in test_i440fx_defaults()
69 g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00); in test_i440fx_defaults()
71 g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00); in test_i440fx_defaults()
73 g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00); in test_i440fx_defaults()
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dhal_bt_coexist.c86 u8 bt_rssi_state = 0; in rtl8723e_dm_bt_check_coex_rssi_state1()
213 long undecoratedsmoothed_pwdb = 0; in rtl8723e_dm_bt_check_coex_rssi_state()
214 u8 bt_rssi_state = 0; in rtl8723e_dm_bt_check_coex_rssi_state()
336 long undecoratedsmoothed_pwdb = 0; in rtl8723e_dm_bt_get_rx_ss()
356 u8 h2c_parameter[3] = {0}; in rtl8723e_dm_bt_balance()
361 h2c_parameter[0] = ms0; in rtl8723e_dm_bt_balance()
364 h2c_parameter[2] = 0; in rtl8723e_dm_bt_balance()
365 h2c_parameter[1] = 0; in rtl8723e_dm_bt_balance()
366 h2c_parameter[0] = 0; in rtl8723e_dm_bt_balance()
371 "[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", in rtl8723e_dm_bt_balance()
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-39x.dtsi32 #size-cells = <0>;
35 cpu@0 {
38 reg = <0>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
75 reg = <0x8000 0x1000>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
[all …]
H A Darmada-38x.dtsi42 pcie-mem-aperture = <0xe0000000 0x8000000>;
43 pcie-io-aperture = <0xe8000000 0x100000>;
47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
66 clocks = <&coreclk 0>;
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-38x.dtsi41 pcie-mem-aperture = <0xe0000000 0x8000000>;
42 pcie-io-aperture = <0xe8000000 0x100000>;
46 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
51 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
52 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
55 clocks = <&coreclk 0>;
61 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
62 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
65 clocks = <&coreclk 0>;
71 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Ddiskonchip.c37 #define CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS 0
43 0xfffc8000, 0xfffca000, 0xfffcc000, 0xfffce000,
44 0xfffd0000, 0xfffd2000, 0xfffd4000, 0xfffd6000,
45 0xfffd800
[all...]
/openbmc/linux/drivers/scsi/qla2xxx/
H A Dqla_fw.h14 #define MBS_CHECKSUM_ERROR 0x4010
15 #define MBS_INVALID_PRODUCT_KEY 0x4020
55 #define PDS_PLOGI_PENDING 0x03
56 #define PDS_PLOGI_COMPLETE 0x04
57 #define PDS_PRLI_PENDING 0x05
58 #define PDS_PRLI_COMPLETE 0x06
59 #define PDS_PORT_UNAVAILABLE 0x07
60 #define PDS_PRLO_PENDING 0x09
61 #define PDS_LOGO_PENDING 0x11
62 #define PDS_PRLI2_PENDING 0x12
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmcu.c39 #define FW_START_OVERRIDE BIT(0)
53 #define MT7615_PATCH_ADDRESS 0x80000
54 #define MT7622_PATCH_ADDRESS 0x9c000
55 #define MT7663_PATCH_ADDRESS 0xdc000
75 seq = ++dev->mt76.mcu.msg_seq & 0xf; in mt7615_mcu_fill_msg()
77 seq = ++dev->mt76.mcu.msg_seq & 0xf; in mt7615_mcu_fill_msg()
95 txd[0] = cpu_to_le32(val); in mt7615_mcu_fill_msg()
139 int ret = 0; in mt7615_mcu_parse_response()
196 return mt76_tx_queue_skb_raw(dev, dev->mt76.q_mcu[qid], skb, 0); in mt7615_mcu_send_message()
252 mt76_poll(dev, MT_CONN_ON_MISC, MT_CFG_LPCR_HOST_FW_OWN, 0, 3000); in mt7615_mcu_drv_pmctrl()
[all …]
/openbmc/linux/drivers/scsi/
H A Daha152x.c281 (cmd) ? ((cmd)->device->id & 0x0f) : -1, \
282 (cmd) ? ((u8)(cmd)->device->lun & 0x07) : -1
293 #define IRQ_MIN 0
305 not_issued = 0x0001, /* command not yet issued */
306 selecting = 0x0002, /* target is being selected */
307 identified = 0x0004, /* IDENTIFY was sent */
308 disconnected = 0x0008, /* target disconnected */
309 completed = 0x0010, /* target sent COMMAND COMPLETE */
310 aborted = 0x0020, /* ABORT was sent */
311 resetted = 0x0040, /* BUS DEVICE RESET was sent */
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]