52     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));  in test_i440fx_defaults()
56     g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);  in test_i440fx_defaults()
58     g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);  in test_i440fx_defaults()
61     g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);  in test_i440fx_defaults()
63     g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);  in test_i440fx_defaults()
66     g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);  in test_i440fx_defaults()
67     g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);  in test_i440fx_defaults()
69     g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);  in test_i440fx_defaults()
71     g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);  in test_i440fx_defaults()
73     g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);  in test_i440fx_defaults()
76     value = qpci_config_readw(dev, 0x50); /* PMCCFG */  in test_i440fx_defaults()
86     g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */  in test_i440fx_defaults()
89     g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */  in test_i440fx_defaults()
92     g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */  in test_i440fx_defaults()
94     g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */  in test_i440fx_defaults()
97     g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */  in test_i440fx_defaults()
99     g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */  in test_i440fx_defaults()
102     g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */  in test_i440fx_defaults()
103     g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */  in test_i440fx_defaults()
104     g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */  in test_i440fx_defaults()
105     g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */  in test_i440fx_defaults()
106     g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */  in test_i440fx_defaults()
107     g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */  in test_i440fx_defaults()
108     g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */  in test_i440fx_defaults()
111     g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */  in test_i440fx_defaults()
112     g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */  in test_i440fx_defaults()
113     g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */  in test_i440fx_defaults()
114     g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */  in test_i440fx_defaults()
115     g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */  in test_i440fx_defaults()
116     g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */  in test_i440fx_defaults()
117     g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */  in test_i440fx_defaults()
118     g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */  in test_i440fx_defaults()
121     g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */  in test_i440fx_defaults()
123     g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */  in test_i440fx_defaults()
126     g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */  in test_i440fx_defaults()
129     g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */  in test_i440fx_defaults()
131     g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */  in test_i440fx_defaults()
133     g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */  in test_i440fx_defaults()
135     g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */  in test_i440fx_defaults()
147     int regno = 0x59 + (index / 2);  in pam_set()
152         reg = (reg & 0x0F) | (flags << 4);  in pam_set()
154         reg = (reg & 0xF0) | flags;  in pam_set()
169     g_test_message("verify_area: data[0] = 0x%x", data[0]);  in verify_area()
171     for (i = 0; i < size; i++) {  in verify_area()
205         { 0, 0 },             /* Reserved */  in test_i440fx_pam()
206         { 0xF0000, 0xFFFFF }, /* BIOS Area */  in test_i440fx_pam()
207         { 0xC0000, 0xC3FFF }, /* Option ROM */  in test_i440fx_pam()
208         { 0xC4000, 0xC7FFF }, /* Option ROM */  in test_i440fx_pam()
209         { 0xC8000, 0xCBFFF }, /* Option ROM */  in test_i440fx_pam()
210         { 0xCC000, 0xCFFFF }, /* Option ROM */  in test_i440fx_pam()
211         { 0xD0000, 0xD3FFF }, /* Option ROM */  in test_i440fx_pam()
212         { 0xD4000, 0xD7FFF }, /* Option ROM */  in test_i440fx_pam()
213         { 0xD8000, 0xDBFFF }, /* Option ROM */  in test_i440fx_pam()
214         { 0xDC000, 0xDFFFF }, /* Option ROM */  in test_i440fx_pam()
215         { 0xE0000, 0xE3FFF }, /* BIOS Extension */  in test_i440fx_pam()
216         { 0xE4000, 0xE7FFF }, /* BIOS Extension */  in test_i440fx_pam()
217         { 0xE8000, 0xEBFFF }, /* BIOS Extension */  in test_i440fx_pam()
218         { 0xEC000, 0xEFFFF }, /* BIOS Extension */  in test_i440fx_pam()
222     dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));  in test_i440fx_pam()
225     for (i = 0; i < ARRAY_SIZE(pam_area); i++) {  in test_i440fx_pam()
230         g_test_message("Checking area 0x%05x..0x%05x",  in test_i440fx_pam()
235         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));  in test_i440fx_pam()
240         write_area(pam_area[i].start, pam_area[i].end, 0x42);  in test_i440fx_pam()
248         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));  in test_i440fx_pam()
252         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));  in test_i440fx_pam()
255         write_area(pam_area[i].start, pam_area[i].end, 0x82);  in test_i440fx_pam()
261         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));  in test_i440fx_pam()
267         g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));  in test_i440fx_pam()
270         pam_set(dev, i, 0);  in test_i440fx_pam()
273         g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));  in test_i440fx_pam()
301     for (i = 0; i < BLOB_SIZE; i++) {  in create_blob_file()
341     memread(0x100000000ULL - BLOB_SIZE, buf, BLOB_SIZE);  in test_i440fx_firmware()
342     for (i = 0; i < BLOB_SIZE; ++i) {  in test_i440fx_firmware()
347     memset(buf, 0, BLOB_SIZE);  in test_i440fx_firmware()
349     memread(0x100000 - isa_bios_size, buf, isa_bios_size);  in test_i440fx_firmware()
350     for (i = 0; i < isa_bios_size; ++i) {  in test_i440fx_firmware()