Lines Matching +full:0 +full:xdc000
41 pcie-mem-aperture = <0xe0000000 0x8000000>;
42 pcie-io-aperture = <0xe8000000 0x100000>;
46 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
51 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
52 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
55 clocks = <&coreclk 0>;
61 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
62 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
65 clocks = <&coreclk 0>;
71 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
72 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
75 clocks = <&coreclk 0>;
81 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
82 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
85 clocks = <&coreclk 0>;
91 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
92 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
95 clocks = <&coreclk 0>;
104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
108 reg = <0x8000 0x1000>;
111 arm,double-linefill-incr = <0>;
112 arm,double-linefill-wrap = <0>;
113 arm,double-linefill = <0>;
119 reg = <0xc000 0x58>;
124 reg = <0xc200 0x20>;
131 reg = <0xc600 0x20>;
139 #size-cells = <0>;
141 reg = <0xd000 0x1000>,
142 <0xc100 0x100>;
147 reg = <0x11000 0x20>;
149 #size-cells = <0>;
152 clocks = <&coreclk 0>;
158 reg = <0x11100 0x20>;
160 #size-cells = <0>;
163 clocks = <&coreclk 0>;
169 reg = <0x12000 0x100>;
173 clocks = <&coreclk 0>;
179 reg = <0x12100 0x100>;
183 clocks = <&coreclk 0>;
188 reg = <0x18000 0x20>;
190 ge0_rgmii_pins: ge-rgmii-pins-0 {
206 i2c0_pins: i2c-pins-0 {
216 ref_clk0_pins: ref-clk-pins-0 {
226 spi0_pins: spi-pins-0 {
252 uart0_pins: uart-pins-0 {
270 sata0_pins: sata-pins-0 {
294 reg = <0x18100 0x40>, <0x181c0 0x08>;
306 clocks = <&coreclk 0>;
312 reg = <0x18140 0x40>, <0x181c8 0x08>;
324 clocks = <&coreclk 0>;
330 reg = <0x18200 0x100>;
335 reg = <0x18220 0x4>;
336 clocks = <&coreclk 0>;
342 reg = <0x18600 0x04>;
348 reg = <0x20000 0x100>, <0x20180 0x20>,
349 <0x20250 0x8>;
354 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
365 reg = <0x20300 0x30>, <0x21040 0x30>;
378 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
385 reg = <0x20800 0x10>;
390 reg = <0x20d20 0x6c>;
395 reg = <0x21010 0x1c>;
400 reg = <0x22000 0x1000>;
417 reg = <0x70000 0x4000>;
426 reg = <0x30000 0x4000>;
434 reg = <0x34000 0x4000>;
442 reg = <0x58000 0x500>;
450 reg = <0x60800 0x100
451 0x60a00 0x100>;
470 reg = <0x60900 0x100
471 0x60b00 0x100>;
490 #size-cells = <0>;
492 reg = <0x72004 0x4>;
498 reg = <0x90000 0x10000>;
508 marvell,crypto-sram-size = <0x800>;
513 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
520 reg = <0xa8000 0x2000>;
528 reg = <0xc8000 0xac>;
536 reg = <0xe0000 0x2000>;
544 reg = <0xe4250 0xc>;
552 reg = <0xe4078 0x4>, <0xe4070 0x8>;
558 reg = <0xd0000 0x54>;
560 #size-cells = <0>;
562 clocks = <&coredivclk 0>;
569 reg = <0xd8000 0x1000>,
570 <0xdc000 0x100>,
571 <0x18454 0x4>;
574 mrvl,clk-delay-cycles = <0x1F>;
580 reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
588 reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
597 reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
601 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
606 reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
610 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
615 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
616 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
627 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
629 #size-cells = <0>;
630 cell-index = <0>;
632 clocks = <&coreclk 0>;
639 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
641 #size-cells = <0>;
644 clocks = <&coreclk 0>;
653 #clock-cells = <0>;
660 #clock-cells = <0>;