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/openbmc/linux/drivers/media/dvb-frontends/
H A Daf9013_priv.h39 { 28800000, 8000000, { 0x02, 0x8a, 0x28, 0xa3, 0x05, 0x14,
40 0x51, 0x11, 0x00, 0xa2, 0x8f, 0x3d, 0x00, 0xa2, 0x8a,
41 0x29, 0x00, 0xa2, 0x85, 0x14, 0x01, 0x45, 0x14, 0x14 } },
42 { 28800000, 7000000, { 0x02, 0x38, 0xe3, 0x8e, 0x04, 0x71,
43 0xc7, 0x07, 0x00, 0x8e, 0x3d, 0x55, 0x00, 0x8e, 0x38,
44 0xe4, 0x00, 0x8e, 0x34, 0x72, 0x01, 0x1c, 0x71, 0x32 } },
45 { 28800000, 6000000, { 0x01, 0xe7, 0x9e, 0x7a, 0x03, 0xcf,
46 0x3c, 0x3d, 0x00, 0x79, 0xeb, 0x6e, 0x00, 0x79, 0xe7,
47 0x9e, 0x00, 0x79, 0xe3, 0xcf, 0x00, 0xf3, 0xcf, 0x0f } },
49 { 20480000, 8000000, { 0x03, 0x92, 0x49, 0x26, 0x07, 0x24,
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Diomux.c14 * the offsets of pins in iomuxc0 are from 0xD000,
15 * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
17 static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
33 …debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X… in mx7ulp_iomux_setup_pad()
65 for (i = 0; i < count; i++) { in mx7ulp_iomux_setup_multiple_pads()
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmedia5200.dts28 PowerPC,5200@0 {
35 memory@0 {
36 reg = <0x00000000 0x08000000>; // 128MB RAM
72 phy0: ethernet-phy@0 {
73 reg = <0>;
78 reg = <0x1000 0x100>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <0xc000 0 0 1 &media5200_fpga 0 2 // 1st slot
85 0xc000 0 0 2 &media5200_fpga 0 3
86 0xc000 0 0 3 &media5200_fpga 0 4
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Darmada-37xx-wdt.txt15 reg = <0xd000 0x1000>;
20 reg = <0x8300 0x40>;
/openbmc/linux/arch/powerpc/include/asm/
H A Dio-workarounds.h30 #define SPIDER_PCI_REG_BASE 0xd000
31 #define SPIDER_PCI_REG_SIZE 0x1000
32 #define SPIDER_PCI_VCI_CNTL_STAT 0x0110
33 #define SPIDER_PCI_DUMMY_READ 0x0810
34 #define SPIDER_PCI_DUMMY_READ_BASE 0x0814
/openbmc/linux/drivers/net/ethernet/netronome/nfp/nfpcore/
H A Dnfp_dev.c13 .qc_idx_mask = GENMASK(8, 0),
14 .qc_addr_offset = 0x400000,
19 .pcie_cfg_expbar_offset = 0x0a00,
20 .pcie_expl_offset = 0xd000,
21 .qc_area_sz = 0x100000,
25 .qc_idx_mask = GENMASK(8, 0),
26 .qc_addr_offset = 0,
32 .qc_idx_mask = GENMASK(7, 0),
33 .qc_addr_offset = 0x80000,
38 .pcie_cfg_expbar_offset = 0x0400,
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Dmx7ulp-pins.h12 …_3V = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x0, 0x0000,…
13 … = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x1, 0x0000,…
14 …CS1 = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x3, 0xD104,…
15 …CTS_b = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x4, 0xD1F8,…
16 …CL = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x5, 0xD17C,…
17 …IN = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x6, 0xD1A8,…
18 …BCLK = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0x7, 0xD1B8,…
19 … = IOMUX_PAD(0xD000, 0xD000, IOMUX_CONFIG_MPORTS | 0xd, 0x0000,…
20 …_3V = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x0, 0x0000,…
21 … = IOMUX_PAD(0xD004, 0xD004, IOMUX_CONFIG_MPORTS | 0x1, 0x0000,…
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sm8250-camss.yaml113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,postmask.yaml77 reg = <0 0x1400d000 0 0x1000>;
78 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>;
81 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
/openbmc/linux/drivers/media/platform/mediatek/mdp/
H A Dmtk_mdp_ipi.h14 AP_MDP_INIT = 0xd000,
15 AP_MDP_DEINIT = 0xd001,
16 AP_MDP_PROCESS = 0xd002,
18 VPU_MDP_INIT_ACK = 0xe000,
19 VPU_MDP_DEINIT_ACK = 0xe001,
20 VPU_MDP_PROCESS_ACK = 0xe002
104 int32_t orientation; /* 0, 90, 180, 270 */
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dtegra.h10 #define NV_PA_ARM_PERIPHBASE 0x50040000
11 #define NV_PA_PG_UP_BASE 0x60000000
12 #define NV_PA_TMRUS_BASE 0x60005010
13 #define NV_PA_CLK_RST_BASE 0x60006000
14 #define NV_PA_FLOW_BASE 0x60007000
15 #define NV_PA_GPIO_BASE 0x6000D000
16 #define NV_PA_EVP_BASE 0x6000F000
17 #define NV_PA_APB_MISC_BASE 0x70000000
18 #define NV_PA_APB_MISC_GP_BASE (NV_PA_APB_MISC_BASE + 0x0800)
19 #define NV_PA_APB_UARTA_BASE (NV_PA_APB_MISC_BASE + 0x6000)
[all …]
/openbmc/linux/include/linux/mdio/
H A Dmdio-xgene.h15 #define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
16 #define BLOCK_DIAG_CSR_OFFSET 0xd000
17 #define XGENET_CONFIG_REG_ADDR 0x20
19 #define MAC_ADDR_REG_OFFSET 0x00
20 #define MAC_COMMAND_REG_OFFSET 0x04
21 #define MAC_WRITE_REG_OFFSET 0x08
22 #define MAC_READ_REG_OFFSET 0x0c
23 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
25 #define CLKEN_OFFSET 0x08
26 #define SRST_OFFSET 0x00
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dsyna.txt57 reg = <0xf7dd0000 0x10000>;
91 reg = <0xea0000 0x400>;
98 reg = <0xd000 0x100>;
/openbmc/linux/drivers/leds/rgb/
H A Dleds-qcom-lpg.c17 #define LPG_SUBTYPE_REG 0x05
18 #define LPG_SUBTYPE_LPG 0x2
19 #define LPG_SUBTYPE_PWM 0xb
20 #define LPG_SUBTYPE_HI_RES_PWM 0xc
21 #define LPG_SUBTYPE_LPG_LITE 0x11
22 #define LPG_PATTERN_CONFIG_REG 0x40
23 #define LPG_SIZE_CLK_REG 0x41
24 #define PWM_CLK_SELECT_MASK GENMASK(1, 0)
25 #define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)
27 #define LPG_PREDIV_CLK_REG 0x42
[all …]
/openbmc/linux/drivers/staging/media/meson/vdec/
H A Dhevc_regs.h9 #define HEVC_ASSIST_MMU_MAP_ADDR 0xc024
11 #define HEVC_ASSIST_MBOX1_CLR_REG 0xc1d4
12 #define HEVC_ASSIST_MBOX1_MASK 0xc1d8
14 #define HEVC_ASSIST_SCRATCH_0 0xc300
15 #define HEVC_ASSIST_SCRATCH_1 0xc304
16 #define HEVC_ASSIST_SCRATCH_2 0xc308
17 #define HEVC_ASSIST_SCRATCH_3 0xc30c
18 #define HEVC_ASSIST_SCRATCH_4 0xc310
19 #define HEVC_ASSIST_SCRATCH_5 0xc314
20 #define HEVC_ASSIST_SCRATCH_6 0xc318
[all …]
/openbmc/linux/arch/loongarch/include/asm/
H A Dcpu.h18 * 31 24 23 16 15 12 11 0
25 #define PRID_COMP_MASK 0xff0000
27 #define PRID_COMP_LOONGSON 0x140000
35 #define PRID_SERIES_MASK 0xf000
37 #define PRID_SERIES_LA132 0x8000 /* Loongson 32bit */
38 #define PRID_SERIES_LA264 0xa000 /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364 0xb000 /* Loongson 64bit, 3-issue */
40 #define PRID_SERIES_LA464 0xc000 /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664 0xd000 /* Loongson 64bit, 6-issue */
44 * Particular Product ID values for bits 11:0 of the PRID register.
[all …]
/openbmc/qemu/hw/m68k/
H A Dnext-cube.c35 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...) do { } while (0)
43 #define ENTRY 0x0100001e
44 #define RAM_SIZE 0x4000000
116 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
117 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
118 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
123 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
124 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
[all …]
/openbmc/qemu/target/tricore/
H A Dcsfr.h.inc9 A(0xfe00, PCXI, TRICORE_FEATURE_13)
10 A(0xfe08, PC, TRICORE_FEATURE_13)
11 A(0xfe14, SYSCON, TRICORE_FEATURE_13)
12 R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
13 R(0xfe1c, CORE_ID, TRICORE_FEATURE_161)
14 E(0xfe20, BIV, TRICORE_FEATURE_13)
15 E(0xfe24, BTV, TRICORE_FEATURE_13)
16 E(0xfe28, ISP, TRICORE_FEATURE_13)
17 A(0xfe2c, ICR, TRICORE_FEATURE_13)
18 A(0xfe38, FCX, TRICORE_FEATURE_13)
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dinterlaken-lac-portals.dtsi34 #address-cells = <0x1>;
35 #size-cells = <0x1>;
38 lportal0: lac-portal@0 {
39 compatible = "fsl,interlaken-lac-portal-v1.0";
40 reg = <0x0 0x1000>;
44 compatible = "fsl,interlaken-lac-portal-v1.0";
45 reg = <0x1000 0x1000>;
49 compatible = "fsl,interlaken-lac-portal-v1.0";
50 reg = <0x2000 0x1000>;
54 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
/openbmc/linux/drivers/media/platform/mediatek/vcodec/encoder/
H A Dvenc_ipi_msg.h12 #define AP_IPIMSG_VENC_BASE 0xC000
13 #define VPU_IPIMSG_VENC_BASE 0xD000
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm53573.dtsi26 #size-cells = <0>;
28 cpu@0 {
31 reg = <0x0>;
37 ranges = <0x00000000 0x18310000 0x00008000>;
44 #address-cells = <0>;
46 reg = <0x1000 0x1000>,
47 <0x2000 0x0100>;
65 #clock-cells = <0>;
73 reg = <0x18000000 0x1000>;
74 ranges = <0x00000000 0x18000000 0x00100000>;
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/asp2/
H A Dbcmasp_intf_defs.h6 ((((intf)->port) * 0x800) + 0xc000)
7 #define UMC_CMD 0x008
8 #define UMC_CMD_TX_EN BIT(0)
10 #define UMC_CMD_SPEED_SHIFT 0x2
11 #define UMC_CMD_SPEED_MASK 0x3
12 #define UMC_CMD_SPEED_10 0x0
13 #define UMC_CMD_SPEED_100 0x1
14 #define UMC_CMD_SPEED_1000 0x2
15 #define UMC_CMD_SPEED_2500 0x3
33 #define UMC_MAC0 0x0c
[all …]
/openbmc/linux/arch/mips/include/asm/xtalk/
H A Dxwidget.h18 #define WIDGET_ID 0x04
19 #define WIDGET_STATUS 0x0c
20 #define WIDGET_ERR_UPPER_ADDR 0x14
21 #define WIDGET_ERR_LOWER_ADDR 0x1c
22 #define WIDGET_CONTROL 0x24
23 #define WIDGET_REQ_TIMEOUT 0x2c
24 #define WIDGET_INTDEST_UPPER_ADDR 0x34
25 #define WIDGET_INTDEST_LOWER_ADDR 0x3c
26 #define WIDGET_ERR_CMD_WORD 0x44
27 #define WIDGET_LLP_CFG 0x4c
[all …]
/openbmc/linux/arch/mips/sgi-ip27/
H A Dip27-xtalk.c22 #define XBOW_WIDGET_PART_NUM 0x0
23 #define XXBOW_WIDGET_PART_NUM 0xd000 /* Xbow in Xbridge */
46 memset(&w1_res, 0, sizeof(w1_res)); in bridge_platform_create()
85 bd->intr_addr = BIT_ULL(47) + 0x01800000 + PI_INT_PEND_MOD; in bridge_platform_create()
143 pr_info("xtalk:n%d/%d unknown widget (0x%x)\n", in probe_one_port()
148 return 0; in probe_one_port()
199 return 0; in xbow_probe()
215 (RAW_NODE_SWIN_BASE(nasid, 0x0) + WIDGET_ID); in xtalk_probe_node()
220 bridge_platform_create(nasid, 0x8, 0xa); in xtalk_probe_node()
224 pr_info("xtalk:n%d/0 xbow widget\n", nasid); in xtalk_probe_node()
[all …]

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