Lines Matching +full:0 +full:xd000
35 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...) do { } while (0)
43 #define ENTRY 0x0100001e
44 #define RAM_SIZE 0x4000000
116 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
117 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
118 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
123 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
124 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
125 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
126 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e,
129 #define SCR2_RTCLK 0x2
130 #define SCR2_RTDATA 0x4
135 if (s->scr2 & 0x1) { in next_scr2_led_update()
140 s->led = 0; in next_scr2_led_update()
153 if (scr2_2 & 0x1) { in next_scr2_rtc_update()
156 rtc->phase = 0; in next_scr2_rtc_update()
160 ((scr2_2 & SCR2_RTCLK) == 0)) { in next_scr2_rtc_update()
163 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); in next_scr2_rtc_update()
167 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); in next_scr2_rtc_update()
170 if (rtc->command <= 0x1F) { in next_scr2_rtc_update()
172 if (rtc->ram[rtc->command] & (0x80 >> (rtc->phase - 8))) { in next_scr2_rtc_update()
177 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); in next_scr2_rtc_update()
179 /* read the status 0x30 */ in next_scr2_rtc_update()
180 if (rtc->command == 0x30) { in next_scr2_rtc_update()
182 /* for now status = 0x98 (new rtc + FTU) */ in next_scr2_rtc_update()
183 if (rtc->status & (0x80 >> (rtc->phase - 8))) { in next_scr2_rtc_update()
188 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); in next_scr2_rtc_update()
190 /* read the status 0x31 */ in next_scr2_rtc_update()
191 if (rtc->command == 0x31) { in next_scr2_rtc_update()
193 if (rtc->control & (0x80 >> (rtc->phase - 8))) { in next_scr2_rtc_update()
197 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); in next_scr2_rtc_update()
200 if ((rtc->command >= 0x20) && (rtc->command <= 0x2F)) { in next_scr2_rtc_update()
202 /* for now 0x00 */ in next_scr2_rtc_update()
205 int ret = 0; in next_scr2_rtc_update()
208 case 0x20: in next_scr2_rtc_update()
211 case 0x21: in next_scr2_rtc_update()
214 case 0x22: in next_scr2_rtc_update()
217 case 0x24: in next_scr2_rtc_update()
220 case 0x25: in next_scr2_rtc_update()
223 case 0x26: in next_scr2_rtc_update()
229 if (ret & (0x80 >> (rtc->phase - 8))) { in next_scr2_rtc_update()
233 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); in next_scr2_rtc_update()
240 if (rtc->command >= 0x80 && rtc->command <= 0x9F) { in next_scr2_rtc_update()
241 rtc->ram[rtc->command - 0x80] = rtc->value; in next_scr2_rtc_update()
244 if (rtc->command == 0xB1) { in next_scr2_rtc_update()
246 if (rtc->value & 0x04) { in next_scr2_rtc_update()
247 rtc->status = rtc->status & (~0x18); in next_scr2_rtc_update()
248 s->int_status = s->int_status & (~0x04); in next_scr2_rtc_update()
256 rtc->command = 0; in next_scr2_rtc_update()
257 rtc->value = 0; in next_scr2_rtc_update()
269 case 0x7000: in next_mmio_read()
274 case 0x7800: in next_mmio_read()
279 case 0xc000 ... 0xc003: in next_mmio_read()
280 val = extract32(s->scr1, (4 - (addr - 0xc000) - size) << 3, in next_mmio_read()
284 case 0xd000 ... 0xd003: in next_mmio_read()
285 val = extract32(s->scr2, (4 - (addr - 0xd000) - size) << 3, in next_mmio_read()
289 case 0x14020: in next_mmio_read()
290 val = 0x7f; in next_mmio_read()
294 val = 0; in next_mmio_read()
295 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); in next_mmio_read()
308 case 0x7000: in next_mmio_write()
314 case 0x7800: in next_mmio_write()
319 case 0xc000 ... 0xc003: in next_mmio_write()
321 s->scr1 = deposit32(s->scr1, (4 - (addr - 0xc000) - size) << 3, in next_mmio_write()
325 case 0xd000 ... 0xd003: in next_mmio_write()
326 s->scr2 = deposit32(s->scr2, (4 - (addr - 0xd000) - size) << 3, in next_mmio_write()
334 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, in next_mmio_write()
347 #define SCSICSR_ENABLE 0x01
348 #define SCSICSR_RESET 0x02 /* reset scsi dma */
349 #define SCSICSR_FIFOFL 0x04
350 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */
351 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */
352 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */
360 case 0x14108: in next_scr_readfn()
362 val = 0x40 | 0x04 | 0x2 | 0x1; in next_scr_readfn()
365 case 0x14020: in next_scr_readfn()
370 case 0x14021: in next_scr_readfn()
372 val = 0x40; in next_scr_readfn()
381 case 0x1a000 ... 0x1a003: in next_scr_readfn()
382 val = extract32(clock(), (4 - (addr - 0x1a000) - size) << 3, in next_scr_readfn()
387 case 0x6000: in next_scr_readfn()
388 val = 0xff; in next_scr_readfn()
392 DPRINTF("BMAP Read @ 0x%x size %u\n", (unsigned int)addr, size); in next_scr_readfn()
393 val = 0; in next_scr_readfn()
406 case 0x14108: in next_scr_writefn()
408 if (val == 0x0) { in next_scr_writefn()
409 /* qemu_irq_raise(s->fd_irq[0]); */ in next_scr_writefn()
413 case 0x14020: /* SCSI Control Register */ in next_scr_writefn()
424 * s->scsi_csr_1 = 0xc0; in next_scr_writefn()
425 * s->scsi_csr_1 |= 0x1; in next_scr_writefn()
436 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ in next_scr_writefn()
438 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); in next_scr_writefn()
447 s->int_status |= 0x4000000; in next_scr_writefn()
450 s->int_status &= ~(0x4000000); in next_scr_writefn()
456 * int_mask &= ~0x1000; in next_scr_writefn()
460 * s->scsi_queued = 0; in next_scr_writefn()
465 /* int_mask |= 0x1000; */ in next_scr_writefn()
467 if (val & 0x80) { in next_scr_writefn()
468 /* int_mask |= 0x1000; */ in next_scr_writefn()
469 /* s->scsi_csr_1 |= 0x80; */ in next_scr_writefn()
476 case 0x1a000: in next_scr_writefn()
478 DPRINTF("BMAP Write @ 0x%x with 0x%"PRIx64 " size %u\n", in next_scr_writefn()
491 #define NEXTDMA_SCSI(x) (0x10 + x)
492 #define NEXTDMA_FD(x) (0x10 + x)
493 #define NEXTDMA_ENTX(x) (0x110 + x)
494 #define NEXTDMA_ENRX(x) (0x150 + x)
495 #define NEXTDMA_CSR 0x0
496 #define NEXTDMA_NEXT 0x4000
497 #define NEXTDMA_LIMIT 0x4004
498 #define NEXTDMA_START 0x4008
499 #define NEXTDMA_STOP 0x400c
500 #define NEXTDMA_NEXT_INIT 0x4200
501 #define NEXTDMA_SIZE 0x4204
641 val = 0; in next_dma_read()
645 * once the csr's are done, subtract 0x3FEC from the addr, and that will in next_dma_read()
665 int shift = 0; in next_irq()
764 int irq = 0; in nextdma_write()
772 if ((size % align) != 0) { in nextdma_write()
779 * so we check to see if initbuf is 0 in nextdma_write()
781 if (next_state->dma[type].next_initbuf == 0) { in nextdma_write()
789 next_state->dma[type].next_initbuf = 0; in nextdma_write()
799 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ in nextdma_write()
816 next_irq(opaque, irq, 0); in nextdma_write()
845 sysbus_esp->it_shift = 0; in next_scsi_init()
849 sysbus_connect_irq(sysbusdev, 0, qdev_get_gpio_in(pcdev, NEXT_SCSI_I)); in next_scsi_init()
850 sysbus_mmio_map(sysbusdev, 0, 0x2114000); in next_scsi_init()
852 next_pc->scsi_reset = qdev_get_gpio_in(dev, 0); in next_scsi_init()
864 qdev_prop_set_uint32(dev, "disabled", 0); in next_escc_init()
866 qdev_prop_set_uint32(dev, "it_shift", 0); in next_escc_init()
869 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); in next_escc_init()
875 sysbus_connect_irq(s, 0, qdev_get_gpio_in(pcdev, NEXT_SCC_I)); in next_escc_init()
877 sysbus_mmio_map(s, 0, 0x2118000); in next_escc_init()
885 /* 0x0000XX00 << vital bits */ in next_pc_reset()
886 s->scr1 = 0x00011102; in next_pc_reset()
887 s->scr2 = 0x00ff0c80; in next_pc_reset()
890 s->rtc.status = 0x90; in next_pc_reset()
904 "next.mmio", 0xd0000); in next_pc_realize()
906 "next.scr", 0x20000); in next_pc_realize()
951 VMSTATE_STRUCT(rtc, NeXTPC, 0, next_rtc_vmstate, NextRtc),
992 env->vbr = 0; in next_cube_init()
993 env->sr = 0x2700; in next_cube_init()
1000 /* 64MB RAM starting at 0x04000000 */ in next_cube_init()
1001 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); in next_cube_init()
1004 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); in next_cube_init()
1007 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02000000); in next_cube_init()
1010 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); in next_cube_init()
1015 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); in next_cube_init()
1016 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ in next_cube_init()
1018 0x0, 64); in next_cube_init()
1019 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); in next_cube_init()
1022 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); in next_cube_init()
1025 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); in next_cube_init()
1026 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); in next_cube_init()
1027 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, in next_cube_init()
1028 0x20000); in next_cube_init()
1029 memory_region_add_subregion(sysmem, 0x0, &m->rom2); in next_cube_init()
1030 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { in next_cube_init()
1037 ptr = rom_ptr(0x01000004, 4); in next_cube_init()
1040 if (env->pc >= 0x01020000) { in next_cube_init()
1057 "next.dma", 0x5000); in next_cube_init()
1058 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); in next_cube_init()