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12

/openbmc/linux/drivers/media/rc/keymaps/
H A Drc-xbox-dvd.c10 {0xa0b, KEY_OK},
11 {0xaa6, KEY_UP},
12 {0xaa7, KEY_DOWN},
13 {0xaa8, KEY_RIGHT},
14 {0xaa9, KEY_LEFT},
15 {0xac3, KEY_INFO},
17 {0xac6, KEY_NUMERIC_9},
18 {0xac7, KEY_NUMERIC_8},
19 {0xac8, KEY_NUMERIC_7},
20 {0xac9, KEY_NUMERIC_6},
[all …]
/openbmc/linux/Documentation/translations/zh_CN/admin-guide/
H A Dbug-hunting.rst15 WARNING: CPU: 1 PID: 28102 at kernel/module.c:1108 module_put+0x57/0x70
23 [<c12ba080>] ? dump_stack+0x44/0x64
24 [<c103ed6a>] ? __warn+0xfa/0x120
25 [<c109e8a7>] ? module_put+0x57/0x70
26 [<c109e8a7>] ? module_put+0x57/0x70
27 [<c103ee33>] ? warn_slowpath_null+0x23/0x30
28 [<c109e8a7>] ? module_put+0x57/0x70
29 [<f80ca4d0>] ? gp8psk_fe_set_frontend+0x460/0x460 [dvb_usb_gp8psk]
30 [<c109f617>] ? symbol_put_addr+0x27/0x50
31 [<f80bc9ca>] ? dvb_usb_adapter_frontend_exit+0x3a/0x70 [dvb_usb]
[all …]
/openbmc/linux/Documentation/translations/zh_TW/admin-guide/
H A Dbug-hunting.rst18 WARNING: CPU: 1 PID: 28102 at kernel/module.c:1108 module_put+0x57/0x70
26 [<c12ba080>] ? dump_stack+0x44/0x64
27 [<c103ed6a>] ? __warn+0xfa/0x120
28 [<c109e8a7>] ? module_put+0x57/0x70
29 [<c109e8a7>] ? module_put+0x57/0x70
30 [<c103ee33>] ? warn_slowpath_null+0x23/0x30
31 [<c109e8a7>] ? module_put+0x57/0x70
32 [<f80ca4d0>] ? gp8psk_fe_set_frontend+0x460/0x460 [dvb_usb_gp8psk]
33 [<c109f617>] ? symbol_put_addr+0x27/0x50
34 [<f80bc9ca>] ? dvb_usb_adapter_frontend_exit+0x3a/0x70 [dvb_usb]
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,cpm1-tsa.yaml39 const: 0
42 '^tdm@[0-1]$':
51 minimum: 0
54 The TDM number for this TDM, 0 for TDMa and 1 for TDMb
81 enum: [0, 1, 2, 3]
82 default: 0
86 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
89 enum: [0, 1, 2, 3]
90 default: 0
94 frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.
[all …]
/openbmc/linux/Documentation/admin-guide/
H A Dbug-hunting.rst7 WARNING: CPU: 1 PID: 28102 at kernel/module.c:1108 module_put+0x57/0x70
15 [<c12ba080>] ? dump_stack+0x44/0x64
16 [<c103ed6a>] ? __warn+0xfa/0x120
17 [<c109e8a7>] ? module_put+0x57/0x70
18 [<c109e8a7>] ? module_put+0x57/0x70
19 [<c103ee33>] ? warn_slowpath_null+0x23/0x30
20 [<c109e8a7>] ? module_put+0x57/0x70
21 [<f80ca4d0>] ? gp8psk_fe_set_frontend+0x460/0x460 [dvb_usb_gp8psk]
22 [<c109f617>] ? symbol_put_addr+0x27/0x50
23 [<f80bc9ca>] ? dvb_usb_adapter_frontend_exit+0x3a/0x70 [dvb_usb]
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4/
H A Dsetup-sh7750.c19 [0] = {
20 .start = 0xffc80000,
21 .end = 0xffc80000 + 0x58 - 1,
26 .start = evt2irq(0x480),
43 DEFINE_RES_MEM(0xffe00000, 0x20),
44 DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 .id = 0,
63 DEFINE_RES_MEM(0xffe80000, 0x100),
64 DEFINE_RES_IRQ(evt2irq(0x700)),
82 DEFINE_RES_MEM(0xffd80000, 0x30),
[all …]
/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h8 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
9 #define MTK_WDMA_DESC_CTRL_LEN1_V2 GENMASK(13, 0)
23 #define MTK_WED_REV_ID 0x004
25 #define MTK_WED_RESET 0x008
26 #define MTK_WED_RESET_TX_BM BIT(0)
42 #define MTK_WED_CTRL 0x00c
43 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
61 #define MTK_WED_EXT_INT_STATUS 0x020
62 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
89 #define MTK_WED_EXT_INT_MASK 0x028
[all …]
/openbmc/linux/arch/sh/kernel/cpu/sh4a/
H A Dsetup-shx3.c20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
H A Dsetup-sh7763.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
32 .id = 0,
47 DEFINE_RES_MEM(0xffe08000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0xb80)),
68 DEFINE_RES_MEM(0xffe10000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0xf00)),
83 [0] = {
84 .start = 0xffe80000,
85 .end = 0xffe80000 + 0x58 - 1,
[all …]
H A Dsetup-sh7780.c25 DEFINE_RES_MEM(0xffe00000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x700)),
31 .id = 0,
46 DEFINE_RES_MEM(0xffe10000, 0x100),
47 DEFINE_RES_IRQ(evt2irq(0xb80)),
65 DEFINE_RES_MEM(0xffd80000, 0x30),
66 DEFINE_RES_IRQ(evt2irq(0x580)),
67 DEFINE_RES_IRQ(evt2irq(0x5a0)),
68 DEFINE_RES_IRQ(evt2irq(0x5c0)),
73 .id = 0,
[all …]
H A Dsetup-sh7734.c32 DEFINE_RES_MEM(0xffe40000, 0x100),
33 DEFINE_RES_IRQ(evt2irq(0x8c0)),
38 .id = 0,
53 DEFINE_RES_MEM(0xffe41000, 0x100),
54 DEFINE_RES_IRQ(evt2irq(0x8e0)),
74 DEFINE_RES_MEM(0xffe42000, 0x100),
75 DEFINE_RES_IRQ(evt2irq(0x900)),
95 DEFINE_RES_MEM(0xffe43000, 0x100),
96 DEFINE_RES_IRQ(evt2irq(0x920)),
116 DEFINE_RES_MEM(0xffe44000, 0x100),
[all …]
H A Dsetup-sh7785.c27 DEFINE_RES_MEM(0xffea0000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0x700)),
33 .id = 0,
48 DEFINE_RES_MEM(0xffeb0000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0x780)),
69 DEFINE_RES_MEM(0xffec0000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0x980)),
90 DEFINE_RES_MEM(0xffed0000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0x9a0)),
111 DEFINE_RES_MEM(0xffee0000, 0x100),
[all …]
H A Dsetup-sh7786.c35 DEFINE_RES_MEM(0xffea0000, 0x100),
36 DEFINE_RES_IRQ(evt2irq(0x700)),
37 DEFINE_RES_IRQ(evt2irq(0x720)),
38 DEFINE_RES_IRQ(evt2irq(0x760)),
39 DEFINE_RES_IRQ(evt2irq(0x740)),
44 .id = 0,
62 DEFINE_RES_MEM(0xffeb0000, 0x100),
63 DEFINE_RES_IRQ(evt2irq(0x780)),
67 DEFINE_RES_MEM(0xffeb0000, 0x100),
69 DEFINE_RES_IRQ(0),
[all …]
H A Dsetup-sh7757.c30 DEFINE_RES_MEM(0xfe4b0000, 0x100), /* SCIF2 */
31 DEFINE_RES_IRQ(evt2irq(0x700)),
36 .id = 0,
50 DEFINE_RES_MEM(0xfe4c0000, 0x100), /* SCIF3 */
51 DEFINE_RES_IRQ(evt2irq(0xb80)),
70 DEFINE_RES_MEM(0xfe4d0000, 0x100), /* SCIF4 */
71 DEFINE_RES_IRQ(evt2irq(0xf00)),
89 DEFINE_RES_MEM(0xfe430000, 0x20),
90 DEFINE_RES_IRQ(evt2irq(0x580)),
91 DEFINE_RES_IRQ(evt2irq(0x5a0)),
[all …]
/openbmc/linux/arch/sh/drivers/pci/
H A Dpcie-sh7786.c44 .name = "PCIe0 MEM 0",
45 .start = 0xfd000000,
46 .end = 0xfd000000 + SZ_8M - 1,
50 .start = 0xc0000000,
51 .end = 0xc0000000 + SZ_512M - 1,
55 .start = 0x10000000,
56 .end = 0x10000000 + SZ_64M - 1,
60 .start = 0xfe100000,
61 .end = 0xfe100000 + SZ_1M - 1,
68 .name = "PCIe1 MEM 0",
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath9k/
H A Deeprom.h38 #define AR5416_EEPROM_MAGIC 0x5aa5
40 #define AR5416_EEPROM_MAGIC 0xa55a
43 #define CTRY_DEBUG 0x1ff
44 #define CTRY_DEFAULT 0
46 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
47 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
48 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
49 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
50 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
52 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
[all …]
/openbmc/qemu/hw/sh4/
H A Dsh7750.c101 EVENPORTMASK(0); in portdir()
112 ODDPORTMASK(1) | ODDPORTMASK(0); in portpullup()
157 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n", in error_access()
163 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n", in ignore_access()
189 return 0; in sh7750_mem_readw()
204 return 0; in sh7750_mem_readw()
229 return 0; in sh7750_mem_readl()
248 case 0x1f000030: /* Processor version */ in sh7750_mem_readl()
251 case 0x1f000040: /* Cache version */ in sh7750_mem_readl()
254 case 0x1f000044: /* Processor revision */ in sh7750_mem_readl()
[all …]
/openbmc/linux/drivers/memory/tegra/
H A Dtegra210.c12 .id = 0x00,
16 .id = 0x01,
21 .reg = 0x228,
25 .reg = 0x2e8,
26 .shift = 0,
27 .mask = 0xff,
28 .def = 0x1e,
32 .id = 0x02,
37 .reg = 0x228,
41 .reg = 0x2f4,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
[all …]
H A Dgmc_8_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
[all …]
/openbmc/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip06.dtsi23 #size-cells = <0>;
87 reg = <0x10000>;
95 reg = <0x10001>;
103 reg = <0x10002>;
111 reg = <0x10003>;
119 reg = <0x10100>;
127 reg = <0x10101>;
135 reg = <0x10102>;
143 reg = <0x10103>;
151 reg = <0x10200>;
[all …]
H A Dhip07.dtsi23 #size-cells = <0>;
270 reg = <0x10000>;
273 numa-node-id = <0>;
279 reg = <0x10001>;
282 numa-node-id = <0>;
288 reg = <0x10002>;
291 numa-node-id = <0>;
297 reg = <0x10003>;
300 numa-node-id = <0>;
306 reg = <0x10100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam437x-gp-evm.dts57 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
58 brightness-levels = <0 51 53 56 62 75 101 152 255>;
68 pinctrl-0 = <&matrix_keypad_default>;
80 linux,keymap = <0x00000201 /* P1 */
81 0x00010202 /* P2 */
82 0x01000067 /* UP */
83 0x0101006a /* RIGHT */
84 0x02000069 /* LEFT */
85 0x0201006c>; /* DOWN */
103 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra210.c22 #define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
182 #define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
1266 #define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
1267 #define PINGROUP_REG_A 0x3000 /* bank 1 */
1290 .mux_bit = 0, \
1306 .drv_bank = 0, \
1335 .drv_bank = 0, \
1354 …PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, N,…
1355 …PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, N,…
1356 …PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, N,…
[all …]
/openbmc/linux/drivers/net/can/flexcan/
H A Dflexcan-core.c62 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
63 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
64 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
65 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
66 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
69 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
70 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
71 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
72 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
84 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
[all …]

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