cpu/sh4/setup-sh7750.c

19 	[0] = {
20 		.start	= 0xffc80000,
21 		.end	= 0xffc80000 + 0x58 - 1,
26 		.start	= evt2irq(0x480),
43 	DEFINE_RES_MEM(0xffe00000, 0x20),
44 	DEFINE_RES_IRQ(evt2irq(0x4e0)),
49 	.id		= 0,
63 	DEFINE_RES_MEM(0xffe80000, 0x100),
64 	DEFINE_RES_IRQ(evt2irq(0x700)),
82 	DEFINE_RES_MEM(0xffd80000, 0x30),
83 	DEFINE_RES_IRQ(evt2irq(0x400)),
84 	DEFINE_RES_IRQ(evt2irq(0x420)),
85 	DEFINE_RES_IRQ(evt2irq(0x440)),
90 	.id		= 0,
108 	DEFINE_RES_MEM(0xfe100000, 0x20),
109 	DEFINE_RES_IRQ(evt2irq(0xb00)),
110 	DEFINE_RES_IRQ(evt2irq(0xb80)),
164 		dev[0] = &scif_device;  in plat_early_device_setup()
167 		dev[0] = &sci_device;  in plat_early_device_setup()
169 		dev[0] = &scif_device;  in plat_early_device_setup()
178 	UNUSED = 0,
192 	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
193 	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
194 	INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
195 	INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
196 	INTC_VECT(RTC, 0x4c0),
197 	INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
198 	INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
199 	INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
200 	INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
201 	INTC_VECT(WDT, 0x560),
202 	INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
206 	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
207 	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
208 	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
209 	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
210 	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
224 	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
225 	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
226 	INTC_VECT(DMAC, 0x6c0),
237 	INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
238 	INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
239 	INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
240 	INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
241 	INTC_VECT(DMAC, 0x6c0),
254 	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
258 	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
259 	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
260 	    0, 0, 0, 0, 0, 0, TMU4, TMU3,
273 	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
274 	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
283 	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
284 	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
285 	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
286 	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
341 #define INTC_ICR	0xffd00000UL
352 	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */  in plat_irq_setup_pins()