Lines Matching +full:0 +full:xae0
101 EVENPORTMASK(0); in portdir()
112 ODDPORTMASK(1) | ODDPORTMASK(0); in portpullup()
157 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n", in error_access()
163 fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n", in ignore_access()
189 return 0; in sh7750_mem_readw()
204 return 0; in sh7750_mem_readw()
229 return 0; in sh7750_mem_readl()
248 case 0x1f000030: /* Processor version */ in sh7750_mem_readl()
251 case 0x1f000040: /* Cache version */ in sh7750_mem_readl()
254 case 0x1f000044: /* Processor revision */ in sh7750_mem_readl()
320 if (mem_value != 0) { in sh7750_mem_writew()
377 if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { in sh7750_mem_writel()
386 s->cpu->env.ptea = mem_value & 0x0000000f; in sh7750_mem_writel()
395 s->cpu->env.tra = mem_value & 0x000007ff; in sh7750_mem_writel()
398 s->cpu->env.expevt = mem_value & 0x000007ff; in sh7750_mem_writel()
401 s->cpu->env.intevt = mem_value & 0x000007ff; in sh7750_mem_writel()
458 UNUSED = 0,
486 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
487 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
488 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
489 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
490 INTC_VECT(RTC_CUI, 0x4c0),
491 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
492 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
493 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
494 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
495 INTC_VECT(WDT, 0x560),
496 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
508 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
509 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
510 { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
511 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
512 { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, TMU4, TMU3,
519 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
520 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
521 INTC_VECT(DMAC_DMAE, 0x6c0),
532 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
533 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
534 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
535 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
536 INTC_VECT(DMAC_DMAE, 0x6c0),
548 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
552 { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
553 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
554 0, 0, 0, 0, 0, 0, TMU4, TMU3,
563 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
564 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
570 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
571 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
572 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
573 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
582 INTC_VECT(IRL_0, 0x200),
583 INTC_VECT(IRL_1, 0x220),
584 INTC_VECT(IRL_2, 0x240),
585 INTC_VECT(IRL_3, 0x260),
586 INTC_VECT(IRL_4, 0x280),
587 INTC_VECT(IRL_5, 0x2a0),
588 INTC_VECT(IRL_6, 0x2c0),
589 INTC_VECT(IRL_7, 0x2e0),
590 INTC_VECT(IRL_8, 0x300),
591 INTC_VECT(IRL_9, 0x320),
592 INTC_VECT(IRL_A, 0x340),
593 INTC_VECT(IRL_B, 0x360),
594 INTC_VECT(IRL_C, 0x380),
595 INTC_VECT(IRL_D, 0x3a0),
596 INTC_VECT(IRL_E, 0x3c0),
608 #define MM_REGION_MASK 0x07000000
609 #define MM_ICACHE_ADDR (0)
623 return 0; in invalid_read()
630 uint32_t ret = 0; in sh7750_mmct_read()
724 "memory", 0x1fc01000); in sh7750_init()
727 &s->iomem, 0x1f000000, 0x1000); in sh7750_init()
728 memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0); in sh7750_init()
731 &s->iomem, 0x1f000000, 0x1000); in sh7750_init()
732 memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0); in sh7750_init()
735 &s->iomem, 0x1f800000, 0x1000); in sh7750_init()
736 memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8); in sh7750_init()
739 &s->iomem, 0x1f800000, 0x1000); in sh7750_init()
740 memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8); in sh7750_init()
743 &s->iomem, 0x1fc00000, 0x1000); in sh7750_init()
744 memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc); in sh7750_init()
747 &s->iomem, 0x1fc00000, 0x1000); in sh7750_init()
748 memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); in sh7750_init()
751 "cache-and-tlb", 0x08000000); in sh7750_init()
752 memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); in sh7750_init()
767 qdev_prop_set_chr(dev, "chardev", serial_hd(0)); in sh7750_init()
770 sysbus_mmio_map(sb, 0, 0xffe00000); in sh7750_init()
772 mr = sysbus_mmio_get_region(sb, 0); in sh7750_init()
774 0, memory_region_size(mr)); in sh7750_init()
775 memory_region_add_subregion(sysmem, A7ADDR(0xffe00000), alias); in sh7750_init()
776 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCI1_ERI]); in sh7750_init()
777 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCI1_RXI]); in sh7750_init()
778 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCI1_TXI]); in sh7750_init()
779 qdev_connect_gpio_out_named(dev, "tei", 0, s->intc.irqs[SCI1_TEI]); in sh7750_init()
788 sysbus_mmio_map(sb, 0, 0xffe80000); in sh7750_init()
790 mr = sysbus_mmio_get_region(sb, 0); in sh7750_init()
792 0, memory_region_size(mr)); in sh7750_init()
793 memory_region_add_subregion(sysmem, A7ADDR(0xffe80000), alias); in sh7750_init()
794 qdev_connect_gpio_out_named(dev, "eri", 0, s->intc.irqs[SCIF_ERI]); in sh7750_init()
795 qdev_connect_gpio_out_named(dev, "rxi", 0, s->intc.irqs[SCIF_RXI]); in sh7750_init()
796 qdev_connect_gpio_out_named(dev, "txi", 0, s->intc.irqs[SCIF_TXI]); in sh7750_init()
797 qdev_connect_gpio_out_named(dev, "bri", 0, s->intc.irqs[SCIF_BRI]); in sh7750_init()
799 tmu012_init(sysmem, 0x1fd80000, in sh7750_init()
822 NULL, 0); in sh7750_init()
823 tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, in sh7750_init()
838 NULL, 0); in sh7750_init()
849 sh_intc_toggle_source(&s->intc.sources[IRL], 1, 0); /* enable */ in sh7750_irl()
850 return qemu_allocate_irq(sh_intc_set_irl, &s->intc.sources[IRL], 0); in sh7750_irl()