Lines Matching +full:0 +full:xae0
62 #define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
63 #define FLEXCAN_MCR_IDAM_A (0x0 << 8)
64 #define FLEXCAN_MCR_IDAM_B (0x1 << 8)
65 #define FLEXCAN_MCR_IDAM_C (0x2 << 8)
66 #define FLEXCAN_MCR_IDAM_D (0x3 << 8)
69 #define FLEXCAN_CTRL_PRESDIV(x) (((x) & 0xff) << 24)
70 #define FLEXCAN_CTRL_RJW(x) (((x) & 0x03) << 22)
71 #define FLEXCAN_CTRL_PSEG1(x) (((x) & 0x07) << 19)
72 #define FLEXCAN_CTRL_PSEG2(x) (((x) & 0x07) << 16)
84 #define FLEXCAN_CTRL_PROPSEG(x) ((x) & 0x07)
95 #define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
96 #define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
128 #define FLEXCAN_ESR_FLT_CONF_MASK (0x3 << FLEXCAN_EST_FLT_CONF_SHIFT)
129 #define FLEXCAN_ESR_FLT_CONF_ACTIVE (0x0 << FLEXCAN_EST_FLT_CONF_SHIFT)
130 #define FLEXCAN_ESR_FLT_CONF_PASSIVE (0x1 << FLEXCAN_EST_FLT_CONF_SHIFT)
133 #define FLEXCAN_ESR_WAK_INT BIT(0)
152 #define FLEXCAN_CBT_EPSEG2_MASK GENMASK(4, 0)
158 #define FLEXCAN_FDCTRL_MBDSR_8 0x0
159 #define FLEXCAN_FDCTRL_MBDSR_12 0x1
160 #define FLEXCAN_FDCTRL_MBDSR_32 0x2
161 #define FLEXCAN_FDCTRL_MBDSR_64 0x3
165 #define FLEXCAN_FDCTRL_TDCVAL GENMASK(5, 0)
172 #define FLEXCAN_FDCBT_FPSEG2_MASK GENMASK(2, 0)
177 #define FLEXCAN_TX_MB_RESERVED_RX_MAILBOX 0
185 #define FLEXCAN_MB_CODE_MASK (0xf << 24)
186 #define FLEXCAN_MB_CODE_RX_BUSY_BIT (0x1 << 24)
187 #define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
188 #define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
189 #define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
190 #define FLEXCAN_MB_CODE_RX_OVERRUN (0x6 << 24)
191 #define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
193 #define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
194 #define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
195 #define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
196 #define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
204 #define FLEXCAN_MB_CNT_LENGTH(x) (((x) & 0xf) << 16)
205 #define FLEXCAN_MB_CNT_TIMESTAMP(x) ((x) & 0xffff)
218 u32 mcr; /* 0x00 */
219 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
220 u32 timer; /* 0x08 */
221 u32 tcr; /* 0x0c */
222 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
223 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
224 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
225 u32 ecr; /* 0x1c */
226 u32 esr; /* 0x20 */
227 u32 imask2; /* 0x24 */
228 u32 imask1; /* 0x28 */
229 u32 iflag2; /* 0x2c */
230 u32 iflag1; /* 0x30 */
231 union { /* 0x34 */
235 u32 esr2; /* 0x38 */
236 u32 imeur; /* 0x3c */
237 u32 lrfr; /* 0x40 */
238 u32 crcr; /* 0x44 */
239 u32 rxfgmask; /* 0x48 */
240 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
241 u32 cbt; /* 0x50 - Not affected by Soft Reset */
242 u32 _reserved2; /* 0x54 */
243 u32 dbg1; /* 0x58 */
244 u32 dbg2; /* 0x5c */
245 u32 _reserved3[8]; /* 0x60 */
247 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
250 * 0x080...0x08f 0 RX message buffer
251 * 0x090...0x0df 1-5 reserved
252 * 0x0e0...0x0ff 6-7 8 entry ID table
254 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
258 u32 _reserved4[256]; /* 0x480 */
259 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
260 u32 _reserved5[24]; /* 0x980 */
261 u32 gfwr_mx6; /* 0x9e0 - MX6 */
262 u32 _reserved6[39]; /* 0x9e4 */
263 u32 _rxfir[6]; /* 0xa80 */
264 u32 _reserved8[2]; /* 0xa98 */
265 u32 _rxmgmask; /* 0xaa0 */
266 u32 _rxfgmask; /* 0xaa4 */
267 u32 _rx14mask; /* 0xaa8 */
268 u32 _rx15mask; /* 0xaac */
269 u32 tx_smb[4]; /* 0xab0 */
270 u32 rx_smb0[4]; /* 0xac0 */
271 u32 rx_smb1[4]; /* 0xad0 */
273 u32 mecr; /* 0xae0 */
274 u32 erriar; /* 0xae4 */
275 u32 erridpr; /* 0xae8 */
276 u32 errippr; /* 0xaec */
277 u32 rerrar; /* 0xaf0 */
278 u32 rerrdr; /* 0xaf4 */
279 u32 rerrsynr; /* 0xaf8 */
280 u32 errsr; /* 0xafc */
281 u32 _reserved7[64]; /* 0xb00 */
282 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
283 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
284 u32 fdcrc; /* 0xc08 */
285 u32 _reserved9[199]; /* 0xc0c */
287 u32 tx_smb_fd[18]; /* 0xf28 */
288 u32 rx_smb0_fd[18]; /* 0xf70 */
289 u32 rx_smb1_fd[18]; /* 0xfb8 */
293 static_assert(sizeof(struct flexcan_regs) == 0x4 * 18 + 0xfb8);
459 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size; in flexcan_get_mb()
480 return 0; in flexcan_low_power_enter_ack()
494 return 0; in flexcan_low_power_exit_ack()
522 val = 0; in flexcan_stop_mode_enable_scfw()
542 if (ret < 0) in flexcan_enter_stop_mode()
561 if (ret < 0) in flexcan_exit_stop_mode()
565 1 << priv->stm.req_bit, 0); in flexcan_exit_stop_mode()
593 int err = 0; in flexcan_clks_enable()
619 return 0; in flexcan_transceiver_enable()
627 return 0; in flexcan_transceiver_disable()
678 return 0; in flexcan_chip_freeze()
697 return 0; in flexcan_chip_unfreeze()
712 return 0; in flexcan_chip_softreset()
722 bec->txerr = (reg >> 0) & 0xff; in __flexcan_get_berr_counter()
723 bec->rxerr = (reg >> 8) & 0xff; in __flexcan_get_berr_counter()
725 return 0; in __flexcan_get_berr_counter()
735 if (err < 0) in flexcan_get_berr_counter()
776 for (i = 0; i < cfd->len; i += sizeof(u32)) { in flexcan_start_xmit()
781 can_put_echo_skb(skb, dev, 0, 0); in flexcan_start_xmit()
787 * Write twice INACTIVE(0x8) code to first MB. in flexcan_start_xmit()
882 rx_state = bec.rxerr >= bec.txerr ? new_state : 0; in flexcan_irq_state()
883 tx_state = bec.rxerr <= bec.txerr ? new_state : 0; in flexcan_irq_state()
908 u64 reg = 0; in flexcan_read64_mask()
1000 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; in flexcan_mailbox_read()
1005 cfd->len = can_fd_dlc2len((reg_ctrl >> 16) & 0xf); in flexcan_mailbox_read()
1010 cfd->len = can_cc_dlc2len((reg_ctrl >> 16) & 0xf); in flexcan_mailbox_read()
1019 for (i = 0; i < cfd->len; i += sizeof(u32)) { in flexcan_mailbox_read()
1089 can_rx_offload_get_echo_skb_queue_timestamp(&priv->offload, 0, in flexcan_irq()
1171 reg &= ~(FLEXCAN_CTRL_PRESDIV(0xff) | in flexcan_set_bittiming_ctrl()
1172 FLEXCAN_CTRL_RJW(0x3) | in flexcan_set_bittiming_ctrl()
1173 FLEXCAN_CTRL_PSEG1(0x7) | in flexcan_set_bittiming_ctrl()
1174 FLEXCAN_CTRL_PSEG2(0x7) | in flexcan_set_bittiming_ctrl()
1175 FLEXCAN_CTRL_PROPSEG(0x7)); in flexcan_set_bittiming_ctrl()
1183 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); in flexcan_set_bittiming_ctrl()
1187 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x\n", __func__, in flexcan_set_bittiming_ctrl()
1206 if (bt->phase_seg1 > 0x20) { in flexcan_set_bittiming_cbt()
1207 bt->prop_seg += (bt->phase_seg1 - 0x20); in flexcan_set_bittiming_cbt()
1208 bt->phase_seg1 = 0x20; in flexcan_set_bittiming_cbt()
1218 netdev_dbg(dev, "writing cbt=0x%08x\n", reg_cbt); in flexcan_set_bittiming_cbt()
1236 if (dbt->phase_seg1 > 0x8) { in flexcan_set_bittiming_cbt()
1237 dbt->prop_seg += (dbt->phase_seg1 - 0x8); in flexcan_set_bittiming_cbt()
1238 dbt->phase_seg1 = 0x8; in flexcan_set_bittiming_cbt()
1242 reg_fdcbt &= ~(FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, 0x3ff) | in flexcan_set_bittiming_cbt()
1243 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, 0x7) | in flexcan_set_bittiming_cbt()
1244 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, 0x1f) | in flexcan_set_bittiming_cbt()
1245 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, 0x7) | in flexcan_set_bittiming_cbt()
1246 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, 0x7)); in flexcan_set_bittiming_cbt()
1254 netdev_dbg(dev, "writing fdcbt=0x%08x\n", reg_fdcbt); in flexcan_set_bittiming_cbt()
1263 netdev_dbg(dev, "writing ctrl2=0x%08x\n", reg_ctrl2); in flexcan_set_bittiming_cbt()
1270 FIELD_PREP(FLEXCAN_FDCTRL_TDCOFF, 0x1f)); in flexcan_set_bittiming_cbt()
1287 netdev_dbg(dev, "writing fdctrl=0x%08x\n", reg_fdctrl); in flexcan_set_bittiming_cbt()
1290 netdev_dbg(dev, "%s: mcr=0x%08x ctrl=0x%08x ctrl2=0x%08x fdctrl=0x%08x cbt=0x%08x fdcbt=0x%08x\n", in flexcan_set_bittiming_cbt()
1314 netdev_dbg(dev, "writing ctrl=0x%08x\n", reg); in flexcan_set_bittiming()
1331 * that require initialization, ranging from 0x080 to 0xADF in flexcan_ram_init()
1332 * and from 0xF28 to 0xFFF when the CAN FD feature is enabled. in flexcan_ram_init()
1341 memset_io(®s->init, 0, sizeof(regs->init)); in flexcan_ram_init()
1344 memset_io(®s->init_fd, 0, sizeof(regs->init_fd)); in flexcan_ram_init()
1363 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) + in flexcan_rx_offload_setup()
1414 priv->write(0, ®s->imask2); in flexcan_chip_interrupts_disable()
1415 priv->write(0, ®s->imask1); in flexcan_chip_interrupts_disable()
1462 reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff); in flexcan_chip_start()
1500 netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr); in flexcan_chip_start()
1533 netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl); in flexcan_chip_start()
1546 reg_fdctrl &= ~(FIELD_PREP(FLEXCAN_FDCTRL_MBDSR1, 0x3) | in flexcan_chip_start()
1547 FIELD_PREP(FLEXCAN_FDCTRL_MBDSR0, 0x3)); in flexcan_chip_start()
1563 netdev_dbg(dev, "%s: writing fdctrl=0x%08x", in flexcan_chip_start()
1592 priv->write(0x0, ®s->rxgmask); in flexcan_chip_start()
1593 priv->write(0x0, ®s->rx14mask); in flexcan_chip_start()
1594 priv->write(0x0, ®s->rx15mask); in flexcan_chip_start()
1597 priv->write(0x0, ®s->rxfgmask); in flexcan_chip_start()
1600 for (i = 0; i < priv->mb_count; i++) in flexcan_chip_start()
1601 priv->write(0, ®s->rximr[i]); in flexcan_chip_start()
1615 * 1. By default, CTRL2[ECRWRE] = 0, MECR[ECRWRDIS] = 1 in flexcan_chip_start()
1650 netdev_dbg(dev, "%s: reading mcr=0x%08x ctrl=0x%08x\n", __func__, in flexcan_chip_start()
1653 return 0; in flexcan_chip_start()
1679 return 0; in __flexcan_chip_stop()
1709 if (err < 0) in flexcan_open()
1750 return 0; in flexcan_open()
1793 return 0; in flexcan_close()
1815 return 0; in flexcan_set_mode()
1883 return 0; in register_flexcandev()
1939 "gpr %s req_gpr=0x02%x req_bit=%u\n", in flexcan_setup_stop_mode_gpr()
1942 return 0; in flexcan_setup_stop_mode_gpr()
1957 if (ret < 0) { in flexcan_setup_stop_mode_scfw()
1971 * Return: = 0 setup stop mode successfully or doesn't support this feature
1972 * < 0 fail to setup stop mode (could be deferred probe)
1987 /* return 0 directly if doesn't support stop mode feature */ in flexcan_setup_stop_mode()
1988 return 0; in flexcan_setup_stop_mode()
1992 * directly return 0, this will skip the wakeup capable setting and in flexcan_setup_stop_mode()
1996 return 0; in flexcan_setup_stop_mode()
2005 return 0; in flexcan_setup_stop_mode()
2047 u32 clock_freq = 0; in flexcan_probe()
2085 irq = platform_get_irq(pdev, 0); in flexcan_probe()
2086 if (irq < 0) in flexcan_probe()
2089 regs = devm_platform_ioremap_resource(pdev, 0); in flexcan_probe()
2120 "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n", in flexcan_probe()
2164 if (priv->irq_boff < 0) { in flexcan_probe()
2169 if (priv->irq_err < 0) { in flexcan_probe()
2196 if (err < 0) { in flexcan_probe()
2203 return 0; in flexcan_probe()
2257 return 0; in flexcan_suspend()
2288 return 0; in flexcan_resume()
2298 return 0; in flexcan_runtime_suspend()
2325 return 0; in flexcan_noirq_suspend()
2344 return 0; in flexcan_noirq_resume()