Home
last modified time | relevance | path

Searched +full:0 +full:xa8000000 (Results 1 – 25 of 59) sorted by relevance

123

/openbmc/linux/arch/sh/include/mach-kfr2r09/mach/
H A Dpartner-jet-setup.txt8 LIST "> RD zImage, 0xa8800000"
9 LIST "> G=0xa8800000"
13 LIST "> RD romImage, 0"
18 EW 0xa4520004, 0xa507
21 ED 0xff00001c, 0x00000800
24 ED 0xff000010, 0x00000004
27 ED 0xff800020, 0xa5a50001
28 ED 0xfec10000, 0x0000001b
33 ED 0xa4150004, 0x00000050
34 ED 0xa4150000, 0x91053508
[all …]
H A Dromimage.h22 1: .long 0xa8000000
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc8377_wlan.dts28 #size-cells = <0>;
30 PowerPC,8377@0 {
32 reg = <0x0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
45 reg = <0x00000000 0x20000000>; // 512MB at 0
52 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>;
55 ranges = <0x0 0x0 0xfc000000 0x04000000>;
[all …]
H A Dmpc8377_rdb.dts27 #size-cells = <0>;
29 PowerPC,8377@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8378_rdb.dts27 #size-cells = <0>;
29 PowerPC,8378@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
44 reg = <0x00000000 0x10000000>; // 256MB at 0
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
58 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dspear-pwm.txt15 reg = <0xa8000000 0x1000>;
/openbmc/linux/tools/testing/selftests/powerpc/include/
H A Dinstructions.h10 (0x7c00060c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10))
16 asm volatile(str(COPY(0, %0, 0))";" in copy()
25 asm volatile(str(COPY(0, %0, 1))";" in copy_first()
34 (0x7c00070c | (RA) << (31-15) | (RB) << (31-20) | (L) << (31-10) | (RC) << (31-31))
42 asm volatile(str(PASTE(0, %1, 0, 0))";" in paste()
43 "mfcr %0;" in paste()
55 asm volatile(str(PASTE(0, %1, 1, 1))";" in paste_last()
56 "mfcr %0;" in paste_last()
64 #define PPC_INST_COPY __COPY(0, 0, 0)
65 #define PPC_INST_COPY_FIRST __COPY(0, 0, 1)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Ddavicom,dm9000.yaml54 reg = <0xa8000000 0x2>, <0xa8000002 0x2>;
/openbmc/linux/arch/sh/include/mach-ecovec24/mach/
H A Dromimage.h22 1 : .long 0xa8000000
36 #define HIZCRA 0xa4050158
37 #define PGDR 0xa405012c
/openbmc/u-boot/include/configs/
H A Dvexpress_common.h20 #define V2M_PA_CS0 0x40000000
21 #define V2M_PA_CS1 0x44000000
22 #define V2M_PA_CS2 0x48000000
23 #define V2M_PA_CS3 0x4c000000
24 #define V2M_PA_CS7 0x10000000
27 #define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
31 #define V2M_BASE 0x60000000
34 #define V2M_PA_CS0 0x08000000
35 #define V2M_PA_CS1 0x0c000000
36 #define V2M_PA_CS2 0x14000000
[all …]
H A DMPC837XERDB.h83 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
84 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
87 #define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
90 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
91 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
92 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
97 #define CONFIG_SYS_SICRH 0x08200000
98 #define CONFIG_SYS_SICRL 0x00000000
103 #define CONFIG_SYS_OBIR 0x30100000
108 #define CONFIG_SYS_IMMR 0xE0000000
[all …]
H A DMPC837XEMDS.h84 #define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
89 #define CONFIG_SYS_SICRH 0x00000000
90 #define CONFIG_SYS_SICRL 0x00000000
95 #define CONFIG_SYS_OBIR 0x31100000
102 #define CONFIG_SYS_IMMR 0xE0000000
107 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
115 /* 0x80080001 */ /* ODT 150ohm on SoC */
124 #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
132 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
138 /* 0x80010202 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dmobiveil-pcie.txt49 reg = <0xa0000000 0x00001000>,
50 <0xb0000000 0x00010000>,
51 <0xff000000 0x00200000>,
52 <0xb0010000 0x00001000>;
60 bus-range = <0x00000000 0x000000ff>;
64 interrupts = < 0 89 4 >;
65 interrupt-map-mask = <0 0 0 7>;
66 interrupt-map = <0 0 0 0 &pci_express 0>,
67 <0 0 0 1 &pci_express 1>,
68 <0 0 0 2 &pci_express 2>,
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx31.h60 #define FSL_IMX31_SECURE_ROM_ADDR 0x00000000
61 #define FSL_IMX31_SECURE_ROM_SIZE 0x4000
62 #define FSL_IMX31_ROM_ADDR 0x00404000
63 #define FSL_IMX31_ROM_SIZE 0x4000
64 #define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000
65 #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000
66 #define FSL_IMX31_IRAM_ADDR 0x1FFFC000
67 #define FSL_IMX31_IRAM_SIZE 0x4000
68 #define FSL_IMX31_I2C1_ADDR 0x43F80000
69 #define FSL_IMX31_I2C1_SIZE 0x4000
[all …]
/openbmc/linux/arch/sh/include/mach-common/mach/
H A Dsdk7780.h16 #define PA_ROM 0xa0000000 /* EPROM */
17 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
18 #define PA_FROM 0xa0800000 /* Flash-ROM */
19 #define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */
20 #define PA_EXT1 0xa4000000
21 #define PA_EXT1_SIZE 0x04000000
22 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
23 #define PA_SDRAM_SIZE 0x08000000
25 #define PA_EXT4 0xb0000000
26 #define PA_EXT4_SIZE 0x04000000
[all …]
/openbmc/u-boot/drivers/ddr/fsl/
H A Dmpc85xx_ddr_gen2.c38 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) { in fsl_ddr_set_memctl_regs()
41 out_be32(&gur->ddrioovcr, 0x90000000); in fsl_ddr_set_memctl_regs()
43 out_be32(&gur->ddrioovcr, 0xA8000000); in fsl_ddr_set_memctl_regs()
47 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { in fsl_ddr_set_memctl_regs()
48 if (i == 0) { in fsl_ddr_set_memctl_regs()
90 while (in_be32(&ddr->sdram_cfg_2) & 0x10) { in fsl_ddr_set_memctl_regs()
/openbmc/u-boot/board/renesas/ecovec/
H A Dlowlevel_init.S135 PVDR_D: .long 0x00000001
139 RWTCSR_D: .long 0x0000A507
141 MMUCR_D: .long 0x00000004
143 PLLCR_D: .long 0x00004000
145 FRQCRA_D: .long 0x8E003508
147 FRQCRB_D: .long 0x0
149 MMSELR_D: .long 0xA5A50000
151 CMNCR_D: .long 0x00000013
153 CS0BCR_D: .long 0x11110400
155 CS0WCR_D: .long 0x00000440
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dspear320.dtsi15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
20 reg = <0xb3000000 0x1000>;
26 reg = <0x90000000 0x1000>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
46 reg = <0x70000000 0x100>;
54 reg = <0xb3000000 0x1000>;
[all …]
/openbmc/linux/arch/sh/include/mach-se/mach/
H A Dse7780.h17 #define PA_ROM 0xa0000000 /* EPROM */
18 #define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */
19 #define PA_FROM 0xa1000000 /* Flash-ROM */
20 #define PA_FROM_SIZE 0x01000000 /* Flash-ROM size 16M byte */
21 #define PA_EXT1 0xa4000000
22 #define PA_EXT1_SIZE 0x04000000
25 #define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */
26 #define PA_SDRAM_SIZE 0x08000000
28 #define PA_EXT4 0xb0000000
29 #define PA_EXT4_SIZE 0x04000000
[all …]
/openbmc/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr25 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
26 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
27 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
30 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
31 0x14000000 - 0x17ffffff(CS5) | I2C | USB
32 0x18000000 - 0x1bffffff(CS6) | reserved | SD
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
[all …]
/openbmc/qemu/hw/arm/
H A Dimx25_pdk.c38 * 0x00000000-0x7fffffff See i.MX25 SOC fr support
39 * 0x80000000-0x87ffffff RAM + Alias EMULATED
40 * 0x90000000-0x9fffffff RAM + Alias EMULATED
41 * 0xa0000000-0xa7ffffff Flash IGNORED
42 * 0xa8000000-0xafffffff Flash IGNORED
43 * 0xb0000000-0xb1ffffff SRAM IGNORED
44 * 0xb2000000-0xb3ffffff SRAM IGNORED
45 * 0xb4000000-0xb5ffffff CS4 IGNORED
46 * 0xb6000000-0xb8000fff Reserved IGNORED
47 * 0xb8001000-0xb8001fff SDRAM CTRL reg IGNORED
[all …]
/openbmc/u-boot/board/espt/
H A Dlowlevel_init.S168 PACR_A: .long 0xFFEF0000
169 PBCR_A: .long 0xFFEF0002
170 PCCR_A: .long 0xFFEF0004
171 PDCR_A: .long 0xFFEF0006
172 PECR_A: .long 0xFFEF0008
173 PFCR_A: .long 0xFFEF000A
174 PGCR_A: .long 0xFFEF000C
175 PHCR_A: .long 0xFFEF000E
176 PICR_A: .long 0xFFEF0010
177 PJCR_A: .long 0xFFEF0012
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/openbmc/linux/arch/arm/boot/dts/samsung/
H A Ds5pv210-smdkv210.dts32 reg = <0x20000000 0x40000000>;
35 pmic_ap_clk: clock-0 {
38 #clock-cells = <0>;
44 reg = <0xa8000000 0x2>, <0xa8000002 0x2>;
53 pwms = <&pwm 3 5000000 0>;
54 brightness-levels = <0 4 8 16 32 64 128 255>;
57 pinctrl-0 = <&pwm3_out>;
61 dc5v_reg: regulator-0 {
79 pinctrl-0 = <&keypad_row0>, <&keypad_row1>, <&keypad_row2>,
88 keypad,row = <0>;
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h9 #define BIT_C 0x00000001
11 #define OP_BLR 0x4e800020
12 #define OP_EXTSB 0x7c000774
13 #define OP_EXTSH 0x7c000734
14 #define OP_NEG 0x7c0000d0
15 #define OP_CNTLZW 0x7c000034
16 #define OP_ADD 0x7c000214
17 #define OP_ADDC 0x7c000014
18 #define OP_ADDME 0x7c0001d4
19 #define OP_ADDZE 0x7c000194
[all …]

123