192f9cccaSSubrahmanya Lingappa* Mobiveil AXI PCIe Root Port Bridge DT description 292f9cccaSSubrahmanya Lingappa 392f9cccaSSubrahmanya LingappaMobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP 492f9cccaSSubrahmanya Lingappahas up to 8 outbound and inbound windows for the address translation. 592f9cccaSSubrahmanya Lingappa 692f9cccaSSubrahmanya LingappaRequired properties: 792f9cccaSSubrahmanya Lingappa- #address-cells: Address representation for root ports, set to <3> 892f9cccaSSubrahmanya Lingappa- #size-cells: Size representation for root ports, set to <2> 992f9cccaSSubrahmanya Lingappa- #interrupt-cells: specifies the number of cells needed to encode an 1092f9cccaSSubrahmanya Lingappa interrupt source. The value must be 1. 1192f9cccaSSubrahmanya Lingappa- compatible: Should contain "mbvl,gpex40-pcie" 1292f9cccaSSubrahmanya Lingappa- reg: Should contain PCIe registers location and length 1393bad0f5SHou Zhiqiang Mandatory: 1492f9cccaSSubrahmanya Lingappa "config_axi_slave": PCIe controller registers 1592f9cccaSSubrahmanya Lingappa "csr_axi_slave" : Bridge config registers 1693bad0f5SHou Zhiqiang Optional: 1792f9cccaSSubrahmanya Lingappa "gpio_slave" : GPIO registers to control slot power 1892f9cccaSSubrahmanya Lingappa "apb_csr" : MSI registers 1992f9cccaSSubrahmanya Lingappa 2092f9cccaSSubrahmanya Lingappa- device_type: must be "pci" 2192f9cccaSSubrahmanya Lingappa- apio-wins : number of requested apio outbound windows 2292f9cccaSSubrahmanya Lingappa default 2 outbound windows are configured - 2392f9cccaSSubrahmanya Lingappa 1. Config window 2492f9cccaSSubrahmanya Lingappa 2. Memory window 2592f9cccaSSubrahmanya Lingappa- ppio-wins : number of requested ppio inbound windows 2692f9cccaSSubrahmanya Lingappa default 1 inbound memory window is configured. 2792f9cccaSSubrahmanya Lingappa- bus-range: PCI bus numbers covered 2892f9cccaSSubrahmanya Lingappa- interrupt-controller: identifies the node as an interrupt controller 2992f9cccaSSubrahmanya Lingappa- #interrupt-cells: specifies the number of cells needed to encode an 3092f9cccaSSubrahmanya Lingappa interrupt source. The value must be 1. 3192f9cccaSSubrahmanya Lingappa- interrupts: The interrupt line of the PCIe controller 3292f9cccaSSubrahmanya Lingappa last cell of this field is set to 4 to 3392f9cccaSSubrahmanya Lingappa denote it as IRQ_TYPE_LEVEL_HIGH type interrupt. 3492f9cccaSSubrahmanya Lingappa- interrupt-map-mask, 3592f9cccaSSubrahmanya Lingappa interrupt-map: standard PCI properties to define the mapping of the 3692f9cccaSSubrahmanya Lingappa PCI interface to interrupt numbers. 3792f9cccaSSubrahmanya Lingappa- ranges: ranges for the PCI memory regions (I/O space region is not 3892f9cccaSSubrahmanya Lingappa supported by hardware) 3992f9cccaSSubrahmanya Lingappa Please refer to the standard PCI bus binding document for a more 4092f9cccaSSubrahmanya Lingappa detailed explanation 4192f9cccaSSubrahmanya Lingappa 4292f9cccaSSubrahmanya Lingappa 4392f9cccaSSubrahmanya LingappaExample: 4492f9cccaSSubrahmanya Lingappa++++++++ 4592f9cccaSSubrahmanya Lingappa pcie0: pcie@a0000000 { 4692f9cccaSSubrahmanya Lingappa #address-cells = <3>; 4792f9cccaSSubrahmanya Lingappa #size-cells = <2>; 4892f9cccaSSubrahmanya Lingappa compatible = "mbvl,gpex40-pcie"; 4992f9cccaSSubrahmanya Lingappa reg = <0xa0000000 0x00001000>, 5092f9cccaSSubrahmanya Lingappa <0xb0000000 0x00010000>, 5192f9cccaSSubrahmanya Lingappa <0xff000000 0x00200000>, 5292f9cccaSSubrahmanya Lingappa <0xb0010000 0x00001000>; 5392f9cccaSSubrahmanya Lingappa reg-names = "config_axi_slave", 5492f9cccaSSubrahmanya Lingappa "csr_axi_slave", 5592f9cccaSSubrahmanya Lingappa "gpio_slave", 5692f9cccaSSubrahmanya Lingappa "apb_csr"; 5792f9cccaSSubrahmanya Lingappa device_type = "pci"; 5892f9cccaSSubrahmanya Lingappa apio-wins = <2>; 5992f9cccaSSubrahmanya Lingappa ppio-wins = <1>; 6092f9cccaSSubrahmanya Lingappa bus-range = <0x00000000 0x000000ff>; 6192f9cccaSSubrahmanya Lingappa interrupt-controller; 6292f9cccaSSubrahmanya Lingappa interrupt-parent = <&gic>; 6392f9cccaSSubrahmanya Lingappa #interrupt-cells = <1>; 6492f9cccaSSubrahmanya Lingappa interrupts = < 0 89 4 >; 6592f9cccaSSubrahmanya Lingappa interrupt-map-mask = <0 0 0 7>; 6692f9cccaSSubrahmanya Lingappa interrupt-map = <0 0 0 0 &pci_express 0>, 6792f9cccaSSubrahmanya Lingappa <0 0 0 1 &pci_express 1>, 6892f9cccaSSubrahmanya Lingappa <0 0 0 2 &pci_express 2>, 6992f9cccaSSubrahmanya Lingappa <0 0 0 3 &pci_express 3>; 7092f9cccaSSubrahmanya Lingappa ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>; 7192f9cccaSSubrahmanya Lingappa 7292f9cccaSSubrahmanya Lingappa }; 73