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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_vcn.h38 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
41 #define VCN_DEC_KMD_CMD 0x80000000
42 #define VCN_DEC_CMD_FENCE 0x00000000
43 #define VCN_DEC_CMD_TRAP 0x00000001
44 #define VCN_DEC_CMD_WRITE_REG 0x00000004
45 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
46 #define VCN_DEC_CMD_PACKET_START 0x0000000a
47 #define VCN_DEC_CMD_PACKET_END 0x0000000b
49 #define VCN_DEC_SW_CMD_NO_OP 0x00000000
50 #define VCN_DEC_SW_CMD_END 0x00000001
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8723ae/
H A Dhal_bt_coexist.c86 u8 bt_rssi_state = 0; in rtl8723e_dm_bt_check_coex_rssi_state1()
213 long undecoratedsmoothed_pwdb = 0; in rtl8723e_dm_bt_check_coex_rssi_state()
214 u8 bt_rssi_state = 0; in rtl8723e_dm_bt_check_coex_rssi_state()
336 long undecoratedsmoothed_pwdb = 0; in rtl8723e_dm_bt_get_rx_ss()
356 u8 h2c_parameter[3] = {0}; in rtl8723e_dm_bt_balance()
361 h2c_parameter[0] = ms0; in rtl8723e_dm_bt_balance()
364 h2c_parameter[2] = 0; in rtl8723e_dm_bt_balance()
365 h2c_parameter[1] = 0; in rtl8723e_dm_bt_balance()
366 h2c_parameter[0] = 0; in rtl8723e_dm_bt_balance()
371 "[DM][BT], Balance=[%s:%dms:%dms], write 0xc=0x%x\n", in rtl8723e_dm_bt_balance()
[all …]
/openbmc/linux/drivers/net/ethernet/huawei/hinic/
H A Dhinic_hw_qp_ctxt.h17 #define HINIC_SQ_CTXT_CEQ_ATTR_GLOBAL_SQ_ID_MASK 0x3FF
18 #define HINIC_SQ_CTXT_CEQ_ATTR_EN_MASK 0x1
27 #define HINIC_SQ_CTXT_CI_IDX_MASK 0xFFF
28 #define HINIC_SQ_CTXT_CI_WRAPPED_MASK 0x1
34 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_SHIFT 0
37 #define HINIC_SQ_CTXT_WQ_PAGE_HI_PFN_MASK 0xFFFFF
38 #define HINIC_SQ_CTXT_WQ_PAGE_PI_MASK 0xFFF
44 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_SHIFT 0
48 #define HINIC_SQ_CTXT_PREF_CACHE_THRESHOLD_MASK 0x3FFF
49 #define HINIC_SQ_CTXT_PREF_CACHE_MAX_MASK 0x7FF
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Dphy.h96 RTW_DECL_TABLE_PHY_COND_CORE(name, cfg, 0)
121 if (chip->rfe_defs_size == 0) in rtw_get_rfe_def()
141 return 0; in rtw_check_supported_rfe()
168 #define MASKBYTE0 0xff
169 #define MASKBYTE1 0xff00
170 #define MASKBYTE2 0xff0000
171 #define MASKBYTE3 0xff000000
172 #define MASKHWORD 0xffff0000
173 #define MASKLWORD 0x0000ffff
174 #define MASKDWORD 0xffffffff
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHalBtc8723b2Ant.c15 } while (0)
28 s32 btRssi = 0; in halbtc8723b2ant_BtRssiState()
97 s32 wifiRssi = 0; in halbtc8723b2ant_WifiRssiState()
184 u8 H2C_Parameter[1] = {0}; in halbtc8723b2ant_QueryBtInfo()
188 H2C_Parameter[0] |= BIT0; /* trigger */ in halbtc8723b2ant_QueryBtInfo()
190 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); in halbtc8723b2ant_QueryBtInfo()
293 u8 numOfDiffProfile = 0; in halbtc8723b2ant_ActionAlgorithm()
421 u8 H2C_Parameter[1] = {0}; in halbtc8723b2ant_SetFwDacSwingLevel()
424 /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ in halbtc8723b2ant_SetFwDacSwingLevel()
425 H2C_Parameter[0] = dacSwingLvl; in halbtc8723b2ant_SetFwDacSwingLevel()
[all …]
/openbmc/linux/include/linux/mfd/syscon/
H A Datmel-st.h15 #define AT91_ST_CR 0x00 /* Control Register */
16 #define AT91_ST_WDRST BIT(0) /* Watchdog Timer Restart */
18 #define AT91_ST_PIMR 0x04 /* Period Interval Mode Register */
19 #define AT91_ST_PIV 0xffff /* Period Interval Value */
21 #define AT91_ST_WDMR 0x08 /* Watchdog Mode Register */
22 #define AT91_ST_WDV 0xffff /* Watchdog Counter Value */
26 #define AT91_ST_RTMR 0x0c /* Real-time Mode Register */
27 #define AT91_ST_RTPRES 0xffff /* Real-time Prescalar Value */
29 #define AT91_ST_SR 0x10 /* Status Register */
30 #define AT91_ST_PITS BIT(0) /* Period Interval Timer Status */
[all …]
/openbmc/u-boot/arch/arm/mach-at91/armv7/
H A Dtimer.c26 * setting the 20 bit counter period to its maximum (0xfffff).
35 #define TIMER_LOAD_VAL 0xfffff
52 return 0; in timer_init()
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dtimer.c23 * setting the 20 bit counter period to its maximum (0xfffff).
32 #define TIMER_LOAD_VAL 0xfffff
48 return 0; in timer_init()
/openbmc/linux/arch/x86/platform/pvh/
H A Dhead.S31 * - `cr0`: bit 0 (PE) must be set. All the other writeable bits are cleared.
33 * - `cs `: must be a 32-bit read/execute code segment with a base of `0`
34 * and a limit of `0xFFFFFFFF`. The selector value is unspecified.
36 * `0` and a limit of `0xFFFFFFFF`. The selector values are all
38 * - `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit
39 * of '0x67'.
146 .word 0
149 .quad 0x0000000000000000 /* NULL descriptor */
151 .quad GDT_ENTRY(0xa09a, 0, 0xfffff) /* PVH_CS_SEL */
153 .quad GDT_ENTRY(0xc09a, 0, 0xfffff) /* PVH_CS_SEL */
[all …]
/openbmc/qemu/hw/pci-host/
H A Dmv64361.c87 memory_region_init(&s->io, OBJECT(dev), name, 0x10000); in mv64361_pcihost_realize()
95 &s->mem, &s->io, 0, 4, TYPE_PCI_BUS); in mv64361_pcihost_realize()
97 pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE); in mv64361_pcihost_realize()
102 DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
243 val &= 0x1fffff; in set_mem_windows()
244 for (mask = 1, i = 0; i < 21; i++, mask <<= 1) { in set_mem_windows()
248 * 0-3 are SDRAM chip selects but we map all RAM directly in set_mem_windows()
253 p = &s->pci[0]; in set_mem_windows()
259 (p->io_base & 0xfffff) << 16); in set_mem_windows()
262 p = &s->pci[0]; in set_mem_windows()
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/openbmc/linux/arch/loongarch/net/
H A Dbpf_jit.h37 } while (0)
73 emit_insn(ctx, lu32id, reg, 0); in emit_zext_32()
82 emit_insn(ctx, addiw, reg, reg, 0); in emit_sext_32()
90 imm_31_12 = (addr >> 12) & 0xfffff; in move_addr()
94 imm_11_0 = addr & 0xfff; in move_addr()
98 imm_51_32 = (addr >> 32) & 0xfffff; in move_addr()
102 imm_63_52 = (addr >> 52) & 0xfff; in move_addr()
111 if (imm == 0) { in move_imm()
129 imm_63_52 = (imm >> 52) & 0xfff; in move_imm()
130 imm_51_0 = imm & 0xfffffffffffff; in move_imm()
[all …]
/openbmc/linux/drivers/scsi/csiostor/
H A Dt4fw_api_stor.h44 FCOE_LINK_DOWN = 0x0,
45 FCOE_LINK_UP = 0x1,
46 FCOE_LINK_COND = 0x2,
50 FCOE_LINKDOWN = 0x0,
51 FCOE_LINKUP = 0x1,
55 PROT_FCOE = 0x1,
56 PROT_ISCSI = 0x2,
60 FLOGI_VFPORT = 0x1, /* 0xfffffe */
61 FDISC_VFPORT = 0x2, /* 0xfffffe */
62 NS_VNPORT = 0x3, /* 0xfffffc */
[all …]
/openbmc/u-boot/arch/x86/cpu/i386/
H A Dcpu.c37 ((((base) & 0xff000000ULL) << (56-24)) | \
38 (((flags) & 0x0000f0ffULL) << 40) | \
39 (((limit) & 0x000f0000ULL) << (48-16)) | \
40 (((base) & 0x00ffffffULL) << 16) | \
41 (((limit) & 0x0000ffffULL)))
83 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_ds()
88 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_es()
93 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_fs()
98 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_gs()
103 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_ss()
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/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dpmmu_hbw_stlb_masks.h24 #define PMMU_HBW_STLB_BUSY_BUSY_SHIFT 0
25 #define PMMU_HBW_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define PMMU_HBW_STLB_ASID_ASID_SHIFT 0
29 #define PMMU_HBW_STLB_ASID_ASID_MASK 0x3FF
32 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define PMMU_HBW_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define PMMU_HBW_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define PMMU_HBW_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
H A Ddcore0_hmmu0_stlb_masks.h24 #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0
25 #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF
28 #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0
29 #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF
32 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0
33 #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF
36 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0
37 #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF
40 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0
41 #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Devergreen_dma.c46 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0)); in evergreen_dma_fence_ring_emit()
47 radeon_ring_write(ring, addr & 0xfffffffc); in evergreen_dma_fence_ring_emit()
48 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
51 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0)); in evergreen_dma_fence_ring_emit()
53 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0)); in evergreen_dma_fence_ring_emit()
54 radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); in evergreen_dma_fence_ring_emit()
76 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 1)); in evergreen_dma_ring_ib_execute()
77 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in evergreen_dma_ring_ib_execute()
78 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
86 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0)); in evergreen_dma_ring_ib_execute()
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpam.h35 * 0xa0000 - 0xbffff compatible SMRAM
37 * 0xc0000 - 0xc3fff Expansion area memory segments
38 * 0xc4000 - 0xc7fff
39 * 0xc8000 - 0xcbfff
40 * 0xcc000 - 0xcffff
41 * 0xd0000 - 0xd3fff
42 * 0xd4000 - 0xd7fff
43 * 0xd8000 - 0xdbfff
44 * 0xdc000 - 0xdffff
45 * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
[all …]
/openbmc/linux/drivers/firmware/efi/libstub/
H A Dx86-5lvl.c16 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
17 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
37 if (native_cpuid_eax(0) < 7 || in efi_setup_5level_paging()
48 memset(la57_code + tmpl_size, 0x90, PAGE_SIZE - tmpl_size); in efi_setup_5level_paging()
81 new_cr3 = memset(pgt, 0, PAGE_SIZE); in efi_5level_switch()
82 new_cr3[0] = (u64)cr3 | _PAGE_TABLE_NOENC; in efi_5level_switch()
84 /* take the new root table pointer from the current entry #0 */ in efi_5level_switch()
85 new_cr3 = (u64 *)(cr3[0] & PAGE_MASK); in efi_5level_switch()
/openbmc/qemu/tests/migration/i386/
H A Da-b-bootblock.S14 #define ACPI_ENABLE 0xf1
15 #define ACPI_PORT_SMI_CMD 0xb2
16 #define ACPI_PM_BASE 0x600
19 #define ACPI_SCI_ENABLE 0x0001
20 #define ACPI_SLEEP_TYPE 0x0400
21 #define ACPI_SLEEP_ENABLE 0x2000
31 .org 0x7c00
36 start: # at 0x7c00 ?
41 data32 ljmp $8,$0x7c20
43 .org 0x7c20
[all …]
/openbmc/qemu/hw/misc/
H A Dbcm2835_rng.c41 uint32_t res = 0; in bcm2835_rng_read()
46 case 0x0: /* rng_ctrl */ in bcm2835_rng_read()
49 case 0x4: /* rng_status */ in bcm2835_rng_read()
52 case 0x8: /* rng_data */ in bcm2835_rng_read()
60 res = 0; in bcm2835_rng_read()
75 case 0x0: /* rng_ctrl */ in bcm2835_rng_write()
78 case 0x4: /* rng_status */ in bcm2835_rng_write()
80 s->rng_status &= ~0xFFFFF; /* clear 20 lower bits */ in bcm2835_rng_write()
81 s->rng_status |= value & 0xFFFFF; /* set them to new value */ in bcm2835_rng_write()
114 TYPE_BCM2835_RNG, 0x10); in bcm2835_rng_init()
[all …]
H A Dxlnx-versal-xramc.c20 #define XLNX_XRAM_CTRL_ERR_DEBUG 0
42 return 0; in xram_ien_prew()
52 return 0; in xram_ids_prew()
57 .reset = 0xf,
58 .rsvd = 0xfffffff0,
60 .rsvd = 0xfffff800,
61 .w1c = 0x7ff,
64 .reset = 0x7ff,
65 .rsvd = 0xfffff800,
66 .ro = 0x7ff,
[all …]
/openbmc/linux/sound/soc/tegra/
H A Dtegra20_spdif.h19 #define TEGRA20_SPDIF_CTRL 0x0
20 #define TEGRA20_SPDIF_STATUS 0x4
21 #define TEGRA20_SPDIF_STROBE_CTRL 0x8
22 #define TEGRA20_SPDIF_DATA_FIFO_CSR 0x0C
23 #define TEGRA20_SPDIF_DATA_OUT 0x40
24 #define TEGRA20_SPDIF_DATA_IN 0x80
25 #define TEGRA20_SPDIF_CH_STA_RX_A 0x100
26 #define TEGRA20_SPDIF_CH_STA_RX_B 0x104
27 #define TEGRA20_SPDIF_CH_STA_RX_C 0x108
28 #define TEGRA20_SPDIF_CH_STA_RX_D 0x10C
[all …]
/openbmc/linux/arch/x86/boot/
H A Dpm.c23 asm volatile("lcallw *%0" in realmode_switch_hook()
28 outb(0x80, 0x70); /* Disable NMI */ in realmode_switch_hook()
38 outb(0xff, 0xa1); /* Mask all interrupts on the secondary PIC */ in mask_all_interrupts()
40 outb(0xfb, 0x21); /* Mask all but cascade on the primary PIC */ in mask_all_interrupts()
49 outb(0, 0xf0); in reset_coprocessor()
51 outb(0, 0xf1); in reset_coprocessor()
69 /* CS: code, read/execute, 4 GB, base 0 */ in setup_gdt()
70 [GDT_ENTRY_BOOT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff), in setup_gdt()
71 /* DS: data, read/write, 4 GB, base 0 */ in setup_gdt()
72 [GDT_ENTRY_BOOT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff), in setup_gdt()
[all …]
/openbmc/qemu/hw/watchdog/
H A Dwdt_aspeed.c23 #define WDT_STATUS (0x00 / 4)
24 #define WDT_RELOAD_VALUE (0x04 / 4)
25 #define WDT_RESTART (0x08 / 4)
26 #define WDT_CTRL (0x0C / 4)
27 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
28 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
33 #define WDT_CTRL_ENABLE BIT(0)
34 #define WDT_RESET_WIDTH (0x18 / 4)
36 #define WDT_POLARITY_MASK (0xFF << 24)
37 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
[all …]
/openbmc/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dsge_defs.h9 #define S_EC_CREDITS 0
10 #define M_EC_CREDITS 0x7FFF
19 #define M_EC_INDEX 0xFFFF
23 #define S_EC_SIZE 0
24 #define M_EC_SIZE 0xFFFF
29 #define M_EC_BASE_LO 0xFFFF
33 #define S_EC_BASE_HI 0
34 #define M_EC_BASE_HI 0xF
39 #define M_EC_RESPQ 0x7
44 #define M_EC_TYPE 0x7
[all …]

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