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/openbmc/u-boot/arch/arm/mach-at91/armv7/
H A Dtimer.c26 * setting the 20 bit counter period to its maximum (0xfffff).
35 #define TIMER_LOAD_VAL 0xfffff
52 return 0; in timer_init()
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dtimer.c23 * setting the 20 bit counter period to its maximum (0xfffff).
32 #define TIMER_LOAD_VAL 0xfffff
48 return 0; in timer_init()
/openbmc/libcper/generator/sections/
H A Dgen-section-memory.c23 //Validation 22-63 reserved. 19/20=0 for bank in generate_section_memory()
24 *validation &= 0x27FFFF; in generate_section_memory()
26 *validation = 0x27FFFF; in generate_section_memory()
28 *validation = 0x275555; in generate_section_memory()
30 *(bytes + 73) &= ~0x1C; //Extended bits 2-4 in generate_section_memory()
54 //Validation 22-63, 20/21 is 0 since 6 is valid in generate_section_memory2()
55 *validation &= 0xFFFFF; in generate_section_memory2()
57 *validation = 0xFFFFF; in generate_section_memory2()
59 *validation = 0x55555; in generate_section_memory2()
61 *(bytes + 63) = 0; //Reserved byte 63 in generate_section_memory2()
/openbmc/qemu/include/hw/pci-host/
H A Dpam.h35 * 0xa0000 - 0xbffff compatible SMRAM
37 * 0xc0000 - 0xc3fff Expansion area memory segments
38 * 0xc4000 - 0xc7fff
39 * 0xc8000 - 0xcbfff
40 * 0xcc000 - 0xcffff
41 * 0xd0000 - 0xd3fff
42 * 0xd4000 - 0xd7fff
43 * 0xd8000 - 0xdbfff
44 * 0xdc000 - 0xdffff
45 * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
[all …]
/openbmc/qemu/hw/pci-host/
H A Dmv64361.c87 memory_region_init(&s->io, OBJECT(dev), name, 0x10000); in mv64361_pcihost_realize()
95 &s->mem, &s->io, 0, 4, TYPE_PCI_BUS); in mv64361_pcihost_realize()
97 pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE); in mv64361_pcihost_realize()
102 DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
242 val &= 0x1fffff; in set_mem_windows()
243 for (mask = 1, i = 0; i < 21; i++, mask <<= 1) { in set_mem_windows()
247 * 0-3 are SDRAM chip selects but we map all RAM directly in set_mem_windows()
252 p = &s->pci[0]; in set_mem_windows()
258 (p->io_base & 0xfffff) << 16); in set_mem_windows()
261 p = &s->pci[0]; in set_mem_windows()
[all …]
/openbmc/qemu/tests/qtest/migration/i386/
H A Da-b-bootblock.S14 #define ACPI_ENABLE 0xf1
15 #define ACPI_PORT_SMI_CMD 0xb2
16 #define ACPI_PM_BASE 0x600
19 #define ACPI_SCI_ENABLE 0x0001
20 #define ACPI_SLEEP_TYPE 0x0400
21 #define ACPI_SLEEP_ENABLE 0x2000
31 .org 0x7c00
36 start: # at 0x7c00 ?
41 data32 ljmp $8,$0x7c20
43 .org 0x7c20
[all …]
/openbmc/qemu/hw/misc/
H A Dbcm2835_rng.c41 uint32_t res = 0; in bcm2835_rng_read()
46 case 0x0: /* rng_ctrl */ in bcm2835_rng_read()
49 case 0x4: /* rng_status */ in bcm2835_rng_read()
52 case 0x8: /* rng_data */ in bcm2835_rng_read()
60 res = 0; in bcm2835_rng_read()
75 case 0x0: /* rng_ctrl */ in bcm2835_rng_write()
78 case 0x4: /* rng_status */ in bcm2835_rng_write()
80 s->rng_status &= ~0xFFFFF; /* clear 20 lower bits */ in bcm2835_rng_write()
81 s->rng_status |= value & 0xFFFFF; /* set them to new value */ in bcm2835_rng_write()
114 TYPE_BCM2835_RNG, 0x10); in bcm2835_rng_init()
[all …]
H A Dxlnx-versal-xramc.c20 #define XLNX_XRAM_CTRL_ERR_DEBUG 0
42 return 0; in xram_ien_prew()
52 return 0; in xram_ids_prew()
57 .reset = 0xf,
58 .rsvd = 0xfffffff0,
60 .rsvd = 0xfffff800,
61 .w1c = 0x7ff,
64 .reset = 0x7ff,
65 .rsvd = 0xfffff800,
66 .ro = 0x7ff,
[all …]
/openbmc/u-boot/arch/x86/cpu/i386/
H A Dcpu.c37 ((((base) & 0xff000000ULL) << (56-24)) | \
38 (((flags) & 0x0000f0ffULL) << 40) | \
39 (((limit) & 0x000f0000ULL) << (48-16)) | \
40 (((base) & 0x00ffffffULL) << 16) | \
41 (((limit) & 0x0000ffffULL)))
83 asm volatile("movl %0, %%ds" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_ds()
88 asm volatile("movl %0, %%es" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_es()
93 asm volatile("movl %0, %%fs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_fs()
98 asm volatile("movl %0, %%gs" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_gs()
103 asm volatile("movl %0, %%ss" : : "r" (segment * X86_GDT_ENTRY_SIZE)); in load_ss()
[all …]
/openbmc/u-boot/include/
H A Datmel_lcdc.h12 #define ATMEL_LCDC_DMABADDR1 0x00
13 #define ATMEL_LCDC_DMABADDR2 0x04
14 #define ATMEL_LCDC_DMAFRMPT1 0x08
15 #define ATMEL_LCDC_DMAFRMPT2 0x0c
16 #define ATMEL_LCDC_DMAFRMADD1 0x10
17 #define ATMEL_LCDC_DMAFRMADD2 0x14
19 #define ATMEL_LCDC_DMAFRMCFG 0x18
20 #define ATMEL_LCDC_FRSIZE (0x7fffff << 0)
22 #define ATMEL_LCDC_BLENGTH (0x7f << ATMEL_LCDC_BLENGTH_OFFSET)
24 #define ATMEL_LCDC_DMACON 0x1c
[all …]
/openbmc/qemu/hw/watchdog/
H A Dwdt_aspeed.c23 #define WDT_STATUS (0x00 / 4)
24 #define WDT_RELOAD_VALUE (0x04 / 4)
25 #define WDT_RESTART (0x08 / 4)
26 #define WDT_CTRL (0x0C / 4)
27 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
28 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
33 #define WDT_CTRL_ENABLE BIT(0)
34 #define WDT_RESET_WIDTH (0x18 / 4)
36 #define WDT_POLARITY_MASK (0xFF << 24)
37 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
[all …]
H A Dwdt_i6300esb.c41 #define ESB_CONFIG_REG 0x60 /* Config register */
42 #define ESB_LOCK_REG 0x68 /* WDT lock register */
45 #define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
46 #define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
47 #define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
48 #define ESB_RELOAD_REG 0x0c /* Reload register */
51 #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
52 #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
53 #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
56 #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
[all …]
/openbmc/qemu/pc-bios/optionrom/
H A Dpvh.S28 #define GS_PROT_JUMP 0
48 .short 0xaa55; \
62 shl $0x4, %eax
68 shl $0x4, %ecx
71 sub $0x20, %ecx
72 sub $0x30, %esp
73 shr $0x4, %ecx
90 /* initialize HVM memmap table using int 0x15(e820) */
111 movl $0x0000e820, %eax
113 movl $0x534d4150, %edx
[all …]
H A Dlinuxboot.S50 add $0x20, %bx
64 pushw %ax /* IP = 0 */
79 /* Read info block in low memory (0x10000 or 0x90000) */
86 cmpw $0x203, %es:0x206 // if protocol >= 0x203
88 movl $0x37ffffff, %es:0x22c // else assume 0x37ffffff
96 xor %es:0x22c, %eax // if it matches es:0x22c
104 mov $0xe801, %ax
107 int $0x15
134 movl %edi, %es:0x218 /* put it in the header */
162 mov $0x10, %eax
[all …]
H A Dmultiboot.S25 #define MULTIBOOT_MAGIC 0x2badb002
27 #define GS_PROT_JUMP 0
39 shl $0x4, %eax
45 shl $0x4, %ecx
48 sub $0x20, %ecx
49 sub $0x30, %esp
50 shr $0x4, %ecx
81 int $0x12
90 /* Initialize multiboot mmap structs using int 0x15(e820) */
92 /* Start storing mmap data at %es:0 */
[all...]
/openbmc/qemu/bsd-user/x86_64/
H A Dtarget_arch_cpu.h32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()
65 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), in target_cpu_init()
66 PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); in target_cpu_init()
68 bsd_x86_64_set_idt(0, 0); in target_cpu_init()
69 bsd_x86_64_set_idt(1, 0); in target_cpu_init()
70 bsd_x86_64_set_idt(2, 0); in target_cpu_init()
73 bsd_x86_64_set_idt(5, 0); in target_cpu_init()
74 bsd_x86_64_set_idt(6, 0); in target_cpu_init()
75 bsd_x86_64_set_idt(7, 0); in target_cpu_init()
76 bsd_x86_64_set_idt(8, 0); in target_cpu_init()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dap.c30 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for in tegra_get_chip()
31 * Tegra30, 0x35 for T114, and 0x40 for Tegra124. in tegra_get_chip()
34 debug("%s: CHIPID is 0x%02X\n", __func__, rev); in tegra_get_chip()
44 sku_id = readl(&fuse->sku_info) & 0xff; in tegra_get_sku_info()
45 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); in tegra_get_sku_info()
105 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", in tegra_get_chip_sku()
125 writel(0xFFFF, &scu->scu_inv_all); in enable_scu()
127 /* Enable SCU - bit 0 */ in enable_scu()
162 for (i = 0; i < 23; i++) in init_pmc_scratch()
163 writel(0, &pmc->pmc_scratch1 + i); in init_pmc_scratch()
[all …]
/openbmc/qemu/bsd-user/i386/
H A Dtarget_arch_cpu.h32 env->cr[0] = CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK; in target_cpu_init()
56 env->idt.base = target_mmap(0, sizeof(uint64_t) * (env->idt.limit + 1), in target_cpu_init()
57 PROT_READ | PROT_WRITE, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); in target_cpu_init()
59 bsd_i386_set_idt(0, 0); in target_cpu_init()
60 bsd_i386_set_idt(1, 0); in target_cpu_init()
61 bsd_i386_set_idt(2, 0); in target_cpu_init()
64 bsd_i386_set_idt(5, 0); in target_cpu_init()
65 bsd_i386_set_idt(6, 0); in target_cpu_init()
66 bsd_i386_set_idt(7, 0); in target_cpu_init()
67 bsd_i386_set_idt(8, 0); in target_cpu_init()
[all …]
/openbmc/u-boot/drivers/timer/
H A Datmel_pit_timer.c13 #define AT91_PIT_VALUE 0xfffff
35 return 0; in atmel_pit_get_count()
47 ret = clk_get_by_index(dev, 0, &clk); in atmel_pit_probe()
59 return 0; in atmel_pit_probe()
68 return 0; in atmel_pit_ofdata_to_platdata()
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Network/Experimental/
H A DTunnel.interface.yaml36 the range 0–0xFFFFF, or be set to "inherit", in which case the
/openbmc/u-boot/board/syteco/zmx25/
H A Dlowlevel_init.S24 write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
25 write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
31 write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
32 write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
33 write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
36 write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
58 ldr r1, =0x002a7420
62 ldr r1, =0x92216008
65 str r1, [r2, #0x400]
68 ldr r1, =0xa2216008
[all …]
/openbmc/u-boot/board/d-link/dns325/
H A Dkwbimage.cfg17 NAND_PAGE_SIZE 0x0800
22 # Configure RGMII-0 interface pad voltage to 1.8V
23 DATA 0xFFD100e0 0x1b1b1b9b
26 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
27 # bit13-0: 0xc30, 3120 DDR2 clks refresh rate
28 # bit23-14: 0 required
31 # bit29-26: 0 required
32 # bit31-30: 0b01 required
34 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
35 # bit3-0: 0 required
[all …]
/openbmc/qemu/linux-user/i386/
H A Dcpu_loop.c41 e1 = (addr << 16) | (limit & 0xffff); in write_dt()
42 e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000); in write_dt()
45 p[0] = tswap32(e1); in write_dt()
55 e1 = (addr & 0xffff) | (sel << 16); in set_gate64()
56 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); in set_gate64()
58 p[0] = tswap32(e1); in set_gate64()
61 p[3] = 0; in set_gate64()
68 set_gate64(idt_table + n * 2, 0, dpl, 0, 0); in set_idt()
75 e1 = (addr & 0xffff) | (sel << 16); in set_gate()
76 e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8); in set_gate()
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dddr.c19 #define DDR_CTRL_UPD_MRS BIT(0)
22 #define DDR_REFRESH_M 0x3ff
23 #define DDR_REFRESH(x) ((x) & 0x3ff)
27 #define DDR_TRAS_S 0
28 #define DDR_TRAS_M 0x1f
30 #define DDR_TRCD_M 0xf
33 #define DDR_TRP_M 0xf
36 #define DDR_TRRD_M 0xf
39 #define DDR_TRFC_M 0x7f
42 #define DDR_TMRD_M 0xf
[all …]
/openbmc/u-boot/board/CZ.NIC/turris_mox/
H A Dmox_sp.c9 #define RWTM_CMD_PARAM(i) (size_t)(0xd00b0000 + (i) * 4)
10 #define RWTM_CMD 0xd00b0040
11 #define RWTM_CMD_RETSTATUS 0xd00b0080
12 #define RWTM_CMD_STATUS(i) (size_t)(0xd00b0084 + (i) * 4)
14 #define RWTM_HOST_INT_RESET 0xd00b00c8
15 #define RWTM_HOST_INT_MASK 0xd00b00cc
16 #define SP_CMD_COMPLETE BIT(0)
18 #define MBOX_STS_SUCCESS (0x0 << 30)
19 #define MBOX_STS_FAIL (0x1 << 30)
20 #define MBOX_STS_BADCMD (0x2 << 30)
[all …]

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