Lines Matching +full:0 +full:xfffff

41 #define ESB_CONFIG_REG  0x60            /* Config register                   */
42 #define ESB_LOCK_REG 0x68 /* WDT lock register */
45 #define ESB_TIMER1_REG 0x00 /* Timer1 value after each reset */
46 #define ESB_TIMER2_REG 0x04 /* Timer2 value after each reset */
47 #define ESB_GINTSR_REG 0x08 /* General Interrupt Status Register */
48 #define ESB_RELOAD_REG 0x0c /* Reload register */
51 #define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */
52 #define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */
53 #define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */
56 #define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */
57 #define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */
58 #define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */
61 #define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */
64 #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */
65 #define ESB_UNLOCK2 0x86 /* Step 2 to unlock reset registers */
77 #define CLOCK_SCALE_1KHZ 0
81 #define INT_TYPE_IRQ 0 /* APIC 1, INT 10 */
95 int unlock_state; /* Guest writes 0x80, 0x86 to unlock the
97 * states 0 -> 1 -> 2 when this happens.
162 d->free_run = 0; in i6300esb_reset()
163 d->locked = 0; in i6300esb_reset()
164 d->enabled = 0; in i6300esb_reset()
165 d->timer1_preload = 0xfffff; in i6300esb_reset()
166 d->timer2_preload = 0xfffff; in i6300esb_reset()
168 d->unlock_state = 0; in i6300esb_reset()
220 d->reboot_enabled = (data & ESB_WDT_REBOOT) == 0; in i6300esb_config_write()
222 (data & ESB_WDT_FREQ) != 0 ? CLOCK_SCALE_1MHZ : CLOCK_SCALE_1KHZ; in i6300esb_config_write()
226 d->locked = (data & ESB_WDT_LOCK) != 0; in i6300esb_config_write()
227 d->free_run = (data & ESB_WDT_FUNC) != 0; in i6300esb_config_write()
229 d->enabled = (data & ESB_WDT_ENABLE) != 0; in i6300esb_config_write()
230 if (!old && d->enabled) /* Enabled transitioned from 0 -> 1 */ in i6300esb_config_write()
249 (d->reboot_enabled ? 0 : ESB_WDT_REBOOT) | in i6300esb_config_read()
250 (d->clock_scale == CLOCK_SCALE_1MHZ ? ESB_WDT_FREQ : 0) | in i6300esb_config_read()
255 (d->free_run ? ESB_WDT_FUNC : 0) | in i6300esb_config_read()
256 (d->locked ? ESB_WDT_LOCK : 0) | in i6300esb_config_read()
257 (d->enabled ? ESB_WDT_ENABLE : 0); in i6300esb_config_read()
268 return 0; in i6300esb_mem_readb()
273 uint32_t data = 0; in i6300esb_mem_readw()
278 if (addr == 0xc) { in i6300esb_mem_readw()
283 data = d->previous_reboot_flag ? 0x1200 : 0; in i6300esb_mem_readw()
293 return 0; in i6300esb_mem_readl()
302 if (addr == 0xc && val == 0x80) in i6300esb_mem_writeb()
304 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) in i6300esb_mem_writeb()
314 if (addr == 0xc && val == 0x80) in i6300esb_mem_writew()
316 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) in i6300esb_mem_writew()
320 if (addr == 0xc) { in i6300esb_mem_writew()
321 if ((val & 0x100) != 0) in i6300esb_mem_writew()
331 if ((val & 0x200) != 0 || (val & 0x1000) != 0) { in i6300esb_mem_writew()
332 d->previous_reboot_flag = 0; in i6300esb_mem_writew()
336 d->unlock_state = 0; in i6300esb_mem_writew()
347 if (addr == 0xc && val == 0x80) in i6300esb_mem_writel()
349 else if (addr == 0xc && val == 0x86 && d->unlock_state == 1) in i6300esb_mem_writel()
353 if (addr == 0) in i6300esb_mem_writel()
354 d->timer1_preload = val & 0xfffff; in i6300esb_mem_writel()
356 d->timer2_preload = val & 0xfffff; in i6300esb_mem_writel()
358 d->unlock_state = 0; in i6300esb_mem_writel()
446 d->previous_reboot_flag = 0; in i6300esb_realize()
449 "i6300esb", 0x10); in i6300esb_realize()
450 pci_register_bar(&d->dev, 0, 0, &d->io_mem); in i6300esb_realize()