Lines Matching +full:0 +full:xfffff
87 memory_region_init(&s->io, OBJECT(dev), name, 0x10000); in mv64361_pcihost_realize()
95 &s->mem, &s->io, 0, 4, TYPE_PCI_BUS); in mv64361_pcihost_realize()
97 pci_create_simple(h->bus, 0, TYPE_MV64361_PCI_BRIDGE); in mv64361_pcihost_realize()
102 DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0),
243 val &= 0x1fffff; in set_mem_windows()
244 for (mask = 1, i = 0; i < 21; i++, mask <<= 1) { in set_mem_windows()
248 * 0-3 are SDRAM chip selects but we map all RAM directly in set_mem_windows()
253 p = &s->pci[0]; in set_mem_windows()
259 (p->io_base & 0xfffff) << 16); in set_mem_windows()
262 p = &s->pci[0]; in set_mem_windows()
267 p->remap[0], (p->mem_size[0] + 1) << 16, in set_mem_windows()
268 (p->mem_base[0] & 0xfffff) << 16); in set_mem_windows()
271 p = &s->pci[0]; in set_mem_windows()
277 (p->mem_base[1] & 0xfffff) << 16); in set_mem_windows()
280 p = &s->pci[0]; in set_mem_windows()
286 (p->mem_base[2] & 0xfffff) << 16); in set_mem_windows()
289 p = &s->pci[0]; in set_mem_windows()
295 (p->mem_base[3] & 0xfffff) << 16); in set_mem_windows()
304 (p->io_base & 0xfffff) << 16); in set_mem_windows()
312 p->remap[0], (p->mem_size[0] + 1) << 16, in set_mem_windows()
313 (p->mem_base[0] & 0xfffff) << 16); in set_mem_windows()
322 (p->mem_base[1] & 0xfffff) << 16); in set_mem_windows()
331 (p->mem_base[2] & 0xfffff) << 16); in set_mem_windows()
340 (p->mem_base[3] & 0xfffff) << 16); in set_mem_windows()
348 (s->regs_base & 0xfffff) << 16, mr); in set_mem_windows()
375 uint32_t ret = 0; in mv64361_read()
382 ret = s->pci[0].io_base; in mv64361_read()
385 ret = s->pci[0].io_size; in mv64361_read()
388 ret = s->pci[0].remap[4] >> 16; in mv64361_read()
391 ret = s->pci[0].mem_base[0]; in mv64361_read()
394 ret = s->pci[0].mem_size[0]; in mv64361_read()
397 ret = (s->pci[0].remap[0] & 0xffff0000) >> 16; in mv64361_read()
400 ret = s->pci[0].remap[0] >> 32; in mv64361_read()
403 ret = s->pci[0].mem_base[1]; in mv64361_read()
406 ret = s->pci[0].mem_size[1]; in mv64361_read()
409 ret = (s->pci[0].remap[1] & 0xffff0000) >> 16; in mv64361_read()
412 ret = s->pci[0].remap[1] >> 32; in mv64361_read()
415 ret = s->pci[0].mem_base[2]; in mv64361_read()
418 ret = s->pci[0].mem_size[2]; in mv64361_read()
421 ret = (s->pci[0].remap[2] & 0xffff0000) >> 16; in mv64361_read()
424 ret = s->pci[0].remap[2] >> 32; in mv64361_read()
427 ret = s->pci[0].mem_base[3]; in mv64361_read()
430 ret = s->pci[0].mem_size[3]; in mv64361_read()
433 ret = (s->pci[0].remap[3] & 0xffff0000) >> 16; in mv64361_read()
436 ret = s->pci[0].remap[3] >> 32; in mv64361_read()
448 ret = s->pci[1].mem_base[0]; in mv64361_read()
451 ret = s->pci[1].mem_size[0]; in mv64361_read()
454 ret = (s->pci[1].remap[0] & 0xffff0000) >> 16; in mv64361_read()
457 ret = s->pci[1].remap[0] >> 32; in mv64361_read()
466 ret = (s->pci[1].remap[1] & 0xffff0000) >> 16; in mv64361_read()
478 ret = (s->pci[1].remap[2] & 0xffff0000) >> 16; in mv64361_read()
490 ret = (s->pci[1].remap[3] & 0xffff0000) >> 16; in mv64361_read()
502 ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), 0, size); in mv64361_read()
506 ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(&s->pci[0]), in mv64361_read()
510 ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(&s->pci[1]), 0, size); in mv64361_read()
538 if (!(s->main_int_cr & s->cpu0_int_mask & 0xffffffff)) { in mv64361_read()
546 ret = 0x98; in mv64361_read()
552 ret = 0x11ff0000 | (s->gpp_int_level << 10); in mv64361_read()
565 ret = 0; in mv64361_read()
575 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%" in mv64361_read()
587 if ((val & 0x3000000ULL) >> 24 != 1) { in warn_swap_bit()
598 s->pci[bus].remap[idx] &= 0xffffffff00000000ULL; in mv64361_set_pci_mem_remap()
599 s->pci[bus].remap[idx] |= (val & 0xffffULL) << 16; in mv64361_set_pci_mem_remap()
611 s->cpu_conf = val & 0xe4e3bffULL; in mv64361_write()
615 s->pci[0].io_base = val & 0x30fffffULL; in mv64361_write()
618 s->pci[0].remap[4] = (val & 0xffffULL) << 16; in mv64361_write()
622 s->pci[0].io_size = val & 0xffffULL; in mv64361_write()
625 s->pci[0].remap[4] = (val & 0xffffULL) << 16; in mv64361_write()
628 s->pci[0].mem_base[0] = val & 0x70fffffULL; in mv64361_write()
631 mv64361_set_pci_mem_remap(s, 0, 0, val, false); in mv64361_write()
635 s->pci[0].mem_size[0] = val & 0xffffULL; in mv64361_write()
639 mv64361_set_pci_mem_remap(s, 0, 0, val, in mv64361_write()
643 s->pci[0].mem_base[1] = val & 0x70fffffULL; in mv64361_write()
646 mv64361_set_pci_mem_remap(s, 0, 1, val, false); in mv64361_write()
650 s->pci[0].mem_size[1] = val & 0xffffULL; in mv64361_write()
654 mv64361_set_pci_mem_remap(s, 0, 1, val, in mv64361_write()
658 s->pci[0].mem_base[2] = val & 0x70fffffULL; in mv64361_write()
661 mv64361_set_pci_mem_remap(s, 0, 2, val, false); in mv64361_write()
665 s->pci[0].mem_size[2] = val & 0xffffULL; in mv64361_write()
669 mv64361_set_pci_mem_remap(s, 0, 2, val, in mv64361_write()
673 s->pci[0].mem_base[3] = val & 0x70fffffULL; in mv64361_write()
676 mv64361_set_pci_mem_remap(s, 0, 3, val, false); in mv64361_write()
680 s->pci[0].mem_size[3] = val & 0xffffULL; in mv64361_write()
684 mv64361_set_pci_mem_remap(s, 0, 3, val, in mv64361_write()
688 s->pci[1].io_base = val & 0x30fffffULL; in mv64361_write()
691 s->pci[1].remap[4] = (val & 0xffffULL) << 16; in mv64361_write()
695 s->pci[1].io_size = val & 0xffffULL; in mv64361_write()
698 s->pci[1].mem_base[0] = val & 0x70fffffULL; in mv64361_write()
701 mv64361_set_pci_mem_remap(s, 1, 0, val, false); in mv64361_write()
705 s->pci[1].mem_size[0] = val & 0xffffULL; in mv64361_write()
709 mv64361_set_pci_mem_remap(s, 1, 0, val, in mv64361_write()
713 s->pci[1].mem_base[1] = val & 0x70fffffULL; in mv64361_write()
720 s->pci[1].mem_size[1] = val & 0xffffULL; in mv64361_write()
728 s->pci[1].mem_base[2] = val & 0x70fffffULL; in mv64361_write()
735 s->pci[1].mem_size[2] = val & 0xffffULL; in mv64361_write()
743 s->pci[1].mem_base[3] = val & 0x70fffffULL; in mv64361_write()
750 s->pci[1].mem_size[3] = val & 0xffffULL; in mv64361_write()
758 s->regs_base = val & 0xfffffULL; in mv64361_write()
764 pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), 0, val, size); in mv64361_write()
768 pci_host_data_le_ops.write(PCI_HOST_BRIDGE(&s->pci[0]), in mv64361_write()
772 pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(&s->pci[1]), 0, val, size); in mv64361_write()
780 s->cpu0_int_mask &= 0xffffffff00000000ULL; in mv64361_write()
781 s->cpu0_int_mask |= val & 0xffffffffULL; in mv64361_write()
784 s->cpu0_int_mask &= 0xffffffffULL; in mv64361_write()
811 for (i = 0; i < 4; i++) { in mv64361_write()
812 if ((ch & 0xff << i) && !(val & 0xff << i)) { in mv64361_write()
813 mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + i, 0); in mv64361_write()
825 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%" in mv64361_write()
858 if (s->gpp_int_level && !(val & 0xff << b)) { in mv64361_gpp_irq()
859 mv64361_update_irq(opaque, MV64361_IRQ_P0_GPP0_7 + b, 0); in mv64361_gpp_irq()
869 s->base_addr_enable = 0x1fffff; in mv64361_realize()
871 TYPE_MV64361, 0x10000); in mv64361_realize()
873 for (i = 0; i < 2; i++) { in mv64361_realize()
894 set_mem_windows(s, 0x1fffff); in mv64361_reset()
895 s->cpu_conf = 0x28000ff; in mv64361_reset()
896 s->regs_base = 0x100f100; in mv64361_reset()
897 s->pci[0].io_base = 0x100f800; in mv64361_reset()
898 s->pci[0].io_size = 0xff; in mv64361_reset()
899 s->pci[0].mem_base[0] = 0x100c000; in mv64361_reset()
900 s->pci[0].mem_size[0] = 0x1fff; in mv64361_reset()
901 s->pci[0].mem_base[1] = 0x100f900; in mv64361_reset()
902 s->pci[0].mem_size[1] = 0xff; in mv64361_reset()
903 s->pci[0].mem_base[2] = 0x100f400; in mv64361_reset()
904 s->pci[0].mem_size[2] = 0x1ff; in mv64361_reset()
905 s->pci[0].mem_base[3] = 0x100f600; in mv64361_reset()
906 s->pci[0].mem_size[3] = 0x1ff; in mv64361_reset()
907 s->pci[1].io_base = 0x100fe00; in mv64361_reset()
908 s->pci[1].io_size = 0xff; in mv64361_reset()
909 s->pci[1].mem_base[0] = 0x1008000; in mv64361_reset()
910 s->pci[1].mem_size[0] = 0x3fff; in mv64361_reset()
911 s->pci[1].mem_base[1] = 0x100fd00; in mv64361_reset()
912 s->pci[1].mem_size[1] = 0xff; in mv64361_reset()
913 s->pci[1].mem_base[2] = 0x1002600; in mv64361_reset()
914 s->pci[1].mem_size[2] = 0x1ff; in mv64361_reset()
915 s->pci[1].mem_base[3] = 0x100ff80; in mv64361_reset()
916 s->pci[1].mem_size[3] = 0x7f; in mv64361_reset()
917 for (i = 0; i < 2; i++) { in mv64361_reset()
918 for (j = 0; j < 4; j++) { in mv64361_reset()
922 s->pci[0].remap[1] = 0; in mv64361_reset()
923 s->pci[1].remap[1] = 0; in mv64361_reset()
924 set_mem_windows(s, 0xfbfff); in mv64361_reset()