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/openbmc/linux/drivers/clk/qcom/
H A Dvideocc-sm8150.c27 { 249600000, 2000000000, 0 },
31 .l = 0x14,
32 .alpha = 0xD555,
33 .config_ctl_val = 0x20485699,
34 .config_ctl_hi_val = 0x00002267,
35 .config_ctl_hi1_val = 0x00000024,
36 .test_ctl_hi1_val = 0x00000020,
37 .user_ctl_val = 0x00000000,
38 .user_ctl_hi_val = 0x00000805,
39 .user_ctl_hi1_val = 0x000000D0,
[all …]
H A Dvideocc-sdm845.c29 .l = 0x10,
30 .alpha = 0xaaab,
34 .offset = 0x42c,
49 { P_BI_TCXO, 0 },
63 F(100000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
64 F(200000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
65 F(330000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
66 F(404000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
67 F(444000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
68 F(533000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
[all …]
H A Dvideocc-sc7180.c26 { 249600000, 2000000000, 0 },
30 .offset = 0x42c,
47 { P_BI_TCXO, 0 },
57 F(19200000, P_BI_TCXO, 1, 0, 0),
58 F(150000000, P_VIDEO_PLL0_OUT_MAIN, 4, 0, 0),
59 F(270000000, P_VIDEO_PLL0_OUT_MAIN, 2.5, 0, 0),
60 F(340000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
61 F(434000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
62 F(500000000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
67 .cmd_rcgr = 0x7f0,
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfpga_manager_gen5.h10 #define FPGAMGRREGS_STAT_MODE_MASK 0x7
11 #define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
18 #define FPGAMGRREGS_CTRL_EN_MASK BIT(0)
24 #define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0)
27 #define FPGAMGRREGS_MODE_FPGAOFF 0x0
28 #define FPGAMGRREGS_MODE_RESETPHASE 0x1
29 #define FPGAMGRREGS_MODE_CFGPHASE 0x2
30 #define FPGAMGRREGS_MODE_INITPHASE 0x3
31 #define FPGAMGRREGS_MODE_USERMODE 0x4
32 #define FPGAMGRREGS_MODE_UNKNOWN 0x5
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dhi3798cv200-perictrl.yaml48 reg = <0x8a20000 0x1000>;
51 ranges = <0x0 0x8a20000 0x1000>;
55 reg = <0x850 0x8>;
58 resets = <&crg 0x188 4>;
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h9 #define MMDC0 0
12 #define MMDC_MDCTL 0x0
13 #define MMDC_MDPDC 0x4
14 #define MMDC_MDOTC 0x8
15 #define MMDC_MDCFG0 0xC
16 #define MMDC_MDCFG1 0x10
17 #define MMDC_MDCFG2 0x14
18 #define MMDC_MDMISC 0x18
19 #define MMDC_MDSCR 0x1C
20 #define MMDC_MDREF 0x20
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-hi3798cv200-combphy.txt37 reg = <0x8a20000 0x1000>;
40 ranges = <0x0 0x8a20000 0x1000>;
44 reg = <0x850 0x8>;
47 resets = <&crg 0x188 4>;
53 reg = <0x858 0x8>;
56 resets = <&crg 0x188 12>;
57 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
/openbmc/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/openbmc/u-boot/board/wandboard/
H A Dspl.c27 * 0x30 == 40 Ohm
28 * 0x28 == 48 Ohm
31 #define IMX6DQ_DRIVE_STRENGTH 0x30
32 #define IMX6SDL_DRIVE_STRENGTH 0x28
33 #define IMX6QP_DRIVE_STRENGTH 0x28
44 .dram_sdba2 = 0x00000000,
74 .dram_sdba2 = 0x00000000,
97 .grp_ddr_type = 0x000c0000,
98 .grp_ddrmode_ctl = 0x00020000,
99 .grp_ddrpke = 0x00000000,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dam335x-icev2.dts29 reg = <0x80000000 0x10000000>; /* 256 MB */
32 vbat: fixedregulator@0 {
51 leds@0 {
54 led@0 {
56 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>;
107 pinctrl-0 = <&user_leds>;
109 led@0 {
152 AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */
153 AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */
154 AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */
[all …]
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra74x-mmc-iodelay.dtsi43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
47 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
48 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
54 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
55 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
56 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
57 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Dam335x-evmsk.dts30 cpu@0 {
37 reg = <0x80000000 0x10000000>; /* 256 MB */
40 vbat: fixedregulator@0 {
56 pinctrl-0 = <&wl12xx_gpio>;
61 gpio = <&gpio1 29 0>;
79 pinctrl-0 = <&user_leds_s0>;
110 gpio_buttons: gpio_buttons@0 {
115 linux,code = <0x100>;
121 linux,code = <0x101>;
127 linux,code = <0x102>;
[all …]
/openbmc/u-boot/board/freescale/mx6ullevk/
H A Dplugin.S11 ldr r1, =0x000C0000
12 str r1, [r0, #0x4B4]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x4AC]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x27C]
17 ldr r1, =0x00000030
18 str r1, [r0, #0x250]
19 str r1, [r0, #0x24C]
20 str r1, [r0, #0x490]
[all …]
/openbmc/u-boot/board/freescale/mx6sllevk/
H A Dplugin.S11 ldr r1, =0x00080000
12 str r1, [r0, #0x550]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x534]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x2AC]
17 str r1, [r0, #0x548]
18 str r1, [r0, #0x52C]
19 ldr r1, =0x00020000
20 str r1, [r0, #0x530]
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra76x-mmc-iodelay.dtsi32 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
33 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
34 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
35 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
36 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
37 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
43 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
44 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
45 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
46 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
H A Ddra74x-mmc-iodelay.dtsi35 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
36 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
37 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
38 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
39 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
40 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
46 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
47 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
48 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
49 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Drtw8822b.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
[all …]
/openbmc/linux/drivers/infiniband/hw/hns/
H A Dhns_roce_common.h53 } while (0)
108 #define ROCEE_VENDOR_ID_REG 0x0
109 #define ROCEE_VENDOR_PART_ID_REG 0x4
111 #define ROCEE_SYS_IMAGE_GUID_L_REG 0xC
112 #define ROCEE_SYS_IMAGE_GUID_H_REG 0x10
114 #define ROCEE_PORT_GID_L_0_REG 0x50
115 #define ROCEE_PORT_GID_ML_0_REG 0x54
116 #define ROCEE_PORT_GID_MH_0_REG 0x58
117 #define ROCEE_PORT_GID_H_0_REG 0x5C
119 #define ROCEE_BT_CMD_H_REG 0x204
[all …]
/openbmc/linux/Documentation/dev-tools/
H A Dkmsan.rst32 BUG: KMSAN: uninit-value in test_uninit_kmsan_check_memory+0x1be/0x380 [kmsan_test]
33 test_uninit_kmsan_check_memory+0x1be/0x380 mm/kmsan/kmsan_test.c:273
35 kunit_try_run_case+0x206/0x420 lib/kunit/test.c:374
36 kunit_generic_run_threadfn_adapter+0x6d/0xc0 lib/kunit/try-catch.c:28
37 kthread+0x721/0x850 kernel/kthread.c:327
38 ret_from_fork+0x1f/0x30 ??:?
41 do_uninit_local_array+0xfa/0x110 mm/kmsan/kmsan_test.c:260
42 test_uninit_kmsan_check_memory+0x1a2/0x380 mm/kmsan/kmsan_test.c:271
44 kunit_try_run_case+0x206/0x420 lib/kunit/test.c:374
45 kunit_generic_run_threadfn_adapter+0x6d/0xc0 lib/kunit/try-catch.c:28
[all …]
/openbmc/u-boot/board/freescale/mx7ulp_evk/
H A Dplugin.S9 ldr r2, =0x403f0000
10 ldr r3, =0x00000000
11 str r3, [r2, #0xdc]
13 ldr r2, =0x403e0000
14 ldr r3, =0x01000020
15 str r3, [r2, #0x40]
16 ldr r3, =0x01000000
17 str r3, [r2, #0x500]
18 ldr r3, =0x80808080
19 str r3, [r2, #0x50c]
[all …]
/openbmc/qemu/hw/intc/
H A Dpnv_xive_regs.h13 /* IC register offsets 0x0 - 0x400 */
14 #define CQ_SWI_CMD_HIST 0x020
15 #define CQ_SWI_CMD_POLL 0x028
16 #define CQ_SWI_CMD_BCAST 0x030
17 #define CQ_SWI_CMD_ASSIGN 0x038
18 #define CQ_SWI_CMD_BLK_UPD 0x040
19 #define CQ_SWI_RSP 0x048
20 #define CQ_CFG_PB_GEN 0x050
22 #define CQ_MSGSND 0x058
23 #define CQ_CNPM_SEL 0x078
[all …]
/openbmc/linux/sound/soc/sh/rcar/
H A Dgen.c52 RSND_REG_SET(id, offset, 0, #id)
68 return 0; in rsnd_is_accessible_reg()
90 return 0; in rsnd_mod_read()
173 memset(&regc, 0, sizeof(regc)); in _rsnd_gen_regmap_init()
198 for (i = 0; i < conf_size; i++) { in _rsnd_gen_regmap_init()
202 regf.lsb = 0; in _rsnd_gen_regmap_init()
215 return 0; in _rsnd_gen_regmap_init()
224 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE0, 0x850), in rsnd_gen4_probe()
225 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE2, 0x858), in rsnd_gen4_probe()
226 RSND_GEN_S_REG(SSI_SYS_INT_ENABLE4, 0x890), in rsnd_gen4_probe()
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.h20 #define SUN4I_BACKEND_MODCTL_REG 0x800
24 #define SUN4I_BACKEND_MODCTL_OUT_LCD0 (0 << 20)
34 #define SUN4I_BACKEND_MODCTL_DEBE_EN BIT(0)
36 #define SUN4I_BACKEND_BACKCOLOR_REG 0x804
39 #define SUN4I_BACKEND_DISSIZE_REG 0x808
40 #define SUN4I_BACKEND_DISSIZE(w, h) (((((h) - 1) & 0xffff) << 16) | \
41 (((w) - 1) & 0xffff))
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l)))
44 #define SUN4I_BACKEND_LAYSIZE(w, h) (((((h) - 1) & 0x1fff) << 16) | \
45 (((w) - 1) & 0x1fff))
[all …]
/openbmc/qemu/hw/ppc/
H A Dprep_systemio.c50 uint8_t sreset; /* 0x0092 */
51 uint8_t equipment; /* 0x080c */
52 uint8_t system_control; /* 0x081c */
53 uint8_t iomap_type; /* 0x0850 */
54 uint8_t ibm_planar_id; /* 0x0852 */
75 if ((val & PORT0092_LE_MODE) != 0) { in prep_port0092_write()
104 /* reset by port 0x4D in the SIO */
112 /* reset by port 0x4D in the SIO */
133 uint32_t val = 0; in prep_port0818_read()
161 PORT081C_L2_CACHEMISS_INHIBIT = PREP_BIT(0),
[all …]

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