xref: /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/mmdc.h (revision e8f80a5a)

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2015, Freescale Semiconductor, Inc.
 */

#ifndef __ARCH_ARM_MACH_S32V234_MMDC_H__
#define __ARCH_ARM_MACH_S32V234_MMDC_H__

#define MMDC0				0
#define MMDC1				1

#define MMDC_MDCTL			0x0
#define MMDC_MDPDC			0x4
#define MMDC_MDOTC			0x8
#define MMDC_MDCFG0			0xC
#define MMDC_MDCFG1			0x10
#define MMDC_MDCFG2			0x14
#define MMDC_MDMISC			0x18
#define MMDC_MDSCR			0x1C
#define MMDC_MDREF			0x20
#define MMDC_MDRWD			0x2C
#define MMDC_MDOR			0x30
#define MMDC_MDMRR			0x34
#define MMDC_MDCFG3LP		0x38
#define MMDC_MDMR4			0x3C
#define MMDC_MDASP			0x40
#define MMDC_MAARCR			0x400
#define MMDC_MAPSR			0x404
#define MMDC_MAEXIDR0		0x408
#define MMDC_MAEXIDR1		0x40C
#define MMDC_MADPCR0		0x410
#define MMDC_MADPCR1		0x414
#define MMDC_MADPSR0		0x418
#define MMDC_MADPSR1		0x41C
#define MMDC_MADPSR2		0x420
#define MMDC_MADPSR3		0x424
#define MMDC_MADPSR4		0x428
#define MMDC_MADPSR5		0x42C
#define MMDC_MASBS0			0x430
#define MMDC_MASBS1			0x434
#define MMDC_MAGENP			0x440
#define MMDC_MPZQHWCTRL		0x800
#define MMDC_MPWLGCR		0x808
#define MMDC_MPWLDECTRL0	0x80C
#define MMDC_MPWLDECTRL1	0x810
#define MMDC_MPWLDLST		0x814
#define MMDC_MPODTCTRL		0x818
#define MMDC_MPRDDQBY0DL	0x81C
#define MMDC_MPRDDQBY1DL	0x820
#define MMDC_MPRDDQBY2DL	0x824
#define MMDC_MPRDDQBY3DL	0x828
#define MMDC_MPDGCTRL0		0x83C
#define MMDC_MPDGCTRL1		0x840
#define MMDC_MPDGDLST0		0x844
#define MMDC_MPRDDLCTL		0x848
#define MMDC_MPRDDLST		0x84C
#define MMDC_MPWRDLCTL		0x850
#define MMDC_MPWRDLST		0x854
#define MMDC_MPZQLP2CTL		0x85C
#define MMDC_MPRDDLHWCTL	0x860
#define MMDC_MPWRDLHWCTL	0x864
#define MMDC_MPRDDLHWST0	0x868
#define MMDC_MPRDDLHWST1	0x86C
#define MMDC_MPWRDLHWST1	0x870
#define MMDC_MPWRDLHWST2	0x874
#define MMDC_MPWLHWERR		0x878
#define MMDC_MPDGHWST0		0x87C
#define MMDC_MPDGHWST1		0x880
#define MMDC_MPDGHWST2		0x884
#define MMDC_MPDGHWST3		0x888
#define MMDC_MPPDCMPR1		0x88C
#define MMDC_MPPDCMPR2		0x890
#define MMDC_MPSWDAR0		0x894
#define MMDC_MPSWDRDR0		0x898
#define MMDC_MPSWDRDR1		0x89C
#define MMDC_MPSWDRDR2		0x8A0
#define MMDC_MPSWDRDR3		0x8A4
#define MMDC_MPSWDRDR4		0x8A8
#define MMDC_MPSWDRDR5		0x8AC
#define MMDC_MPSWDRDR6		0x8B0
#define MMDC_MPSWDRDR7		0x8B4
#define MMDC_MPMUR0			0x8B8
#define MMDC_MPDCCR			0x8C0

#define MMDC_MPMUR0_FRC_MSR			(1 << 11)
#define MMDC_MPZQHWCTRL_ZQ_HW_FOR	(1 << 16)

#endif