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/openbmc/linux/Documentation/i2c/busses/
H A Dscx200_acb.rst15 By default the driver uses two base addresses 0x820 and 0x840.
16 If you want only one base address, specify the second as 0 so as to
28 The SC1100 WRAP boards are known to use base addresses 0x810 and 0x820.
32 scx200_acb.base=0x810,0x820
37 options scx200_acb base=0x810,0x820
/openbmc/linux/arch/arm/mm/
H A Dcache-tauros3.h20 #define TAUROS3_EVENT_CNT2_CFG 0x224
21 #define TAUROS3_EVENT_CNT2_VAL 0x228
22 #define TAUROS3_INV_ALL 0x780
23 #define TAUROS3_CLEAN_ALL 0x784
24 #define TAUROS3_AUX2_CTRL 0x820
/openbmc/phosphor-power/phosphor-regulators/test/
H A Dvalidate-regulators-config_tests.cpp66 "command": "0x8B",
91 "i2c_compare_bit": { "register": "0x02", "position": 3, "value": 1 }
115 "address": "0x70"
177 std::string firstLine = result.substr(0, result.find('\n')); in runToolForOutputWithCommand()
205 EXPECT_EQ(runToolForOutput(configFileName, outputMessage, errorMessage), 0); in expectFileValid()
274 configFile["rules"][0]["actions"][0]["comments"][0] = in TEST()
285 { "i2c_compare_byte": { "register": "0xA0", "value": "0x00" } }, in TEST()
286 { "i2c_compare_byte": { "register": "0xA1", "value": "0x00" } } in TEST()
290 configFile["rules"][0]["actions"].push_back(andAction); in TEST()
296 configFile["rules"][0]["actions"][1]["compare_presence"]["fru"] = in TEST()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dtoshiba,tmpv770x-pipllct.yaml43 #clock-cells = <0>;
52 reg = <0 0x24220000 0 0x820>;
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dconfig.h13 #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
20 #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
25 #define CONFIG_SYS_PAGE_SIZE 0x10000
31 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
32 #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
33 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
48 #define GICD_BASE 0x06000000
49 #define GICR_BASE 0x06100000
52 #define SMMU_BASE 0x05000000 /* GR0 Base */
69 #define CCI_MN_BASE 0x04000000
[all …]
/openbmc/linux/drivers/watchdog/
H A Dnpcm_wdt.c16 #define NPCM_WTCR 0x1C
25 #define NPCM_WTR BIT(0) /* Reset counter */
30 * 170 msec: WTCLK=01 WTIS=00 VAL= 0x400
31 * 670 msec: WTCLK=01 WTIS=01 VAL= 0x410
32 * 1360 msec: WTCLK=10 WTIS=00 VAL= 0x800
33 * 2700 msec: WTCLK=01 WTIS=10 VAL= 0x420
34 * 5360 msec: WTCLK=10 WTIS=01 VAL= 0x810
35 * 10700 msec: WTCLK=01 WTIS=11 VAL= 0x430
36 * 21600 msec: WTCLK=10 WTIS=10 VAL= 0x820
37 * 43000 msec: WTCLK=11 WTIS=00 VAL= 0xC00
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h9 #define MMDC0 0
12 #define MMDC_MDCTL 0x0
13 #define MMDC_MDPDC 0x4
14 #define MMDC_MDOTC 0x8
15 #define MMDC_MDCFG0 0xC
16 #define MMDC_MDCFG1 0x10
17 #define MMDC_MDCFG2 0x14
18 #define MMDC_MDMISC 0x18
19 #define MMDC_MDSCR 0x1C
20 #define MMDC_MDREF 0x20
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dbcm4908_enet.h5 #define ENET_CONTROL 0x000
6 #define ENET_MIB_CTRL 0x004
7 #define ENET_MIB_CTRL_CLR_MIB 0x00000001
8 #define ENET_RX_ERR_MASK 0x008
9 #define ENET_MIB_MAX_PKT_SIZE 0x00C
10 #define ENET_MIB_MAX_PKT_SIZE_VAL 0x00003fff
11 #define ENET_DIAG_OUT 0x01c
12 #define ENET_ENABLE_DROP_PKT 0x020
13 #define ENET_IRQ_ENABLE 0x024
14 #define ENET_IRQ_ENABLE_OVFL 0x00000001
[all …]
/openbmc/linux/drivers/staging/rtl8192u/
H A Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
/openbmc/linux/include/dt-bindings/pinctrl/
H A Dam33xx.h18 #define SLEWCTRL_FAST 0
30 #define PIN_OUTPUT_PULLDOWN 0
43 #define AM335X_PIN_OFFSET_MIN 0x0800U
45 #define AM335X_PIN_GPMC_AD0 0x800
46 #define AM335X_PIN_GPMC_AD1 0x804
47 #define AM335X_PIN_GPMC_AD2 0x808
48 #define AM335X_PIN_GPMC_AD3 0x80c
49 #define AM335X_PIN_GPMC_AD4 0x810
50 #define AM335X_PIN_GPMC_AD5 0x814
51 #define AM335X_PIN_GPMC_AD6 0x818
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman3-1.dtsi2 * QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
40 ranges = <0 0x500000 0xfe000>;
41 reg = <0x500000 0xfe000>;
42 interrupts = <97 2 0 0>, <16 2 1 0>;
45 fsl,qman-channel-range = <0x820 0x10>;
48 muram@0 {
50 reg = <0x0 0x60000>;
54 cell-index = <0x2>;
56 reg = <0x82000 0x1000>;
60 cell-index = <0x3>;
[all …]
/openbmc/u-boot/board/wandboard/
H A Dspl.c27 * 0x30 == 40 Ohm
28 * 0x28 == 48 Ohm
31 #define IMX6DQ_DRIVE_STRENGTH 0x30
32 #define IMX6SDL_DRIVE_STRENGTH 0x28
33 #define IMX6QP_DRIVE_STRENGTH 0x28
44 .dram_sdba2 = 0x00000000,
74 .dram_sdba2 = 0x00000000,
97 .grp_ddr_type = 0x000c0000,
98 .grp_ddrmode_ctl = 0x00020000,
99 .grp_ddrpke = 0x00000000,
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Ddino.h21 #define DINO_IAR0 0x004
22 #define DINO_IODC 0x008
23 #define DINO_IRR0 0x00C /* RO */
24 #define DINO_IAR1 0x010
25 #define DINO_IRR1 0x014 /* RO */
26 #define DINO_IMR 0x018
27 #define DINO_IPR 0x01C
28 #define DINO_TOC_ADDR 0x020
29 #define DINO_ICR 0x024
30 #define DINO_ILR 0x028 /* RO */
[all …]
/openbmc/linux/include/linux/usb/
H A Dusb338x.h19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-miphy28lp.txt56 reg = <0x9b22000 0xff>,
57 <0x9b09000 0xff>,
58 <0x9b04000 0xff>;
63 st,syscfg = <0x114 0x818 0xe0 0xec>;
71 reg = <0x9b2a000 0xff>,
72 <0x9b19000 0xff>,
73 <0x9b14000 0xff>;
78 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
87 reg = <0x8f95000 0xff>,
88 <0x8f90000 0xff>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dpinmux.h34 PMUX_PINGRP_CLK2_OUT_PW5 = (0x68 / 4),
36 PMUX_PINGRP_HDMI_INT_PN7 = (0x110 / 4),
39 PMUX_PINGRP_UART2_RXD_PC3 = (0x164 / 4),
110 PMUX_PINGRP_CAM_MCLK_PCC0 = (0x284 / 4),
149 PMUX_PINGRP_CORE_PWR_REQ = (0x324 / 4),
174 PMUX_PINGRP_SDMMC3_CLK_PA6 = (0x390 / 4),
180 PMUX_PINGRP_PEX_L0_RST_N_PDD1 = (0x3bc / 4),
183 PMUX_PINGRP_PEX_L1_RST_N_PDD5 = (0x3cc / 4),
185 PMUX_PINGRP_HDMI_CEC_PEE3 = (0x3e0 / 4),
200 PMUX_PINGRP_DP_HPD_PFF0 = (0x430 / 4),
[all …]
/openbmc/u-boot/board/freescale/mx6ullevk/
H A Dplugin.S11 ldr r1, =0x000C0000
12 str r1, [r0, #0x4B4]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x4AC]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x27C]
17 ldr r1, =0x00000030
18 str r1, [r0, #0x250]
19 str r1, [r0, #0x24C]
20 str r1, [r0, #0x490]
[all …]
/openbmc/u-boot/board/freescale/mx6sllevk/
H A Dplugin.S11 ldr r1, =0x00080000
12 str r1, [r0, #0x550]
13 ldr r1, =0x00000000
14 str r1, [r0, #0x534]
15 ldr r1, =0x00000030
16 str r1, [r0, #0x2AC]
17 str r1, [r0, #0x548]
18 str r1, [r0, #0x52C]
19 ldr r1, =0x00020000
20 str r1, [r0, #0x530]
[all …]
/openbmc/linux/drivers/net/wireless/rsi/
H A Drsi_hal.h45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/msm/
H A Dqcom,sm6375-mdss.yaml44 "^display-controller@[0-9a-f]+$":
50 "^dsi@[0-9a-f]+$":
58 "^phy@[0-9a-f]+$":
76 reg = <0x05e00000 0x1000>;
90 iommus = <&apps_smmu 0x820 0x2>;
97 reg = <0x05e01000 0x8e030>,
98 <0x05eb0000 0x2008>;
123 interrupts = <0>;
127 #size-cells = <0>;
129 port@0 {
[all …]
/openbmc/linux/drivers/soc/imx/
H A Dsoc-imx.c16 #define IIM_UID 0x820
18 #define OCOTP_UID_H 0x420
19 #define OCOTP_UID_L 0x410
21 #define OCOTP_ULP_UID_1 0x4b0
22 #define OCOTP_ULP_UID_2 0x4c0
23 #define OCOTP_ULP_UID_3 0x4d0
24 #define OCOTP_ULP_UID_4 0x4e0
34 u64 soc_uid = 0; in imx_soc_device_init()
41 return 0; in imx_soc_device_init()
155 soc_uid = val & 0xffff; in imx_soc_device_init()
[all …]
/openbmc/linux/drivers/reset/sti/
H A Dreset-stih407.c25 /* Powerdown requests control 0 */
26 #define SYSCFG_5000 0x0
27 #define SYSSTAT_5500 0x7d0
29 #define SYSCFG_5001 0x4
30 #define SYSSTAT_5501 0x7d4
33 #define SYSCFG_4032 0x80
34 #define SYSSTAT_4520 0x820
35 #define SYSCFG_4002 0x8
39 [STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
46 [STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
[all …]
/openbmc/linux/drivers/reset/hisilicon/
H A Dhi6220_reset.c22 #define PERIPH_ASSERT_OFFSET 0x300
23 #define PERIPH_DEASSERT_OFFSET 0x304
24 #define PERIPH_MAX_INDEX 0x509
26 #define SC_MEDIA_RSTEN 0x052C
27 #define SC_MEDIA_RSTDIS 0x0530
49 u32 offset = idx & 0xff; in hi6220_peripheral_assert()
50 u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_assert()
61 u32 offset = idx & 0xff; in hi6220_peripheral_deassert()
62 u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10; in hi6220_peripheral_deassert()
95 #define AO_SCTRL_SC_PW_CLKEN0 0x800
[all …]
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME129 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
130 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
131 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
132 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
133 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
134 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
135 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
136 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
137 0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
138 0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
[all …]
/openbmc/u-boot/board/freescale/t208xqds/
H A DREADME71 - Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
124 0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
125 0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
126 0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
127 0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
128 0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
129 0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
130 0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
131 0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
132 0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
[all …]

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