Home
last modified time | relevance | path

Searched +full:0 +full:x7c000000 (Results 1 – 25 of 56) sorted by relevance

123

/openbmc/u-boot/configs/
H A Dtbs2910_defconfig4 CONFIG_SYS_TEXT_BASE=0x17800000
10 CONFIG_PRE_CON_BUF_ADDR=0x7c000000
53 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
54 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
/openbmc/linux/arch/powerpc/platforms/embedded6xx/
H A Dholly.c43 #define HOLLY_PCI_CFG_PHYS 0x7c000000
48 if (bus == 0 && PCI_SLOT(devfn) == 0) in holly_exclude_device()
64 lut_addr = 0x900; in holly_remap_bridge()
65 for (i = 0; i < 31; i++) { in holly_remap_bridge()
66 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000201); in holly_remap_bridge()
68 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0); in holly_remap_bridge()
73 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x00000241); in holly_remap_bridge()
75 tsi108_write_reg(TSI108_PB_OFFSET + lut_addr, 0x0); in holly_remap_bridge()
78 tsi108_write_reg(TSI108_PCI_PFAB_IO_UPPER, 0x0); in holly_remap_bridge()
79 tsi108_write_reg(TSI108_PCI_PFAB_IO, 0x1); in holly_remap_bridge()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dstarfive,jh7110-mmc.yaml66 reg = <0x16010000 0x10000>;
75 data-addr = <0>;
76 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
/openbmc/linux/arch/microblaze/include/asm/
H A Dpvr.h13 #define PVR_MSR_BIT 0x400
22 #define PVR0_PVR_FULL_MASK 0x80000000
23 #define PVR0_USE_BARREL_MASK 0x40000000
24 #define PVR0_USE_DIV_MASK 0x20000000
25 #define PVR0_USE_HW_MUL_MASK 0x10000000
26 #define PVR0_USE_FPU_MASK 0x08000000
27 #define PVR0_USE_EXC_MASK 0x04000000
28 #define PVR0_USE_ICACHE_MASK 0x02000000
29 #define PVR0_USE_DCACHE_MASK 0x01000000
30 #define PVR0_USE_MMU 0x00800000
[all …]
/openbmc/linux/arch/arm/mach-footbridge/include/mach/
H A Dhardware.h13 * 0xff800000 0x40000000 1MB X-Bus
14 * 0xff000000 0x7c000000 1MB PCI I/O space
15 * 0xfe000000 0x42000000 1MB CSR
16 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
17 * 0xfc000000 0x79000000 1MB PCI IACK/special space
18 * 0xfb000000 0x7a000000 16MB PCI Config type 1
19 * 0xfa000000 0x7b000000 16MB PCI Config type 0
20 * 0xf9000000 0x50000000 1MB Cache flush
21 * 0xf0000000 0x80000000 16MB ISA memory
24 #define XBUS_SIZE 0x00100000
[all …]
/openbmc/linux/arch/arm/mach-s3c/
H A Dmap-s3c64xx.h22 #define S3C64XX_PA_XM0CSN0 (0x10000000)
23 #define S3C64XX_PA_XM0CSN1 (0x18000000)
24 #define S3C64XX_PA_XM0CSN2 (0x20000000)
25 #define S3C64XX_PA_XM0CSN3 (0x28000000)
26 #define S3C64XX_PA_XM0CSN4 (0x30000000)
27 #define S3C64XX_PA_XM0CSN5 (0x38000000)
30 #define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
31 #define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
35 #define S3C_PA_UART (0x7F005000)
36 #define S3C_PA_UART0 (S3C_PA_UART + 0x00)
[all …]
/openbmc/qemu/target/microblaze/
H A Dcpu.h42 #define MB_CPU_IRQ 0
47 #define SR_PC 0
52 #define SR_BTR 0xb
53 #define SR_EDR 0xd
56 #define MSR_BE (1<<0) /* 0x001 */
57 #define MSR_IE (1<<1) /* 0x002 */
58 #define MSR_C (1<<2) /* 0x004 */
59 #define MSR_BIP (1<<3) /* 0x008 */
60 #define MSR_FSL (1<<4) /* 0x010 */
61 #define MSR_ICE (1<<5) /* 0x020 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/edac/
H A Dapm-xgene-edac.txt53 reg = <0x0 0x7e200000 0x0 0x1000>;
58 reg = <0x0 0x7e700000 0x0 0x1000>;
63 reg = <0x0 0x7e720000 0x0 0x1000>;
68 reg = <0x0 0x1054a000 0x0 0x20>;
73 reg = <0x0 0x7e000000 0x0 0x10>;
86 reg = <0x0 0x78800000 0x0 0x100>;
87 interrupts = <0x0 0x20 0x4>,
88 <0x0 0x21 0x4>,
89 <0x0 0x27 0x4>;
93 reg = <0x0 0x7e800000 0x0 0x1000>;
[all …]
/openbmc/linux/arch/sh/include/asm/
H A Dprocessor_32.h19 #define CCN_PVR 0xff000030
20 #define CCN_CVR 0xff000040
21 #define CCN_PRR 0xff000044
26 * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff
28 #define TASK_SIZE 0x7c000000UL
48 #define SR_DSP 0x00001000
49 #define SR_IMASK 0x000000f0
50 #define SR_FD 0x00008000
51 #define SR_MD 0x40000000
53 #define SR_USER_MASK 0x00000303 // M, Q, S, T bits
[all …]
/openbmc/linux/arch/arm/include/asm/hardware/
H A Ddec21285.h9 #define DC21285_PCI_IACK 0x79000000
10 #define DC21285_ARMCSR_BASE 0x42000000
11 #define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
12 #define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
13 #define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
14 #define DC21285_FLASH 0x41000000
15 #define DC21285_PCI_IO 0x7c000000
16 #define DC21285_PCI_MEM 0x80000000
26 * The footbridge is programmed to expose the system RAM at 0xe0000000.
27 * The requirement is that the RAM isn't placed at bus address 0, which
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30
36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_8_2_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
H A Dgmc_7_1_sh_mask.h27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1
28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0
29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2
30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1
31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4
32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2
33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8
34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3
35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10
36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dpci.c16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
20 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
63 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
64 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
65 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
66 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
67 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ in __mt7921_reg_addr()
[all …]
/openbmc/qemu/include/libdecnumber/
H A DdecNumberLocal.h50 /* 1=little-endian, 0=big-endian */
52 #define DECLITEND 0
58 #define DECUSE64 1 /* 1=use int64s, 0=int32 & smaller only */
60 /* Conditional check flags -- set these to 0 for best performance */
61 #define DECCHECK 0 /* 1 to enable robust checking */
62 #define DECALLOC 0 /* 1 to enable memory accounting */
63 #define DECTRACE 0 /* 1 to trace certain internals, etc. */
92 #define DECNOINT 0 /* 1 to check no internal use of 'int' */
103 extern const uShort DPD2BIN[1024]; /* DPD -> 0-999 */
104 extern const uShort BIN2DPD[1000]; /* 0-999 -> DPD */
[all …]
/openbmc/qemu/hw/arm/
H A Dbcm2838_peripherals.c15 #define CLOCK_ISP_OFFSET 0xc11000
16 #define CLOCK_ISP_SIZE 0x100
19 #define BCM2838_VC_PERI_LOW_BASE 0x7c000000
22 #define BCM2835_SDHC_CAPAREG 0x52134b4
76 "bcm2838-peripherals", &s->peri_low_mr, 0, in bcm2838_peripherals_realize()
95 0)); in bcm2838_peripherals_realize()
103 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc2), 0, in bcm2838_peripherals_realize()
104 qdev_get_gpio_in(mmc_irq_orgate, 0)); in bcm2838_peripherals_realize()
106 sysbus_connect_irq(SYS_BUS_DEVICE(&s_base->sdhci), 0, in bcm2838_peripherals_realize()
110 qdev_connect_gpio_out(mmc_irq_orgate, 0, in bcm2838_peripherals_realize()
[all …]
/openbmc/u-boot/post/lib_powerpc/
H A Dcpu_asm.h9 #define BIT_C 0x00000001
11 #define OP_BLR 0x4e800020
12 #define OP_EXTSB 0x7c000774
13 #define OP_EXTSH 0x7c000734
14 #define OP_NEG 0x7c0000d0
15 #define OP_CNTLZW 0x7c000034
16 #define OP_ADD 0x7c000214
17 #define OP_ADDC 0x7c000014
18 #define OP_ADDME 0x7c0001d4
19 #define OP_ADDZE 0x7c000194
[all …]
/openbmc/linux/include/linux/mfd/
H A Dezx-pcap.h40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/ls102xa/
H A Dfsl_epu.c13 {EPGCR, 0},
15 {EPECR0 + EPECR_STRIDE * 0, 0},
16 {EPECR0 + EPECR_STRIDE * 1, 0},
17 {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
18 {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
19 {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
20 {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
21 {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
22 {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
23 {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
[all …]
/openbmc/qemu/hw/misc/
H A Deccmemctl.c35 * MCC (version 0, implementation 0) SS-600MP
36 * EMC (version 0, implementation 1) SS-10
37 * SMC (version 0, implementation 2) SS-10SX and SS-20
44 #define ECC_MCC 0x00000000
45 #define ECC_EMC 0x10000000
46 #define ECC_SMC 0x20000000
49 #define ECC_MER 0 /* Memory Enable Register */
53 #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */
56 #define ECC_ECR0 7 /* Event Count Register 0 */
60 #define ECC_MER_EE 0x00000001 /* Enable ECC checking */
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2711.dtsi21 #clock-cells = <0>;
28 #clock-cells = <0>;
41 ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
42 <0x7c000000 0x0 0xfc000000 0x02000000>,
43 <0x40000000 0x0 0xff800000 0x00800000>;
45 dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>;
53 reg = <0x40000000 0x100>;
60 reg = <0x40041000 0x1000>,
61 <0x40042000 0x2000>,
62 <0x40044000 0x2000>,
[all …]
/openbmc/qemu/contrib/plugins/
H A Dhowvec.c25 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
62 * 31..28 27..24 23..20 19..16 15..12 11..8 7..4 3..0
66 { " UDEF", "udef", 0xffff0000, 0x00000000, COUNT_NONE},
67 { " SVE", "sve", 0x1e000000, 0x04000000, COUNT_CLASS},
68 { "Reserved", "res", 0x1e000000, 0x00000000, COUNT_CLASS},
70 { " PCrel addr", "pcrel", 0x1f000000, 0x10000000, COUNT_CLASS},
71 { " Add/Sub (imm,tags)", "asit", 0x1f800000, 0x11800000, COUNT_CLASS},
72 { " Add/Sub (imm)", "asi", 0x1f000000, 0x11000000, COUNT_CLASS},
73 { " Logical (imm)", "logi", 0x1f800000, 0x12000000, COUNT_CLASS},
74 { " Move Wide (imm)", "movwi", 0x1f800000, 0x12800000, COUNT_CLASS},
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch3.h12 #define CONFIG_SYS_IMMR 0x01000000
13 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
14 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
15 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
16 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
17 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
21 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
23 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
24 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
[all …]
/openbmc/linux/arch/arm/kernel/
H A Dhead.S30 * the least significant 16 bits to be 0x8000, but we could probably
31 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
34 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
35 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
40 #define PG_DIR_SIZE 0x5000
43 #define PG_DIR_SIZE 0x4000
60 .long 0
61 .long 0
63 .long 0
64 .long 0
[all …]

123