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/openbmc/qemu/tests/migration/i386/
H A Da-b-bootblock.S14 #define ACPI_ENABLE 0xf1
15 #define ACPI_PORT_SMI_CMD 0xb2
16 #define ACPI_PM_BASE 0x600
19 #define ACPI_SCI_ENABLE 0x0001
20 #define ACPI_SLEEP_TYPE 0x0400
21 #define ACPI_SLEEP_ENABLE 0x2000
31 .org 0x7c00
36 start: # at 0x7c00 ?
41 data32 ljmp $8,$0x7c20
43 .org 0x7c20
[all …]
/openbmc/linux/drivers/hwmon/pmbus/
H A Dltc2978.c33 #define LTC2978_MFR_VOUT_PEAK 0xdd
34 #define LTC2978_MFR_VIN_PEAK 0xde
35 #define LTC2978_MFR_TEMPERATURE_PEAK 0xdf
36 #define LTC2978_MFR_SPECIAL_ID 0xe7 /* Undocumented on LTC3882 */
37 #define LTC2978_MFR_COMMON 0xef
40 #define LTC2978_MFR_VOUT_MIN 0xfb
41 #define LTC2978_MFR_VIN_MIN 0xfc
42 #define LTC2978_MFR_TEMPERATURE_MIN 0xfd
45 #define LTC2974_MFR_IOUT_PEAK 0xd7
46 #define LTC2974_MFR_IOUT_MIN 0xd8
[all …]
/openbmc/qemu/tests/tcg/aarch64/
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
/openbmc/qemu/tests/tcg/tricore/asm/
H A Dtest_ftohp.S5 TEST_D_D(ftohp, 1, 0xffff, 0xffffffff)
6 TEST_D_D(ftohp, 2, 0xfc00, 0xff800000)
7 TEST_D_D(ftohp, 3, 0x7c00, 0x7f800000)
8 TEST_D_D(ftohp, 4, 0x0, 0x0)
9 TEST_D_D(ftohp, 5, 0x5, 0x34a43580)
11 #TEST_D_D_PSW(ftohp, 6, 0x400, 0x8c000b80, 0x387fee74)
/openbmc/linux/Documentation/devicetree/bindings/arm/amlogic/
H A Dassist.txt16 reg = <0x7c00 0x200>;
/openbmc/qemu/tests/tcg/arm/
H A Dfcvt.ref4 00 SINGLE: -nan / 0xffa00000 (0 => OK)
5 00 HALF: 0xff00 (0x1 => INVALID)
6 01 SINGLE: -nan / 0xffc00000 (0 => OK)
7 01 HALF: 0xfe00 (0 => OK)
8 02 SINGLE: -inf / 0xff800000 (0 => OK)
9 02 HALF: 0xfc00 (0 => OK)
10 03 SINGLE: -3.40282346638528859812e+38 / 0xff7fffff (0 => OK)
11 03 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
12 04 SINGLE: -1.11100004769645909791e+31 / 0xf30c3a59 (0 => OK)
13 04 HALF: 0xfc00 (0x14 => OVERFLOW INEXACT )
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A Dtsi108.h18 #define TSI108_REG_SIZE (0x10000)
21 #define TSI108_HLP_SIZE 0x1000
22 #define TSI108_PCI_SIZE 0x1000
23 #define TSI108_CLK_SIZE 0x1000
24 #define TSI108_PB_SIZE 0x1000
25 #define TSI108_SD_SIZE 0x1000
26 #define TSI108_DMA_SIZE 0x1000
27 #define TSI108_ETH_SIZE 0x1000
28 #define TSI108_I2C_SIZE 0x400
29 #define TSI108_MPIC_SIZE 0x400
[all …]
/openbmc/u-boot/board/renesas/ap325rxa/
H A Dap325rxa.c13 #define PRPRICR5 0xFF800048 /* LMB */
14 #define PRPRICR5_D 0x2a
17 #define FPGA_NAND_CTL 0xB410020C
18 #define FPGA_NAND_RST 0x0008
19 #define FPGA_NAND_INIT 0x0000
23 #define PACR_D 0x0000
24 #define PBCR_D 0x0000
25 #define PCCR_D 0x1000
26 #define PDCR_D 0x0000
27 #define PECR_D 0x0410
[all …]
H A Dcpld-ap325rxa.c29 #define SCIF_BASE 0xffe00000 /* SCIF0 */
30 #define SCSMR (vu_short *)(SCIF_BASE + 0x00)
31 #define SCBRR (vu_char *)(SCIF_BASE + 0x04)
32 #define SCSCR (vu_short *)(SCIF_BASE + 0x08)
33 #define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
34 #define SC_SR (vu_short *)(SCIF_BASE + 0x10)
35 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
36 #define RFCR (vu_long *)0xFE400020
38 #define SCSCR_INIT 0x0038
39 #define SCSCR_CLR 0x0000
[all …]
/openbmc/linux/drivers/net/ethernet/ezchip/
H A Dnps_enet.h10 #define NPS_ENET_NAPI_POLL_WEIGHT 0x2
11 #define NPS_ENET_MAX_FRAME_LENGTH 0x3FFF
12 #define NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR 0x7
13 #define NPS_ENET_GE_MAC_CFG_0_RX_IFG 0x5
14 #define NPS_ENET_GE_MAC_CFG_0_TX_IFG 0xC
15 #define NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN 0x7
16 #define NPS_ENET_GE_MAC_CFG_2_STAT_EN 0x3
17 #define NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH 0x14
18 #define NPS_ENET_GE_MAC_CFG_3_MAX_LEN 0x3FFC
20 #define NPS_ENET_DISABLE 0
[all …]
/openbmc/linux/arch/mips/include/asm/sgi/
H A Dhpc3.h22 #define HPCDMA_EOX 0x80000000 /* last desc in chain for tx */
23 #define HPCDMA_EOR 0x80000000 /* last desc in chain for rx */
24 #define HPCDMA_EOXP 0x40000000 /* end of packet for tx */
25 #define HPCDMA_EORP 0x40000000 /* end of packet for rx */
26 #define HPCDMA_XIE 0x20000000 /* irq generated when at end of this desc */
27 #define HPCDMA_XIU 0x01000000 /* Tx buffer in use by CPU. */
28 #define HPCDMA_EIPC 0x00ff0000 /* SEEQ ethernet special xternal bytecount */
29 #define HPCDMA_ETXD 0x00008000 /* set to one by HPC when packet tx'd */
30 #define HPCDMA_OWN 0x00004000 /* Denotes ring buffer ownership on rx */
31 #define HPCDMA_BCNT 0x00003fff /* size in bytes of this dma buffer */
[all …]
/openbmc/linux/drivers/gpu/drm/tests/
H A Ddrm_format_helper_test.c97 .clip = DRM_RECT_INIT(0, 0, 1, 1),
98 .xrgb8888 = { 0x01FF0000 },
100 .dst_pitch = 0,
101 .expected = { 0x4C },
104 .dst_pitch = 0,
105 .expected = { 0xE0 },
108 .dst_pitch = 0,
109 .expected = { 0xF800 },
110 .expected_swab = { 0x00F8 },
113 .dst_pitch = 0,
[all …]
/openbmc/qemu/tests/tcg/multiarch/libs/
H A Dfloat_helpers.c27 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
37 0xffff, /* -NaN / AHP -Max */
38 0xfcff, /* -NaN / AHP */
39 0xfc01, /* -NaN / AHP */
40 0xfc00, /* -Inf */
41 0xfbff, /* -Max */
42 0xc000, /* -2 */
43 0xbc00, /* -1 */
44 0x8001, /* -MIN subnormal */
45 0x8000, /* -0 */
[all …]
/openbmc/linux/drivers/media/dvb-frontends/
H A Dnxt200x.c33 #define CRC_CCIT_MASK 0x1021
56 #define dprintk(args...) do { if (debug) pr_debug(args); } while (0)
61 struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = len }; in i2c_writebytes()
64 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", in i2c_writebytes()
68 return 0; in i2c_writebytes()
77 pr_warn("%s: i2c read error (addr 0x%02x, err == %i)\n", in i2c_readbytes()
81 return 0; in i2c_readbytes()
89 …struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf2, .len = len +… in nxt200x_writebytes()
97 buf2[0] = reg; in nxt200x_writebytes()
101 pr_warn("%s: i2c write error (addr 0x%02x, err == %i)\n", in nxt200x_writebytes()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.txt47 Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
71 0x0 - MC portals
72 0x1 - QBMAN portals
99 have a value of 0.
154 stream-match-mask = <0x7C00>;
170 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
171 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
180 * Region type 0x0 - MC portals
181 * Region type 0x1 - QBMAN portals
183 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dbmi.h60 BMI_NO_COMMAND = 0,
83 #define BMI_PARAM_GET_EEPROM_BOARD_ID 0x10
84 #define BMI_PARAM_GET_FLASH_BOARD_ID 0x8000
85 #define BMI_PARAM_FLASH_SECTION_ALL 0x10000
88 #define BMI_PARAM_GET_EXT_BOARD_ID 0x40000
89 #define ATH10K_BMI_EXT_BOARD_ID_SUPPORT 0x40000
91 #define ATH10K_BMI_BOARD_ID_FROM_OTP_MASK 0x7c00
94 #define ATH10K_BMI_CHIP_ID_FROM_OTP_MASK 0x18000
97 #define ATH10K_BMI_BOARD_ID_STATUS_MASK 0xff
98 #define ATH10K_BMI_EBOARD_ID_STATUS_MASK 0xff
[all …]
/openbmc/qemu/tests/qtest/
H A Dboot-sector.c17 #define LOW(x) ((x) & 0xff)
20 #define SIGNATURE 0xdead
21 #define SIGNATURE_OFFSET 0x10
22 #define BOOT_SECTOR_ADDRESS 0x7c00
38 [0x00] = 0xb8,
39 [0x01] = 0x00,
40 [0x02] = 0x00,
42 [0x03] = 0x8e,
43 [0x04] = 0xd8,
45 /* 7c05: mov $0xdead,%ax */
[all …]
/openbmc/linux/arch/mips/rb532/
H A Dirq.c61 .mask = 0x0000efff,
62 .base_addr = (u32 *) KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET)},
64 .mask = 0x00001fff,
67 .mask = 0x00000007,
70 .mask = 0x0003ffff,
73 .mask = 0xffffffff,
93 int ipnum = 0x100 << ip; in enable_local_irq()
100 int ipnum = 0x100 << ip; in disable_local_irq()
107 int ipnum = 0x100 << ip; in ack_local_irq()
118 if (ip < 0) in rb532_enable_irq()
[all …]
/openbmc/linux/drivers/staging/media/meson/vdec/
H A Dcodec_hevc_common.c13 #define MMU_COMPRESS_HEADER_SIZE 0x48000
14 #define MMU_MAP_SIZE 0x4800
17 0x0401, 0x8401, 0x0800, 0x0402,
18 0x9002, 0x1423, 0x8CC3, 0x1423,
19 0x8804, 0x9825, 0x0800, 0x04FE,
20 0x8406, 0x8411, 0x1800, 0x8408,
21 0x8409, 0x8C2A, 0x9C2B, 0x1C00,
22 0x840F, 0x8407, 0x8000, 0x8408,
23 0x2000, 0xA800, 0x8410, 0x04DE,
24 0x840C, 0x840D, 0xAC00, 0xA000,
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_mme_ctrl_lo_masks.h24 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0
25 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F
27 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20
29 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40
31 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180
33 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00
35 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000
37 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000
39 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000
41 #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpsoc_global_conf_masks.h23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF
39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dpsoc_global_conf_masks.h23 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0
24 #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF
27 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0
28 #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1
31 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0
32 #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1
35 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0
36 #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF
39 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0
40 #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF
[all …]
/openbmc/linux/arch/arm/boot/dts/amlogic/
H A Dmeson.dtsi28 reg = <0xc1100000 0x200000>;
31 ranges = <0x0 0xc1100000 0x200000>;
37 reg = <0x4000 0x400>;
44 reg = <0x5400 0x2ac>;
53 reg = <0x7c00 0x200>;
58 reg = <0x8100 0x8>;
63 reg = <0x84c0 0x18>;
71 reg = <0x84dc 0x18>;
78 reg = <0x8500 0x20>;
81 #size-cells = <0>;
[all …]
/openbmc/linux/include/video/
H A Dgbe.h20 uint32_t _pad0[0x010000/4 - 8];
29 volatile uint32_t vt_intr01; /* intr 0,1 y coords */
41 uint32_t _pad1[0xffb0/4];
42 volatile uint32_t ovr_width_tile;/*overlay plane ctrl 0 */
45 uint32_t _pad2[0xfff4/4];
46 volatile uint32_t frm_size_tile;/* normal plane ctrl 0 */
50 uint32_t _pad3[0xfff0/4];
53 uint32_t _pad4[0x7ff8/4];
55 uint32_t _pad5[0x7f80/4];
57 uint32_t _pad6[0x2000/4];
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Devergreen_reg.h28 #define TN_SMC_IND_INDEX_0 0x200
29 #define TN_SMC_IND_DATA_0 0x204
32 #define EVERGREEN_PIF_PHY0_INDEX 0x8
33 #define EVERGREEN_PIF_PHY0_DATA 0xc
34 #define EVERGREEN_PIF_PHY1_INDEX 0x10
35 #define EVERGREEN_PIF_PHY1_DATA 0x14
36 #define EVERGREEN_MM_INDEX_HI 0x18
38 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS 0x310
39 #define EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH 0x324
40 #define EVERGREEN_D3VGA_CONTROL 0x3e0
[all …]

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