Lines Matching +full:0 +full:x7c00
29 #define SCIF_BASE 0xffe00000 /* SCIF0 */
30 #define SCSMR (vu_short *)(SCIF_BASE + 0x00)
31 #define SCBRR (vu_char *)(SCIF_BASE + 0x04)
32 #define SCSCR (vu_short *)(SCIF_BASE + 0x08)
33 #define SC_TDR (vu_char *)(SCIF_BASE + 0x0C)
34 #define SC_SR (vu_short *)(SCIF_BASE + 0x10)
35 #define SCFCR (vu_short *)(SCIF_BASE + 0x18)
36 #define RFCR (vu_long *)0xFE400020
38 #define SCSCR_INIT 0x0038
39 #define SCSCR_CLR 0x0000
40 #define SCFCR_INIT 0x0006
41 #define SCSMR_INIT 0x0080
42 #define RFCR_CLR 0xA400
43 #define SCI_TD_E 0x0020
44 #define SCI_TDRE_CLEAR 0x00df
53 #define CPLD_PFC_ADR ((vu_short *)0xA4050112)
55 #define CPLD_PROG_ADR ((vu_char *)0xA4050132)
56 #define CPLD_PROG_DAT 0x80
59 #define CPLD_INIT_ADR ((vu_char *)0xA4050132)
60 #define CPLD_INIT_DAT 0x40
61 #define CPLD_DONE_ADR ((vu_char *)0xA4050132)
62 #define CPLD_DONE_DAT 0x20
65 #define CPLD_NOMAL_START 0xA0A80000
66 #define CPLD_SAFE_START 0xA0AC0000
67 #define MODE_SW (vu_char *)0xA405012A
83 *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ in init_cpld_loader()
84 /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ in init_cpld_loader()
107 int c = 0; in delay()
108 for (i = 0; i < 200; i++) { in delay()
109 c = *(volatile int *)0xa0000000; in delay()
150 while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) in slave_serial()
156 for (i = 0; i < CPLD_DATA_SIZE; i++) in slave_serial()
192 *((vu_short *)HIZCRB) = 0x0000; in init_cpld()
193 *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ in init_cpld()