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12

/openbmc/u-boot/arch/arm/mach-bcm283x/include/mach/
H A Dwdog.h10 #define BCM2835_WDOG_PHYSADDR 0x3f100000
12 #define BCM2835_WDOG_PHYSADDR 0x20100000
22 #define BCM2835_WDOG_PASSWORD 0x5a000000
24 #define BCM2835_WDOG_RSTC_WRCFG_MASK 0x00000030
25 #define BCM2835_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020
27 #define BCM2835_WDOG_WDOG_TIMEOUT_MASK 0x0000ffff
/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_eefc.h24 #define AT91_EEFC_FMR_FWS_MASK 0x00000f00
25 #define AT91_EEFC_FMR_FRDY_BIT 0x00000001
27 #define AT91_EEFC_FCR_KEY 0x5a000000
28 #define AT91_EEFC_FCR_FARG_MASK 0x00ffff00
30 #define AT91_EEFC_FCR_FCMD_GETD 0x0
31 #define AT91_EEFC_FCR_FCMD_WP 0x1
32 #define AT91_EEFC_FCR_FCMD_WPL 0x2
33 #define AT91_EEFC_FCR_FCMD_EWP 0x3
34 #define AT91_EEFC_FCR_FCMD_EWPL 0x4
35 #define AT91_EEFC_FCR_FCMD_EA 0x5
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157.dtsi13 reg = <0x59000000 0x800>;
22 reg = <0x5a000000 0x800>;
32 #size-cells = <0>;
34 port@0 {
35 reg = <0>;
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dsocionext,uniphier-mio-dmac.yaml52 // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a
57 reg = <0x5a000000 0x1000>;
58 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
59 <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-dma.dtsi14 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
18 #clock-cells = <0>;
25 reg = <0x5a000000 0x10000>;
27 #size-cells = <0>;
41 reg = <0x5a010000 0x10000>;
43 #size-cells = <0>;
57 reg = <0x5a020000 0x10000>;
59 #size-cells = <0>;
73 reg = <0x5a030000 0x10000>;
75 #size-cells = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Dst,stm32-dsi.yaml55 port@0:
93 reg = <0x5a000000 0x800>;
101 #size-cells = <0>;
105 #size-cells = <0>;
107 port@0 {
108 reg = <0>;
122 panel@0 {
124 reg = <0>;
/openbmc/qemu/hw/misc/
H A Dbcm2835_powermgt.c18 #define PASSWORD 0x5a000000
19 #define PASSWORD_MASK 0xff000000
21 #define R_RSTC 0x1c
22 #define V_RSTC_RESET 0x20
23 #define R_RSTS 0x20
24 #define V_RSTS_POWEROFF 0x555 /* Linux uses partition 63 to indicate halt. */
25 #define R_WDOG 0x24
31 uint32_t res = 0; in bcm2835_powermgt_read()
46 "bcm2835_powermgt_read: Unknown offset 0x%08"HWADDR_PRIx in bcm2835_powermgt_read()
48 res = 0; in bcm2835_powermgt_read()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml36 # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
42 minimum: 0
43 maximum: 0x1f
48 minimum: 0
49 maximum: 0x1f
54 minimum: 0
55 maximum: 0x1f
60 minimum: 0
61 maximum: 0x1f
66 minimum: 0
[all …]
/openbmc/linux/crypto/
H A Dmichael_mic.c30 return ((val & 0x00ff00ff) << 8) | ((val & 0xff00ff00) >> 8); in xswap()
44 } while (0)
51 mctx->pending_len = 0; in michael_init()
55 return 0; in michael_init()
74 return 0; in michael_update()
78 mctx->pending_len = 0; in michael_update()
88 if (len > 0) { in michael_update()
93 return 0; in michael_update()
102 /* Last block and padding (0x5a, 4..7 x 0) */ in michael_final()
104 case 0: in michael_final()
[all …]
/openbmc/linux/drivers/watchdog/
H A Dbcm2835_wdt.c23 #define PM_RSTC 0x1c
24 #define PM_RSTS 0x20
25 #define PM_WDOG 0x24
27 #define PM_PASSWORD 0x5a000000
29 #define PM_WDOG_TIME_SET 0x000fffff
30 #define PM_RSTC_WRCFG_CLR 0xffffffcf
31 #define PM_RSTS_HADWRH_SET 0x00000040
32 #define PM_RSTC_WRCFG_SET 0x00000030
33 #define PM_RSTC_WRCFG_FULL_RESET 0x00000020
34 #define PM_RSTC_RESET 0x00000102
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dcs35l45.h20 #define CS35L45_DEVID 0x00000000
21 #define CS35L45_REVID 0x00000004
22 #define CS35L45_RELID 0x0000000C
23 #define CS35L45_OTPID 0x00000010
24 #define CS35L45_SFT_RESET 0x00000020
25 #define CS35L45_GLOBAL_ENABLES 0x00002014
26 #define CS35L45_BLOCK_ENABLES 0x00002018
27 #define CS35L45_BLOCK_ENABLES2 0x0000201C
28 #define CS35L45_ERROR_RELEASE 0x00002034
29 #define CS35L45_SYNC_GPIO1 0x00002430
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap4.dtsi40 #size-cells = <0>;
42 cpu@0 {
46 reg = <0x0>;
57 reg = <0x1>;
67 reg = <0x40304000 0xa000>; /* 40k */
74 reg = <0x48241000 0x1000>,
75 <0x48240100 0x0100>;
81 reg = <0x48242000 0x1000>;
89 reg = <0x48240600 0x20>;
98 reg = <0x48281000 0x1000>;
[all …]
H A Ddra7.dtsi61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
79 #size-cells = <0>;
81 cpu0: cpu@0 {
84 reg = <0>;
109 opp-supported-hw = <0xFF 0x01>;
119 opp-supported-hw = <0xFF 0x02>;
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-ld4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-sld8.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-ld11.dtsi11 /memreserve/ 0x80000000 0x02000000;
21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0 0x000>;
46 reg = <0 0x001>;
95 #clock-cells = <0>;
113 soc@0 {
117 ranges = <0 0 0 0xffffffff>;
122 reg = <0x54006000 0x100>;
123 interrupts = <0 39 4>;
[all …]
H A Duniphier-pxs3.dtsi11 /memreserve/ 0x80000000 0x02000000;
21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
52 reg = <0 0x001>;
61 reg = <0 0x002>;
70 reg = <0 0x003>;
123 #clock-cells = <0>;
141 soc@0 {
145 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-pxs2.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
161 <0x506c0000 0x400>;
162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
[all …]
H A Duniphier-ld20.dtsi12 /memreserve/ 0x80000000 0x02000000;
22 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0 0x000>;
57 reg = <0 0x001>;
67 reg = <0 0x100>;
77 reg = <0 0x101>;
169 #clock-cells = <0>;
221 soc@0 {
225 ranges = <0 0 0 0xffffffff>;
[all …]
/openbmc/linux/drivers/pmdomain/bcm/
H A Dbcm2835-power.c19 #define PM_GNRIC 0x00
20 #define PM_AUDIO 0x04
21 #define PM_STATUS 0x18
22 #define PM_RSTC 0x1c
23 #define PM_RSTS 0x20
24 #define PM_WDOG 0x24
25 #define PM_PADS0 0x28
26 #define PM_PADS2 0x2c
27 #define PM_PADS3 0x30
28 #define PM_PADS4 0x34
[all …]
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi20 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0 0x000>;
46 reg = <0 0x001>;
100 #clock-cells = <0>;
124 reg = <0x0 0x81000000 0x0 0x01000000>;
129 soc@0 {
133 ranges = <0 0 0 0xffffffff>;
138 reg = <0x54006000 0x100>;
140 #size-cells = <0>;
[all …]
/openbmc/linux/include/linux/mfd/
H A Dcs42l43-regs.h13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
[all …]

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