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12

/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp4xx.dtsi19 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
26 ranges = <0 0x0 0x50000000 0x01000000>,
27 <1 0x0 0x51000000 0x01000000>,
28 <2 0x0 0x52000000 0x01000000>,
29 <3 0x0 0x53000000 0x01000000>,
30 <4 0x0 0x54000000 0x01000000>,
31 <5 0x0 0x55000000 0x01000000>,
32 <6 0x0 0x56000000 0x01000000>,
33 <7 0x0 0x57000000 0x01000000>;
34 dma-ranges = <0 0x0 0x50000000 0x01000000>,
[all …]
/openbmc/u-boot/arch/sh/cpu/sh4/
H A Dwatchdog.c11 #define WDT_RST_P (0)
18 return inb(WDT_BASE + 0x04); in csr_read()
23 outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00); in cnt_write()
28 outl((unsigned short)value | 0xA500, WDT_BASE + 0x04); in csr_write()
33 outl(0x55000000, WDT_BASE + 0x08); in watchdog_reset()
39 cnt_write(0); in watchdog_init()
43 return 0; in watchdog_init()
49 return 0; in watchdog_disable()
/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dsocionext,uniphier-gpio.yaml14 pattern: "^gpio@[0-9a-f]+$"
32 The second cell bits[3:0] is used to specify trigger type as follows:
41 minimum: 0
56 "^.+-hog(-[0-9]+)?$":
92 reg = <0x55000000 0x200>;
98 gpio-ranges = <&pinctrl 0 0 0>;
101 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
/openbmc/u-boot/board/renesas/sh7763rdp/
H A Dlowlevel_init.S27 * 0xFFCC0008
37 write32 MSTPCR0_A, MSTPCR0_D /* Address of Power Control Register 0 */
168 CCR_A: .long 0xFF00001C
169 MMUCR_A: .long 0xFF000010
170 RAMCR_A: .long 0xFF000074
173 MSTPCR0_A: .long 0xFFC80030
174 MSTPCR1_A: .long 0xFFC80038
177 WDTST_A: .long 0xFFCC0000
178 WDTCSR_A: .long 0xFFCC0004
179 WDTBST_A: .long 0xFFCC0008
[all …]
/openbmc/u-boot/board/alliedtelesis/x530/
H A Dx530.c22 #define MVEBU_DEV_BUS_BASE (MVEBU_REGISTER(0x10400))
24 #define CONFIG_NVS_LOCATION 0xf4800000
28 {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
29 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
30 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
31 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
32 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
33 {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
40 return 0; in hws_board_topology_load()
50 0x1, /* active interfaces */
[all …]
/openbmc/u-boot/board/espt/
H A Dlowlevel_init.S168 PACR_A: .long 0xFFEF0000
169 PBCR_A: .long 0xFFEF0002
170 PCCR_A: .long 0xFFEF0004
171 PDCR_A: .long 0xFFEF0006
172 PECR_A: .long 0xFFEF0008
173 PFCR_A: .long 0xFFEF000A
174 PGCR_A: .long 0xFFEF000C
175 PHCR_A: .long 0xFFEF000E
176 PICR_A: .long 0xFFEF0010
177 PJCR_A: .long 0xFFEF0012
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dmmio.c21 [INT_SOURCE_CSR] = 0xd7010,
22 [INT_MASK_CSR] = 0xd7014,
23 [INT1_SOURCE_CSR] = 0xd7088,
24 [INT1_MASK_CSR] = 0xd708c,
25 [INT_MCU_CMD_SOURCE] = 0xd51f0,
26 [INT_MCU_CMD_EVENT] = 0x3108,
27 [WFDMA0_ADDR] = 0xd4000,
28 [WFDMA0_PCIE1_ADDR] = 0xd8000,
29 [WFDMA_EXT_CSR_ADDR] = 0xd7000,
30 [CBTOP1_PHY_END] = 0x77ffffff,
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Duniphier-sld8.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
[all …]
H A Duniphier-ld4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
36 #clock-cells = <0>;
41 #clock-cells = <0>;
56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
57 <0x506c0000 0x400>;
58 interrupts = <0 174 4>, <0 175 4>;
69 reg = <0x54006000 0x100>;
70 interrupts = <0 39 4>;
[all …]
H A Duniphier-pro5.dtsi15 #size-cells = <0>;
17 cpu@0 {
20 reg = <0>;
116 #clock-cells = <0>;
121 #clock-cells = <0>;
136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
137 <0x506c0000 0x400>;
138 interrupts = <0 190 4>, <0 191 4>;
149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
150 <0x506c8000 0x400>;
[all …]
H A Duniphier-ld11.dtsi11 /memreserve/ 0x80000000 0x02000000;
21 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0 0x000>;
46 reg = <0 0x001>;
95 #clock-cells = <0>;
113 soc@0 {
117 ranges = <0 0 0 0xffffffff>;
122 reg = <0x54006000 0x100>;
123 interrupts = <0 39 4>;
[all …]
H A Duniphier-pro4.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
44 #clock-cells = <0>;
49 #clock-cells = <0>;
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
77 reg = <0x54006000 0x100>;
78 interrupts = <0 39 4>;
[all …]
H A Duniphier-pxs3.dtsi11 /memreserve/ 0x80000000 0x02000000;
21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
52 reg = <0 0x001>;
61 reg = <0 0x002>;
70 reg = <0 0x003>;
123 #clock-cells = <0>;
141 soc@0 {
145 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-pxs2.dtsi18 #size-cells = <0>;
20 cpu0: cpu@0 {
23 reg = <0>;
111 #clock-cells = <0>;
116 #clock-cells = <0>;
160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
161 <0x506c0000 0x400>;
162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
173 reg = <0x54006000 0x100>;
174 interrupts = <0 39 4>;
[all …]
H A Duniphier-ld20.dtsi12 /memreserve/ 0x80000000 0x02000000;
22 #size-cells = <0>;
44 cpu0: cpu@0 {
47 reg = <0 0x000>;
57 reg = <0 0x001>;
67 reg = <0 0x100>;
77 reg = <0 0x101>;
169 #clock-cells = <0>;
221 soc@0 {
225 ranges = <0 0 0 0xffffffff>;
[all …]
/openbmc/linux/arch/arm/boot/dts/socionext/
H A Duniphier-ld4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-sld8.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
37 #clock-cells = <0>;
42 #clock-cells = <0>;
57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
58 <0x506c0000 0x400>;
71 reg = <0x54006000 0x100>;
73 #size-cells = <0>;
76 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro4.dtsi18 #size-cells = <0>;
20 cpu@0 {
23 reg = <0>;
45 #clock-cells = <0>;
50 #clock-cells = <0>;
65 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
66 <0x506c0000 0x400>;
79 reg = <0x54006000 0x100>;
81 #size-cells = <0>;
84 pinctrl-0 = <&pinctrl_spi0>;
[all …]
H A Duniphier-pro5.dtsi17 #size-cells = <0>;
19 cpu@0 {
22 reg = <0>;
118 #clock-cells = <0>;
123 #clock-cells = <0>;
138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
139 <0x506c0000 0x400>;
152 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
153 <0x506c8000 0x400>;
166 reg = <0x54006000 0x100>;
[all …]
H A Duniphier-pxs2.dtsi19 #size-cells = <0>;
21 cpu0: cpu@0 {
24 reg = <0>;
112 #clock-cells = <0>;
117 #clock-cells = <0>;
163 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
164 <0x506c0000 0x400>;
179 reg = <0x54006000 0x100>;
181 #size-cells = <0>;
184 pinctrl-0 = <&pinctrl_spi0>;
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7996/
H A Dmmio.c15 [WF_AGG_BASE] = { { 0x820e2000, 0x820f2000, 0x830e2000 } },
16 [WF_ARB_BASE] = { { 0x820e3000, 0x820f3000, 0x830e3000 } },
17 [WF_TMAC_BASE] = { { 0x820e4000, 0x820f4000, 0x830e4000 } },
18 [WF_RMAC_BASE] = { { 0x820e5000, 0x820f5000, 0x830e5000 } },
19 [WF_DMA_BASE] = { { 0x820e7000, 0x820f7000, 0x830e7000 } },
20 [WF_WTBLOFF_BASE] = { { 0x820e9000, 0x820f9000, 0x830e9000 } },
21 [WF_ETBF_BASE] = { { 0x820ea000, 0x820fa000, 0x830ea000 } },
22 [WF_LPON_BASE] = { { 0x820eb000, 0x820fb000, 0x830eb000 } },
23 [WF_MIB_BASE] = { { 0x820ed000, 0x820fd000, 0x830ed000 } },
24 [WF_RATE_BASE] = { { 0x820ee000, 0x820fe000, 0x830ee000 } },
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7921/
H A Dpci.c16 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7961),
18 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x7922),
20 { PCI_DEVICE(PCI_VENDOR_ID_ITTIM, 0x7922),
22 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0608),
24 { PCI_DEVICE(PCI_VENDOR_ID_MEDIATEK, 0x0616),
63 { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */ in __mt7921_reg_addr()
64 { 0x820ed000, 0x24800, 0x00800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */ in __mt7921_reg_addr()
65 { 0x820e4000, 0x21000, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */ in __mt7921_reg_addr()
66 { 0x820e7000, 0x21e00, 0x00200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */ in __mt7921_reg_addr()
67 { 0x820eb000, 0x24200, 0x00400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */ in __mt7921_reg_addr()
[all …]
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi20 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0 0x000>;
46 reg = <0 0x001>;
100 #clock-cells = <0>;
124 reg = <0x0 0x81000000 0x0 0x01000000>;
129 soc@0 {
133 ranges = <0 0 0 0xffffffff>;
138 reg = <0x54006000 0x100>;
140 #size-cells = <0>;
[all …]
H A Duniphier-pxs3.dtsi21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
54 reg = <0 0x001>;
65 reg = <0 0x002>;
76 reg = <0 0x003>;
135 #clock-cells = <0>;
190 reg = <0x0 0x81000000 0x0 0x01000000>;
195 soc@0 {
199 ranges = <0 0 0 0xffffffff>;
[all …]
H A Duniphier-ld20.dtsi21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
96 cluster0_opp: opp-table-0 {
180 #clock-cells = <0>;
235 reg = <0x0 0x81000000 0x0 0x01000000>;
240 soc@0 {
[all …]

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