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/openbmc/linux/arch/arm/mach-omap2/
H A Domap54xx.h17 #define L4_54XX_BASE 0x4a000000
18 #define L4_WK_54XX_BASE 0x4ae00000
19 #define L4_PER_54XX_BASE 0x48000000
20 #define L3_54XX_BASE 0x44000000
21 #define OMAP54XX_32KSYNCT_BASE 0x4ae04000
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
23 #define OMAP54XX_CM_CORE_BASE 0x4a008000
24 #define OMAP54XX_PRM_BASE 0x4ae06000
25 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
26 #define OMAP54XX_SCM_BASE 0x4a002000
[all …]
H A Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
H A Dam33xx.h11 #define L4_SLOW_AM33XX_BASE 0x48000000
13 #define AM33XX_SCM_BASE 0x44E10000
15 #define AM33XX_PRCM_BASE 0x44E00000
16 #define AM43XX_PRCM_BASE 0x44DF0000
17 #define AM33XX_TAP_BASE (AM33XX_CTRL_BASE + 0x3FC)
H A Dti81xx.h11 #define L4_SLOW_TI81XX_BASE 0x48000000
13 #define TI81XX_SCM_BASE 0x48140000
15 #define TI81XX_PRCM_BASE 0x48180000
19 * TI81XX register for checking device ID (it adds 0x204 to tap base while
20 * TI81XX DEVICE ID register is at offset 0x600 from control base).
23 TI81XX_CONTROL_DEVICE_ID - 0x204)
26 #define TI81XX_ARM_INTC_BASE 0x48200000
/openbmc/u-boot/include/configs/
H A Drcar-gen3-common.h28 #define GICD_BASE 0xF1010000
29 #define GICC_BASE 0xF1020000
40 #define DRAM_RSV_SIZE 0x08000000
41 #define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
42 #define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
43 #define CONFIG_SYS_LOAD_ADDR 0x58000000
46 #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
48 #define CONFIG_SYS_MONITOR_BASE 0x00000000
60 "bootm_size=0x10000000\0"
63 "tftp 0x48080000 Image; " \
[all …]
H A Dorigen.h20 #define CONFIG_SYS_SDRAM_BASE 0x40000000
26 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000)
27 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
34 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
38 #define CONFIG_SYS_MONITOR_BASE 0x00000000
41 #define S5P_CHECK_SLEEP 0x00000BAD
42 #define S5P_CHECK_DIDLE 0xBAD00000
43 #define S5P_CHECK_LPA 0xABAD0000
46 #define COPY_BL2_FNPTR_ADDR 0x02020030
47 #define CONFIG_SPL_TEXT_BASE 0x02021410
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/omap/
H A Dl4.txt27 reg = <0x48000000 0x800>,
28 <0x48000800 0x800>,
29 <0x48001000 0x400>,
30 <0x48001400 0x400>,
31 <0x48001800 0x400>,
32 <0x48001c00 0x400>;
36 ranges = <0 0x48000000 0x100000>;
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp4xx.dtsi19 * windows in the 256MB space from 0x50000000 to 0x5fffffff.
26 ranges = <0 0x0 0x50000000 0x01000000>,
27 <1 0x0 0x51000000 0x01000000>,
28 <2 0x0 0x52000000 0x01000000>,
29 <3 0x0 0x53000000 0x01000000>,
30 <4 0x0 0x54000000 0x01000000>,
31 <5 0x0 0x55000000 0x01000000>,
32 <6 0x0 0x56000000 0x01000000>,
33 <7 0x0 0x57000000 0x01000000>;
34 dma-ranges = <0 0x0 0x50000000 0x01000000>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dintel,ixp4xx-pci.yaml54 - const: 0xf800
55 - const: 0
56 - const: 0
73 reg = <0xc0000000 0x1000>;
77 bus-range = <0x00 0xff>;
80 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
81 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
83 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
86 interrupt-map-mask = <0xf800 0 0 7>;
88 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p-main.dtsi10 reg = <0x00 0x70000000 0x00 0x10000>;
13 ranges = <0x00 0x00 0x70000000 0x10000>;
23 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
24 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
25 <0x01 0x00000000 0x00 0x2000>, /* GICC */
26 <0x01 0x00010000 0x00 0x1000>, /* GICH */
27 <0x01 0x00020000 0x00 0x2000>; /* GICV */
36 reg = <0x00 0x01820000 0x00 0x10000>;
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
49 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
[all …]
H A Dk3-am64.dtsi53 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
57 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
58 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
59 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
60 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
62 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
H A Dk3-am62.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
/openbmc/u-boot/board/renesas/sh7785lcr/
H A DREADME.sh7785lcr25 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
26 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
27 0x06000000 - 0x07ffffff(CS1) | reserved | I2C
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
30 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
31 0x14000000 - 0x17ffffff(CS5) | I2C | USB
32 0x18000000 - 0x1bffffff(CS6) | reserved | SD
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
[all …]
/openbmc/qemu/linux-user/microblaze/
H A Dtarget_mman.h5 * CONFIG_KERNEL_START 0xc0000000 (default in Kconfig)
7 #define TASK_UNMAPPED_BASE 0x48000000
10 #define ELF_ET_DYN_BASE 0x08000000
/openbmc/qemu/tests/qtest/
H A Ddm163-test.c29 GPIO_OUT(name, 0); \
30 } while (0)
36 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in rise_gpio_pin_dck()
38 qtest_writel(qts, 0x48000414, 0x00000002); in rise_gpio_pin_dck()
44 qtest_writel(qts, 0x48000400, 0xFFFFFEB7); in lower_gpio_pin_dck()
45 /* Write 0 in ODR for PB1 */ in lower_gpio_pin_dck()
46 qtest_writel(qts, 0x48000414, 0x00000000); in lower_gpio_pin_dck()
52 qtest_writel(qts, 0x48000800, 0xFFFFF7FF); in rise_gpio_pin_selbk()
54 qtest_writel(qts, 0x48000814, 0x00000020); in rise_gpio_pin_selbk()
60 qtest_writel(qts, 0x48000800, 0xFFFFF7FF); in lower_gpio_pin_selbk()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfaraday,ftintc010.txt22 reg = <0x48000000 0x1000>;
/openbmc/qemu/hw/arm/
H A Dstrongarm.h7 #define SA_CS0 0x00000000
8 #define SA_CS1 0x08000000
9 #define SA_CS2 0x10000000
10 #define SA_CS3 0x18000000
11 #define SA_PCMCIA_CS0 0x20000000
12 #define SA_PCMCIA_CS1 0x30000000
13 #define SA_CS4 0x40000000
14 #define SA_CS5 0x48000000
16 #define SA_SDCS0 0xc0000000
17 #define SA_SDCS1 0xc8000000
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77965-ulcb.dts20 reg = <0x0 0x48000000 0x0 0x78000000>;
31 clock-names = "du.0", "du.1", "du.3",
32 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77965-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77965-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
30 clock-names = "du.0", "du.1", "du.3",
31 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77960-salvator-xs.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774e1-hihope-rzg2h.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x5 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.3",
36 "dclkin.0", "dclkin.1", "dclkin.3";
H A Dr8a77960-salvator-x.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
H A Dr8a774a1-hihope-rzg2m-rev2.dts19 reg = <0x0 0x48000000 0x0 0x78000000>;
24 reg = <0x6 0x00000000 0x0 0x80000000>;
35 clock-names = "du.0", "du.1", "du.2",
36 "dclkin.0", "dclkin.1", "dclkin.2";
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Ddma-controller.yaml26 reg = <0x48000000 0x1000>;
27 interrupts = <0 12 0x4>,
28 <0 13 0x4>,
29 <0 14 0x4>,
30 <0 15 0x4>;
34 dma-channel-mask = <0xfffe>;

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