Home
last modified time | relevance | path

Searched +full:0 +full:x4321 (Results 1 – 25 of 30) sorted by relevance

12

/openbmc/qemu/tests/qtest/
H A Dendianness-test.c30 { "mips", "malta", 0x10000000, .bswap = true },
31 { "mipsel", "malta", 0x10000000 },
32 { "mips64", "magnum", 0x90000000, .bswap = true },
33 { "mips64", "pica61", 0x90000000, .bswap = true },
34 { "mips64", "malta", 0x10000000, .bswap = true },
35 { "mips64el", "fuloong2e", 0x1fd00000 },
36 { "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" },
37 { "ppc", "40p", 0x80000000, .bswap = true },
38 { "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" },
39 { "ppc64", "mac99", 0xf2000000, .bswap = true, .superio = "i82378" },
[all …]
/openbmc/qemu/tests/tcg/mips/user/ase/dsp/
H A Dtest_dsp_r1_muleq_s_w_phr.c9 rs = 0x8000; in main()
10 rt = 0x8000; in main()
11 result = 0x7FFFFFFF; in main()
15 ("muleq_s.w.phr %0, %2, %3\n\t" in main()
20 dsp = (dsp >> 21) & 0x01; in main()
24 rs = 0x1234; in main()
25 rt = 0x4321; in main()
26 result = 0x98be968; in main()
30 ("muleq_s.w.phr %0, %2, %3\n\t" in main()
35 dsp = (dsp >> 21) & 0x01; in main()
[all …]
H A Dtest_dsp_r1_extr_s_h.c9 ach = 0x05; in main()
10 acl = 0xB4CB; in main()
11 result = 0x00007FFF; in main()
15 "extr_s.h %0, $ac1, 0x03\n\t" in main()
20 dsp = (dsp >> 23) & 0x01; in main()
24 ach = 0xffffffff; in main()
25 acl = 0x12344321; in main()
26 result = 0xFFFF8000; in main()
30 "extr_s.h %0, $ac1, 0x08\n\t" in main()
35 dsp = (dsp >> 23) & 0x01; in main()
[all …]
H A Dtest_dsp_r1_extrv_s_h.c9 ach = 0x05; in main()
10 acl = 0xB4CB; in main()
11 dsp = 0x07; in main()
12 rs = 0x03; in main()
13 result = 0x00007FFF; in main()
16 ("wrdsp %1, 0x01\n\t" in main()
19 "extrv_s.h %0, $ac1, %2\n\t" in main()
24 dsp = (dsp >> 23) & 0x01; in main()
28 rs = 0x08; in main()
29 ach = 0xffffffff; in main()
[all …]
/openbmc/u-boot/arch/arm/mach-zynq/
H A DKconfig58 default 0x800
61 default 0x1400000
68 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
/openbmc/linux/drivers/ssb/
H A Db43_pci_bridge.c21 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4301) },
22 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4306) },
23 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4307) },
24 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) },
25 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
26 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
27 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
28 { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC, 0x4318) },
29 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
30 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
[all …]
H A Dscan.c101 u16 chipid_fallback = 0; in pcidev_to_chipid()
104 case 0x4301: in pcidev_to_chipid()
105 chipid_fallback = 0x4301; in pcidev_to_chipid()
107 case 0x4305 ... 0x4307: in pcidev_to_chipid()
108 chipid_fallback = 0x4307; in pcidev_to_chipid()
110 case 0x4403: in pcidev_to_chipid()
111 chipid_fallback = 0x4402; in pcidev_to_chipid()
113 case 0x4610 ... 0x4615: in pcidev_to_chipid()
114 chipid_fallback = 0x4610; in pcidev_to_chipid()
116 case 0x4710 ... 0x4715: in pcidev_to_chipid()
[all …]
H A Ddriver_chipcommon.c106 ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0); in ssb_chipco_set_clockmode()
130 if (tmp & 0x10) in chipco_pctl_get_slowclksrc()
137 tmp &= 0x7; in chipco_pctl_get_slowclksrc()
138 if (tmp == 0) in chipco_pctl_get_slowclksrc()
215 if (bus->chip_id == 0x4321) { in chipco_powercontrol_init()
216 if (bus->chip_rev == 0) in chipco_powercontrol_init()
217 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4); in chipco_powercontrol_init()
219 chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4); in chipco_powercontrol_init()
229 0x0000FFFF) | 0x00040000); in chipco_powercontrol_init()
247 case 0x4312: in pmu_fast_powerup_delay()
[all …]
/openbmc/u-boot/include/faraday/
H A Dftpci100.h15 unsigned int iosize; /* 0x00 - I/O Space Size Signal */
16 unsigned int prot; /* 0x04 - AHB Protection */
17 unsigned int rsved[8]; /* 0x08-0x24 - Reserved */
18 unsigned int conf; /* 0x28 - PCI Configuration */
19 unsigned int data; /* 0x2c - PCI Configuration DATA */
30 #define PCI_INT_MASK 0x4c
31 #define PCI_MEM_BASE_SIZE1 0x50
32 #define PCI_MEM_BASE_SIZE2 0x54
33 #define PCI_MEM_BASE_SIZE3 0x58
63 #define FTPCI100_BRIDGE_VENDORID 0x159b
[all …]
/openbmc/u-boot/arch/arm/mach-zynqmp/
H A DKconfig58 Expect a table of register-value pairs, e.g. "0x12345678 0x4321"
78 default 0x600
115 default 0x0 if JTAG_MODE
116 default 0x1 if QSPI_MODE_24BIT
117 default 0x2 if QSPI_MODE_32BIT
118 default 0x3 if SD_MODE
119 default 0x4 if NAND_MODE
120 default 0x5 if SD_MODE1
121 default 0x6 if EMMC_MODE
122 default 0x7 if USB_MODE
[all …]
/openbmc/linux/arch/sh/boards/mach-highlander/
H A Dirq-r7785rp.c15 UNUSED = 0,
46 { 0xa4000010, 0, 16, /* IRLMCR1 */
47 { 0, 0, 0, 0, CF, AX88796, SMBUS, TP,
48 RTC, 0, TH_ALERT, 0, 0, 0, 0, 0 } },
49 { 0xa4000012, 0, 16, /* IRLMCR2 */
50 { 0, 0, 0, 0, 0, 0, 0, 0,
55 0, IRQ_CF, IRQ_EXT4, IRQ_EXT5,
66 if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000) in highlander_plat_irq_setup()
71 __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ in highlander_plat_irq_setup()
74 __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */ in highlander_plat_irq_setup()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dfaraday,ftpci100.yaml18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
/openbmc/u-boot/tools/
H A Dzynqimage.c10 * Expected Header Size = 0x8C0
13 * 0x 0 - Interrupt Table (8 words)
14 * ... (Default value = 0xeafffffe)
15 * 0x 1f
16 * 0x 20 - Width Detection
17 * * DEFAULT_WIDTHDETECTION 0xaa995566
18 * 0x 24 - Image Identifier
19 * * DEFAULT_IMAGEIDENTIFIER 0x584c4e58
20 * 0x 28 - Encryption
21 * * 0x00000000 - None
[all …]
H A Dzynqmpimage.c9 * * ug1137 ZynqMP Software Developer Guide v6.0 (Chapter 16)
11 * Expected Header Size = 0x9C0
14 * 0x 0 - Interrupt table (8 words)
15 * ... (Default value = 0xeafffffe)
16 * 0x 1f
17 * 0x 20 - Width detection
18 * * DEFAULT_WIDTHDETECTION 0xaa995566
19 * 0x 24 - Image identifier
20 * * DEFAULT_IMAGEIDENTIFIER 0x584c4e58
21 * 0x 28 - Encryption
[all …]
/openbmc/linux/sound/pci/hda/
H A Dhp_x360_helper.c10 { 0x17, 0x90170110 }, in alc295_fixup_hp_top_speakers()
14 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0000), WRITE_COEF(0x28, 0x0000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
15 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x003f), WRITE_COEF(0x28, 0x1000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
16 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0004), WRITE_COEF(0x28, 0x0600), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
17 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x0006), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
18 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0xc0c0), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
19 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x0008), WRITE_COEF(0x28, 0xb000), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
20 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x002e), WRITE_COEF(0x28, 0x0800), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
21 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006a), WRITE_COEF(0x28, 0x00c1), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
22 …WRITE_COEF(0x24, 0x0012), WRITE_COEF(0x26, 0x006c), WRITE_COEF(0x28, 0x0320), WRITE_COEF(0x29, 0xb… in alc295_fixup_hp_top_speakers()
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dtest-i386.c59 #define CC_C 0x0001
60 #define CC_P 0x0004
61 #define CC_A 0x0010
62 #define CC_Z 0x0040
63 #define CC_S 0x0080
64 #define CC_O 0x0800
73 return v | ((v ^ 0xabcd) << 32); in i2l()
187 asm("lea " STR ", %0"\
195 asm("lea " STR ", %0"\
203 asm(".code16 ; .byte 0x67 ; leal " STR ", %0 ; .code32"\
[all …]
/openbmc/linux/drivers/gpu/drm/tiny/
H A Dbochs.c24 #define VBE_DISPI_IOPORT_INDEX 0x01CE
25 #define VBE_DISPI_IOPORT_DATA 0x01CF
27 #define VBE_DISPI_INDEX_ID 0x0
28 #define VBE_DISPI_INDEX_XRES 0x1
29 #define VBE_DISPI_INDEX_YRES 0x2
30 #define VBE_DISPI_INDEX_BPP 0x3
31 #define VBE_DISPI_INDEX_ENABLE 0x4
32 #define VBE_DISPI_INDEX_BANK 0x5
33 #define VBE_DISPI_INDEX_VIRT_WIDTH 0x6
34 #define VBE_DISPI_INDEX_VIRT_HEIGHT 0x7
[all …]
/openbmc/linux/drivers/s390/block/
H A Ddasd_devmap.c58 * <devno> : (0x)?[0-9a-fA-F]+
59 * <busid> : [0-0a-f]\.[0-9a-f]\.(0x)?[0-9a-fA-F]+
70 int dasd_probeonly = 0; /* is true, when probeonly mode is active */
71 int dasd_autodetect = 0; /* is true, when autodetection is active */
72 int dasd_nopav = 0; /* is true, when PAV is disabled */
103 hash = 0; in dasd_hash_busid()
104 for (i = 0; (i < DASD_BUS_ID_SIZE) && *bus_id; i++, bus_id++) in dasd_hash_busid()
106 return hash & 0xff; in dasd_hash_busid()
140 if (strncmp(DASD_IPLDEV, str, strlen(DASD_IPLDEV)) == 0) { in dasd_busid()
145 *id0 = 0; in dasd_busid()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/
H A Ddpcs_3_1_4_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_SUP_DIG_IDCODE_LO 0x0000
33 …DPCSSYS_CR0_SUP_DIG_IDCODE_HI 0x0001
34 …DPCSSYS_CR0_SUP_DIG_REFCLK_OVRD_IN 0x0002
35 …DPCSSYS_CR0_SUP_DIG_MPLLA_DIV_CLK_OVRD_IN 0x0003
36 …DPCSSYS_CR0_SUP_DIG_MPLLA_HDMI_CLK_OVRD_IN 0x0004
37 …DPCSSYS_CR0_SUP_DIG_MPLLB_DIV_CLK_OVRD_IN 0x0005
38 …DPCSSYS_CR0_SUP_DIG_MPLLB_HDMI_CLK_OVRD_IN 0x0006
39 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_0 0x0007
40 …DPCSSYS_CR0_SUP_DIG_MPLLA_OVRD_IN_1 0x0008
[all …]
H A Ddpcs_4_2_0_offset.h27 // base address: 0x0
28 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
30 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
35 // base address: 0x360
36 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
38 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
43 // base address: 0x6c0
44 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
46 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
51 // base address: 0xa20
[all …]
H A Ddpcs_4_2_2_offset.h14 // base address: 0x0
15 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
17 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
22 // base address: 0x360
23 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
25 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
30 // base address: 0x6c0
31 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
33 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
38 // base address: 0xa20
[all …]
H A Ddpcs_4_2_3_offset.h31 // base address: 0x0
32 …DPCSSYS_CR0_DPCSSYS_CR_ADDR 0x2934
34 …DPCSSYS_CR0_DPCSSYS_CR_DATA 0x2935
39 // base address: 0x360
40 …DPCSSYS_CR1_DPCSSYS_CR_ADDR 0x2a0c
42 …DPCSSYS_CR1_DPCSSYS_CR_DATA 0x2a0d
47 // base address: 0x6c0
48 …DPCSSYS_CR2_DPCSSYS_CR_ADDR 0x2ae4
50 …DPCSSYS_CR2_DPCSSYS_CR_DATA 0x2ae5
55 // base address: 0xa20
[all …]
/openbmc/linux/drivers/scsi/
H A Dhptiop.c48 u32 req = 0; in iop_wait_ready_itl()
51 for (i = 0; i < millisec; i++) { in iop_wait_ready_itl()
61 return 0; in iop_wait_ready_itl()
118 int ret = 0; in iop_intr_itl()
120 if (plx && readl(plx + 0x11C5C) & 0xf) in iop_intr_itl()
121 writel(1, plx + 0x11C60); in iop_intr_itl()
154 outbound_tail = 0; in mv_outbound_read()
158 return 0; in mv_outbound_read()
167 head = 0; in mv_inbound_write()
177 u32 req_type = (tag >> 5) & 0x7; in hptiop_request_callback_mv()
[all …]
H A Dstex.c45 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
46 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
47 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
48 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
49 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
50 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
51 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
52 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
53 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
54 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h26 #define ixATTR00 0x0000
27 #define ixATTR01 0x0001
28 #define ixATTR02 0x0002
29 #define ixATTR03 0x0003
30 #define ixATTR04 0x0004
31 #define ixATTR05 0x0005
32 #define ixATTR06 0x0006
33 #define ixATTR07 0x0007
34 #define ixATTR08 0x0008
35 #define ixATTR09 0x0009
[all …]

12