1de2bdb3dSTom St Denis /* 2de2bdb3dSTom St Denis * 3de2bdb3dSTom St Denis * Copyright (C) 2016 Advanced Micro Devices, Inc. 4de2bdb3dSTom St Denis * 5de2bdb3dSTom St Denis * Permission is hereby granted, free of charge, to any person obtaining a 6de2bdb3dSTom St Denis * copy of this software and associated documentation files (the "Software"), 7de2bdb3dSTom St Denis * to deal in the Software without restriction, including without limitation 8de2bdb3dSTom St Denis * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9de2bdb3dSTom St Denis * and/or sell copies of the Software, and to permit persons to whom the 10de2bdb3dSTom St Denis * Software is furnished to do so, subject to the following conditions: 11de2bdb3dSTom St Denis * 12de2bdb3dSTom St Denis * The above copyright notice and this permission notice shall be included 13de2bdb3dSTom St Denis * in all copies or substantial portions of the Software. 14de2bdb3dSTom St Denis * 15de2bdb3dSTom St Denis * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 16de2bdb3dSTom St Denis * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17de2bdb3dSTom St Denis * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18de2bdb3dSTom St Denis * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 19de2bdb3dSTom St Denis * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20de2bdb3dSTom St Denis * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21de2bdb3dSTom St Denis */ 22de2bdb3dSTom St Denis 23de2bdb3dSTom St Denis #ifndef DCE_6_0_D_H 24de2bdb3dSTom St Denis #define DCE_6_0_D_H 25de2bdb3dSTom St Denis 26de2bdb3dSTom St Denis #define ixATTR00 0x0000 27de2bdb3dSTom St Denis #define ixATTR01 0x0001 28de2bdb3dSTom St Denis #define ixATTR02 0x0002 29de2bdb3dSTom St Denis #define ixATTR03 0x0003 30de2bdb3dSTom St Denis #define ixATTR04 0x0004 31de2bdb3dSTom St Denis #define ixATTR05 0x0005 32de2bdb3dSTom St Denis #define ixATTR06 0x0006 33de2bdb3dSTom St Denis #define ixATTR07 0x0007 34de2bdb3dSTom St Denis #define ixATTR08 0x0008 35de2bdb3dSTom St Denis #define ixATTR09 0x0009 36de2bdb3dSTom St Denis #define ixATTR0A 0x000A 37de2bdb3dSTom St Denis #define ixATTR0B 0x000B 38de2bdb3dSTom St Denis #define ixATTR0C 0x000C 39de2bdb3dSTom St Denis #define ixATTR0D 0x000D 40de2bdb3dSTom St Denis #define ixATTR0E 0x000E 41de2bdb3dSTom St Denis #define ixATTR0F 0x000F 42de2bdb3dSTom St Denis #define ixATTR10 0x0010 43de2bdb3dSTom St Denis #define ixATTR11 0x0011 44de2bdb3dSTom St Denis #define ixATTR12 0x0012 45de2bdb3dSTom St Denis #define ixATTR13 0x0013 46de2bdb3dSTom St Denis #define ixATTR14 0x0014 47de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR0 0x0001 48de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR10 0x000B 49de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR1 0x0002 50de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR11 0x000C 51de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR12 0x000D 52de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR13 0x000E 53de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR2 0x0003 54de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR3 0x0004 55de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR4 0x0005 56de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR5 0x0006 57de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR6 0x0007 58de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR7 0x0008 59de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR8 0x0009 60de2bdb3dSTom St Denis #define ixAUDIO_DESCRIPTOR9 0x000A 61de2bdb3dSTom St Denis #define ixAZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 62de2bdb3dSTom St Denis #define ixAZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 63de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 64de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 65de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 66de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 67de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 68de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 69de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 70de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 71de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_PIN_DEBUG 0x0000 72de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 73de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 74de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 75de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 76de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 77de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 78de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 79de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 80de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002A 81de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002B 82de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002C 83de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002D 84de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002E 85de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002F 86de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 87de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 88de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 89de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 90de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 91de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 92de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 93de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 94de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 95de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 96de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 97de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003A 98de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003B 99de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003C 100de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003D 101de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003E 102de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003F 103de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 104de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 105de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 106de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 107de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 108de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 109de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 110de2bdb3dSTom St Denis #define ixAZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 111de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 112de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005A 113de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005B 114de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005C 115de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005D 116de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005E 117de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005F 118de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 119de2bdb3dSTom St Denis #define ixAZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 120de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 121de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 122de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270D 123de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270E 124de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273E 125de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 126de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2F09 127de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2F0B 128de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2F0A 129de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 130de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 131de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 132de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17FF 133de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 134de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 135de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 136de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 137de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1F05 138de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1F0F 139de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1F0B 140de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1F04 141de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1F0A 142de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 143de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 144de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 145de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 146de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 147de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 148de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 149de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377C 150de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377B 151de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 152de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 153de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 154de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 155de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 156de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 157de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 158de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377A 159de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 160de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 161de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 162de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 163de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 164de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371C 165de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371D 166de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371E 167de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371F 168de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 169de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 170de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 171de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 172de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 173de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 174de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3F09 175de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3F0C 176de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3F0E 177de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0F02 178de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0F04 179de2bdb3dSTom St Denis #define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0F00 180de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378A 181de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378B 182de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378C 183de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378D 184de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378E 185de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378F 186de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 187de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 188de2bdb3dSTom St Denis #define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 189de2bdb3dSTom St Denis #define ixAZALIA_FIFO_SIZE_CONTROL 0x0000 190de2bdb3dSTom St Denis #define ixAZALIA_LATENCY_COUNTER_CONTROL 0x0001 191de2bdb3dSTom St Denis #define ixAZALIA_STREAM_DEBUG 0x0005 192de2bdb3dSTom St Denis #define ixAZALIA_WORSTCASE_LATENCY_COUNT 0x0002 193de2bdb3dSTom St Denis #define ixCRT00 0x0000 194de2bdb3dSTom St Denis #define ixCRT01 0x0001 195de2bdb3dSTom St Denis #define ixCRT02 0x0002 196de2bdb3dSTom St Denis #define ixCRT03 0x0003 197de2bdb3dSTom St Denis #define ixCRT04 0x0004 198de2bdb3dSTom St Denis #define ixCRT05 0x0005 199de2bdb3dSTom St Denis #define ixCRT06 0x0006 200de2bdb3dSTom St Denis #define ixCRT07 0x0007 201de2bdb3dSTom St Denis #define ixCRT08 0x0008 202de2bdb3dSTom St Denis #define ixCRT09 0x0009 203de2bdb3dSTom St Denis #define ixCRT0A 0x000A 204de2bdb3dSTom St Denis #define ixCRT0B 0x000B 205de2bdb3dSTom St Denis #define ixCRT0C 0x000C 206de2bdb3dSTom St Denis #define ixCRT0D 0x000D 207de2bdb3dSTom St Denis #define ixCRT0E 0x000E 208de2bdb3dSTom St Denis #define ixCRT0F 0x000F 209de2bdb3dSTom St Denis #define ixCRT10 0x0010 210de2bdb3dSTom St Denis #define ixCRT11 0x0011 211de2bdb3dSTom St Denis #define ixCRT12 0x0012 212de2bdb3dSTom St Denis #define ixCRT13 0x0013 213de2bdb3dSTom St Denis #define ixCRT14 0x0014 214de2bdb3dSTom St Denis #define ixCRT15 0x0015 215de2bdb3dSTom St Denis #define ixCRT16 0x0016 216de2bdb3dSTom St Denis #define ixCRT17 0x0017 217de2bdb3dSTom St Denis #define ixCRT18 0x0018 218de2bdb3dSTom St Denis #define ixCRT1E 0x001E 219de2bdb3dSTom St Denis #define ixCRT1F 0x001F 220de2bdb3dSTom St Denis #define ixCRT22 0x0022 221de2bdb3dSTom St Denis #define ixDCIO_DEBUG10 0x0010 222de2bdb3dSTom St Denis #define ixDCIO_DEBUG1 0x0001 223de2bdb3dSTom St Denis #define ixDCIO_DEBUG11 0x0011 224de2bdb3dSTom St Denis #define ixDCIO_DEBUG12 0x0012 225de2bdb3dSTom St Denis #define ixDCIO_DEBUG13 0x0013 226de2bdb3dSTom St Denis #define ixDCIO_DEBUG2 0x0002 227de2bdb3dSTom St Denis #define ixDCIO_DEBUG3 0x0003 228de2bdb3dSTom St Denis #define ixDCIO_DEBUG4 0x0004 229de2bdb3dSTom St Denis #define ixDCIO_DEBUG5 0x0005 230de2bdb3dSTom St Denis #define ixDCIO_DEBUG6 0x0006 231de2bdb3dSTom St Denis #define ixDCIO_DEBUG7 0x0007 232de2bdb3dSTom St Denis #define ixDCIO_DEBUG8 0x0008 233de2bdb3dSTom St Denis #define ixDCIO_DEBUG9 0x0009 234de2bdb3dSTom St Denis #define ixDCIO_DEBUGA 0x000A 235de2bdb3dSTom St Denis #define ixDCIO_DEBUGB 0x000B 236de2bdb3dSTom St Denis #define ixDCIO_DEBUGC 0x000C 237de2bdb3dSTom St Denis #define ixDCIO_DEBUGD 0x000D 238de2bdb3dSTom St Denis #define ixDCIO_DEBUGE 0x000E 239de2bdb3dSTom St Denis #define ixDCIO_DEBUGF 0x000F 240de2bdb3dSTom St Denis #define ixDCIO_DEBUG_ID 0x0000 241de2bdb3dSTom St Denis #define ixDMIF_DEBUG02_CORE0 0x0002 242de2bdb3dSTom St Denis #define ixDMIF_DEBUG02_CORE1 0x000A 243de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_A 0x0010 244de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_B 0x0011 245de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_C 0x0012 246de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_D 0x0013 247de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_E 0x0014 248de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_F 0x0015 249de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_G 0x0016 250de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_H 0x0017 251de2bdb3dSTom St Denis #define ixDP_AUX1_DEBUG_I 0x0018 252de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_A 0x0020 253de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_B 0x0021 254de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_C 0x0022 255de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_D 0x0023 256de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_E 0x0024 257de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_F 0x0025 258de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_G 0x0026 259de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_H 0x0027 260de2bdb3dSTom St Denis #define ixDP_AUX2_DEBUG_I 0x0028 261de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_A 0x0030 262de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_B 0x0031 263de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_C 0x0032 264de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_D 0x0033 265de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_E 0x0034 266de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_F 0x0035 267de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_G 0x0036 268de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_H 0x0037 269de2bdb3dSTom St Denis #define ixDP_AUX3_DEBUG_I 0x0038 270de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_A 0x0040 271de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_B 0x0041 272de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_C 0x0042 273de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_D 0x0043 274de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_E 0x0044 275de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_F 0x0045 276de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_G 0x0046 277de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_H 0x0047 278de2bdb3dSTom St Denis #define ixDP_AUX4_DEBUG_I 0x0048 279de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_A 0x0070 280de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_B 0x0071 281de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_C 0x0072 282de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_D 0x0073 283de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_E 0x0074 284de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_F 0x0075 285de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_G 0x0076 286de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_H 0x0077 287de2bdb3dSTom St Denis #define ixDP_AUX5_DEBUG_I 0x0078 288de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_A 0x0080 289de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_B 0x0081 290de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_C 0x0082 291de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_D 0x0083 292de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_E 0x0084 293de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_F 0x0085 294de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_G 0x0086 295de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_H 0x0087 296de2bdb3dSTom St Denis #define ixDP_AUX6_DEBUG_I 0x0088 297de2bdb3dSTom St Denis #define ixFMT_DEBUG0 0x0001 298de2bdb3dSTom St Denis #define ixFMT_DEBUG1 0x0002 299de2bdb3dSTom St Denis #define ixFMT_DEBUG2 0x0003 300de2bdb3dSTom St Denis #define ixFMT_DEBUG_ID 0x0000 301de2bdb3dSTom St Denis #define ixGRA00 0x0000 302de2bdb3dSTom St Denis #define ixGRA01 0x0001 303de2bdb3dSTom St Denis #define ixGRA02 0x0002 304de2bdb3dSTom St Denis #define ixGRA03 0x0003 305de2bdb3dSTom St Denis #define ixGRA04 0x0004 306de2bdb3dSTom St Denis #define ixGRA05 0x0005 307de2bdb3dSTom St Denis #define ixGRA06 0x0006 308de2bdb3dSTom St Denis #define ixGRA07 0x0007 309de2bdb3dSTom St Denis #define ixGRA08 0x0008 310de2bdb3dSTom St Denis #define ixIDDCCIF02_DBG_DCCIF_C 0x0009 311de2bdb3dSTom St Denis #define ixIDDCCIF04_DBG_DCCIF_E 0x000B 312de2bdb3dSTom St Denis #define ixIDDCCIF05_DBG_DCCIF_F 0x000C 313de2bdb3dSTom St Denis #define ixMVP_DEBUG_12 0x000C 314de2bdb3dSTom St Denis #define ixMVP_DEBUG_13 0x000D 315de2bdb3dSTom St Denis #define ixMVP_DEBUG_14 0x000E 316de2bdb3dSTom St Denis #define ixMVP_DEBUG_15 0x000F 317de2bdb3dSTom St Denis #define ixMVP_DEBUG_16 0x0010 318de2bdb3dSTom St Denis #define ixMVP_DEBUG_17 0x0011 319de2bdb3dSTom St Denis #define ixSEQ00 0x0000 320de2bdb3dSTom St Denis #define ixSEQ01 0x0001 321de2bdb3dSTom St Denis #define ixSEQ02 0x0002 322de2bdb3dSTom St Denis #define ixSEQ03 0x0003 323de2bdb3dSTom St Denis #define ixSEQ04 0x0004 324de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION0 0x0005 325de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION10 0x000F 326de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION1 0x0006 327de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION11 0x0010 328de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION12 0x0011 329de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION13 0x0012 330de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION14 0x0013 331de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION15 0x0014 332de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION16 0x0015 333de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION17 0x0016 334de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION2 0x0007 335de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION3 0x0008 336de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION4 0x0009 337de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION5 0x000A 338de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION6 0x000B 339de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION7 0x000C 340de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION8 0x000D 341de2bdb3dSTom St Denis #define ixSINK_DESCRIPTION9 0x000E 342de2bdb3dSTom St Denis #define ixVGADCC_DBG_DCCIF_C 0x007E 343de2bdb3dSTom St Denis #define mmABM_TEST_DEBUG_DATA 0x169F 344de2bdb3dSTom St Denis #define mmABM_TEST_DEBUG_INDEX 0x169E 345de2bdb3dSTom St Denis #define mmAFMT_60958_0 0x1C41 346de2bdb3dSTom St Denis #define mmAFMT_60958_1 0x1C42 347de2bdb3dSTom St Denis #define mmAFMT_60958_2 0x1C48 348de2bdb3dSTom St Denis #define mmAFMT_AUDIO_CRC_CONTROL 0x1C43 349de2bdb3dSTom St Denis #define mmAFMT_AUDIO_CRC_RESULT 0x1C49 350de2bdb3dSTom St Denis #define mmAFMT_AUDIO_DBG_DTO_CNTL 0x1C52 351de2bdb3dSTom St Denis #define mmAFMT_AUDIO_INFO0 0x1C3F 352de2bdb3dSTom St Denis #define mmAFMT_AUDIO_INFO1 0x1C40 353de2bdb3dSTom St Denis #define mmAFMT_AUDIO_PACKET_CONTROL 0x1C4B 354de2bdb3dSTom St Denis #define mmAFMT_AUDIO_PACKET_CONTROL2 0x1C17 355de2bdb3dSTom St Denis #define mmAFMT_AUDIO_SRC_CONTROL 0x1C4F 356de2bdb3dSTom St Denis #define mmAFMT_AVI_INFO0 0x1C21 357de2bdb3dSTom St Denis #define mmAFMT_AVI_INFO1 0x1C22 358de2bdb3dSTom St Denis #define mmAFMT_AVI_INFO2 0x1C23 359de2bdb3dSTom St Denis #define mmAFMT_AVI_INFO3 0x1C24 360de2bdb3dSTom St Denis #define mmAFMT_GENERIC_0 0x1C28 361de2bdb3dSTom St Denis #define mmAFMT_GENERIC_1 0x1C29 362de2bdb3dSTom St Denis #define mmAFMT_GENERIC_2 0x1C2A 363de2bdb3dSTom St Denis #define mmAFMT_GENERIC_3 0x1C2B 364de2bdb3dSTom St Denis #define mmAFMT_GENERIC_4 0x1C2C 365de2bdb3dSTom St Denis #define mmAFMT_GENERIC_5 0x1C2D 366de2bdb3dSTom St Denis #define mmAFMT_GENERIC_6 0x1C2E 367de2bdb3dSTom St Denis #define mmAFMT_GENERIC_7 0x1C2F 368de2bdb3dSTom St Denis #define mmAFMT_GENERIC_HDR 0x1C27 369de2bdb3dSTom St Denis #define mmAFMT_INFOFRAME_CONTROL0 0x1C4D 370de2bdb3dSTom St Denis #define mmAFMT_INTERRUPT_STATUS 0x1C14 371de2bdb3dSTom St Denis #define mmAFMT_ISRC1_0 0x1C18 372de2bdb3dSTom St Denis #define mmAFMT_ISRC1_1 0x1C19 373de2bdb3dSTom St Denis #define mmAFMT_ISRC1_2 0x1C1A 374de2bdb3dSTom St Denis #define mmAFMT_ISRC1_3 0x1C1B 375de2bdb3dSTom St Denis #define mmAFMT_ISRC1_4 0x1C1C 376de2bdb3dSTom St Denis #define mmAFMT_ISRC2_0 0x1C1D 377de2bdb3dSTom St Denis #define mmAFMT_ISRC2_1 0x1C1E 378de2bdb3dSTom St Denis #define mmAFMT_ISRC2_2 0x1C1F 379de2bdb3dSTom St Denis #define mmAFMT_ISRC2_3 0x1C20 380de2bdb3dSTom St Denis #define mmAFMT_MPEG_INFO0 0x1C25 381de2bdb3dSTom St Denis #define mmAFMT_MPEG_INFO1 0x1C26 382de2bdb3dSTom St Denis #define mmAFMT_RAMP_CONTROL0 0x1C44 383de2bdb3dSTom St Denis #define mmAFMT_RAMP_CONTROL1 0x1C45 384de2bdb3dSTom St Denis #define mmAFMT_RAMP_CONTROL2 0x1C46 385de2bdb3dSTom St Denis #define mmAFMT_RAMP_CONTROL3 0x1C47 386de2bdb3dSTom St Denis #define mmAFMT_STATUS 0x1C4A 387de2bdb3dSTom St Denis #define mmAFMT_VBI_PACKET_CONTROL 0x1C4C 388de2bdb3dSTom St Denis #define mmATTRDR 0x00F0 389de2bdb3dSTom St Denis #define mmATTRDW 0x00F0 390de2bdb3dSTom St Denis #define mmATTRX 0x00F0 391de2bdb3dSTom St Denis #define mmAUX_ARB_CONTROL 0x1882 392de2bdb3dSTom St Denis #define mmAUX_CONTROL 0x1880 393de2bdb3dSTom St Denis #define mmAUX_DPHY_RX_CONTROL0 0x188A 394de2bdb3dSTom St Denis #define mmAUX_DPHY_RX_CONTROL1 0x188B 395de2bdb3dSTom St Denis #define mmAUX_DPHY_RX_STATUS 0x188D 396de2bdb3dSTom St Denis #define mmAUX_DPHY_TX_CONTROL 0x1889 397de2bdb3dSTom St Denis #define mmAUX_DPHY_TX_REF_CONTROL 0x1888 398de2bdb3dSTom St Denis #define mmAUX_DPHY_TX_STATUS 0x188C 399de2bdb3dSTom St Denis #define mmAUX_GTC_SYNC_CONTROL 0x188E 400de2bdb3dSTom St Denis #define mmAUX_GTC_SYNC_DATA 0x1890 401de2bdb3dSTom St Denis #define mmAUX_INTERRUPT_CONTROL 0x1883 402de2bdb3dSTom St Denis #define mmAUX_LS_DATA 0x1887 403de2bdb3dSTom St Denis #define mmAUX_LS_STATUS 0x1885 404de2bdb3dSTom St Denis #define mmAUXN_IMPCAL 0x190C 405de2bdb3dSTom St Denis #define mmAUXP_IMPCAL 0x190B 406de2bdb3dSTom St Denis #define mmAUX_SW_CONTROL 0x1881 407de2bdb3dSTom St Denis #define mmAUX_SW_DATA 0x1886 408de2bdb3dSTom St Denis #define mmAUX_SW_STATUS 0x1884 409de2bdb3dSTom St Denis #define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x17C9 410de2bdb3dSTom St Denis #define mmAZALIA_AUDIO_DTO 0x17BA 411de2bdb3dSTom St Denis #define mmAZALIA_AUDIO_DTO_CONTROL 0x17BB 412de2bdb3dSTom St Denis #define mmAZALIA_BDL_DMA_CONTROL 0x17BF 413de2bdb3dSTom St Denis #define mmAZALIA_CONTROLLER_DEBUG 0x17CF 414de2bdb3dSTom St Denis #define mmAZALIA_CORB_DMA_CONTROL 0x17C1 415de2bdb3dSTom St Denis #define mmAZALIA_CYCLIC_BUFFER_SYNC 0x17CA 416de2bdb3dSTom St Denis #define mmAZALIA_DATA_DMA_CONTROL 0x17BE 417de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x17D5 418de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_DEBUG 0x17DF 419de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 420de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 421de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x17DE 422de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x17DB 423de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x17DC 424de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x17DD 425de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x17D7 426de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x17DA 427de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x17D9 428de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x17D8 429de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x17D6 430de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x17D3 431de2bdb3dSTom St Denis #define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x17D2 432de2bdb3dSTom St Denis #define mmAZALIA_GLOBAL_CAPABILITIES 0x17CB 433de2bdb3dSTom St Denis #define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x17CC 434de2bdb3dSTom St Denis #define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x17CD 435de2bdb3dSTom St Denis #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0 436de2bdb3dSTom St Denis #define mmAZALIA_SCLK_CONTROL 0x17BC 437de2bdb3dSTom St Denis #define mmAZALIA_STREAM_DATA 0x17E9 438de2bdb3dSTom St Denis #define mmAZALIA_STREAM_INDEX 0x17E8 439de2bdb3dSTom St Denis #define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x17BD 440de2bdb3dSTom St Denis #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1781 441de2bdb3dSTom St Denis #define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1780 442de2bdb3dSTom St Denis #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1787 443de2bdb3dSTom St Denis #define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1786 444de2bdb3dSTom St Denis #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x178D 445de2bdb3dSTom St Denis #define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x178C 446de2bdb3dSTom St Denis #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1793 447de2bdb3dSTom St Denis #define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1792 448de2bdb3dSTom St Denis #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x1799 449de2bdb3dSTom St Denis #define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x1798 450de2bdb3dSTom St Denis #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x179F 451de2bdb3dSTom St Denis #define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x179E 452de2bdb3dSTom St Denis #define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x17E9 453de2bdb3dSTom St Denis #define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x17E8 454de2bdb3dSTom St Denis #define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x17ED 455de2bdb3dSTom St Denis #define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x17EC 456de2bdb3dSTom St Denis #define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x17F1 457de2bdb3dSTom St Denis #define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x17F0 458de2bdb3dSTom St Denis #define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x17F5 459de2bdb3dSTom St Denis #define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x17F4 460de2bdb3dSTom St Denis #define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x17F9 461de2bdb3dSTom St Denis #define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x17F8 462de2bdb3dSTom St Denis #define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x17FD 463de2bdb3dSTom St Denis #define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x17FC 464de2bdb3dSTom St Denis #define mmAZ_TEST_DEBUG_DATA 0x17D1 465de2bdb3dSTom St Denis #define mmAZ_TEST_DEBUG_INDEX 0x17D0 466de2bdb3dSTom St Denis #define mmBL1_PWM_ABM_CNTL 0x162E 467de2bdb3dSTom St Denis #define mmBL1_PWM_AMBIENT_LIGHT_LEVEL 0x1628 468de2bdb3dSTom St Denis #define mmBL1_PWM_BL_UPDATE_SAMPLE_RATE 0x162F 469de2bdb3dSTom St Denis #define mmBL1_PWM_CURRENT_ABM_LEVEL 0x162B 470de2bdb3dSTom St Denis #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C 471de2bdb3dSTom St Denis #define mmBL1_PWM_GRP2_REG_LOCK 0x1630 472de2bdb3dSTom St Denis #define mmBL1_PWM_MINIMUM_DUTY_CYCLE 0x162D 473de2bdb3dSTom St Denis #define mmBL1_PWM_TARGET_ABM_LEVEL 0x162A 474de2bdb3dSTom St Denis #define mmBL1_PWM_USER_LEVEL 0x1629 475de2bdb3dSTom St Denis #define mmBL_PWM_CNTL 0x191E 476de2bdb3dSTom St Denis #define mmBL_PWM_CNTL2 0x191F 477de2bdb3dSTom St Denis #define mmBL_PWM_GRP1_REG_LOCK 0x1921 478de2bdb3dSTom St Denis #define mmBL_PWM_PERIOD_CNTL 0x1920 479de2bdb3dSTom St Denis #define mmBPHYC_DAC_AUTO_CALIB_CONTROL 0x19FE 480de2bdb3dSTom St Denis #define mmBPHYC_DAC_MACRO_CNTL 0x19FD 481de2bdb3dSTom St Denis #define mmCC_DC_PIPE_DIS 0x177F 482de2bdb3dSTom St Denis #define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x17D4 483de2bdb3dSTom St Denis #define mmCOMM_MATRIXA_TRANS_C11_C12 0x1A43 484de2bdb3dSTom St Denis #define mmCOMM_MATRIXA_TRANS_C13_C14 0x1A44 485de2bdb3dSTom St Denis #define mmCOMM_MATRIXA_TRANS_C21_C22 0x1A45 486de2bdb3dSTom St Denis #define mmCOMM_MATRIXA_TRANS_C23_C24 0x1A46 487de2bdb3dSTom St Denis #define mmCOMM_MATRIXA_TRANS_C31_C32 0x1A47 488de2bdb3dSTom St Denis #define mmCOMM_MATRIXA_TRANS_C33_C34 0x1A48 489de2bdb3dSTom St Denis #define mmCOMM_MATRIXB_TRANS_C11_C12 0x1A49 490de2bdb3dSTom St Denis #define mmCOMM_MATRIXB_TRANS_C13_C14 0x1A4A 491de2bdb3dSTom St Denis #define mmCOMM_MATRIXB_TRANS_C21_C22 0x1A4B 492de2bdb3dSTom St Denis #define mmCOMM_MATRIXB_TRANS_C23_C24 0x1A4C 493de2bdb3dSTom St Denis #define mmCOMM_MATRIXB_TRANS_C31_C32 0x1A4D 494de2bdb3dSTom St Denis #define mmCOMM_MATRIXB_TRANS_C33_C34 0x1A4E 495de2bdb3dSTom St Denis #define mmCRTC0_CRTC_3D_STRUCTURE_CONTROL 0x1B78 496de2bdb3dSTom St Denis #define mmCRTC0_CRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 497de2bdb3dSTom St Denis #define mmCRTC0_CRTC_BLACK_COLOR 0x1BA2 498de2bdb3dSTom St Denis #define mmCRTC0_CRTC_BLANK_CONTROL 0x1B9D 499de2bdb3dSTom St Denis #define mmCRTC0_CRTC_BLANK_DATA_COLOR 0x1BA1 500de2bdb3dSTom St Denis #define mmCRTC0_CRTC_CONTROL 0x1B9C 501de2bdb3dSTom St Denis #define mmCRTC0_CRTC_COUNT_CONTROL 0x1BA9 502de2bdb3dSTom St Denis #define mmCRTC0_CRTC_COUNT_RESET 0x1BAA 503de2bdb3dSTom St Denis #define mmCRTC0_CRTC_DCFE_CLOCK_CONTROL 0x1B7C 504de2bdb3dSTom St Denis #define mmCRTC0_CRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 505de2bdb3dSTom St Denis #define mmCRTC0_CRTC_DTMTEST_CNTL 0x1B92 506de2bdb3dSTom St Denis #define mmCRTC0_CRTC_DTMTEST_STATUS_POSITION 0x1B93 507de2bdb3dSTom St Denis #define mmCRTC0_CRTC_FLOW_CONTROL 0x1B99 508de2bdb3dSTom St Denis #define mmCRTC0_CRTC_FORCE_COUNT_NOW_CNTL 0x1B98 509de2bdb3dSTom St Denis #define mmCRTC0_CRTC_GSL_CONTROL 0x1B7B 510de2bdb3dSTom St Denis #define mmCRTC0_CRTC_GSL_VSYNC_GAP 0x1B79 511de2bdb3dSTom St Denis #define mmCRTC0_CRTC_GSL_WINDOW 0x1B7A 512de2bdb3dSTom St Denis #define mmCRTC0_CRTC_H_BLANK_EARLY_NUM 0x1B7D 513de2bdb3dSTom St Denis #define mmCRTC0_CRTC_H_BLANK_START_END 0x1B81 514de2bdb3dSTom St Denis #define mmCRTC0_CRTC_H_SYNC_A 0x1B82 515de2bdb3dSTom St Denis #define mmCRTC0_CRTC_H_SYNC_A_CNTL 0x1B83 516de2bdb3dSTom St Denis #define mmCRTC0_CRTC_H_SYNC_B 0x1B84 517de2bdb3dSTom St Denis #define mmCRTC0_CRTC_H_SYNC_B_CNTL 0x1B85 518de2bdb3dSTom St Denis #define mmCRTC0_CRTC_H_TOTAL 0x1B80 519de2bdb3dSTom St Denis #define mmCRTC0_CRTC_INTERLACE_CONTROL 0x1B9E 520de2bdb3dSTom St Denis #define mmCRTC0_CRTC_INTERLACE_STATUS 0x1B9F 521de2bdb3dSTom St Denis #define mmCRTC0_CRTC_INTERRUPT_CONTROL 0x1BB4 522de2bdb3dSTom St Denis #define mmCRTC0_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB 523de2bdb3dSTom St Denis #define mmCRTC0_CRTC_MASTER_EN 0x1BC2 524de2bdb3dSTom St Denis #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT 0x1BBF 525de2bdb3dSTom St Denis #define mmCRTC0_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 526de2bdb3dSTom St Denis #define mmCRTC0_CRTC_MVP_STATUS 0x1BC1 527de2bdb3dSTom St Denis #define mmCRTC0_CRTC_NOM_VERT_POSITION 0x1BA5 528de2bdb3dSTom St Denis #define mmCRTC0_CRTC_OVERSCAN_COLOR 0x1BA0 529de2bdb3dSTom St Denis #define mmCRTC0_CRTC_SNAPSHOT_CONTROL 0x1BB0 530de2bdb3dSTom St Denis #define mmCRTC0_CRTC_SNAPSHOT_FRAME 0x1BB2 531de2bdb3dSTom St Denis #define mmCRTC0_CRTC_SNAPSHOT_POSITION 0x1BB1 532de2bdb3dSTom St Denis #define mmCRTC0_CRTC_SNAPSHOT_STATUS 0x1BAF 533de2bdb3dSTom St Denis #define mmCRTC0_CRTC_START_LINE_CONTROL 0x1BB3 534de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STATUS 0x1BA3 535de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STATUS_FRAME_COUNT 0x1BA6 536de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STATUS_HV_COUNT 0x1BA8 537de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STATUS_POSITION 0x1BA4 538de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STATUS_VF_COUNT 0x1BA7 539de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STEREO_CONTROL 0x1BAE 540de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STEREO_FORCE_NEXT_EYE 0x1B9B 541de2bdb3dSTom St Denis #define mmCRTC0_CRTC_STEREO_STATUS 0x1BAD 542de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TEST_DEBUG_DATA 0x1BC7 543de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TEST_DEBUG_INDEX 0x1BC6 544de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TEST_PATTERN_COLOR 0x1BBC 545de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TEST_PATTERN_CONTROL 0x1BBA 546de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TEST_PATTERN_PARAMETERS 0x1BBB 547de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TRIGA_CNTL 0x1B94 548de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TRIGA_MANUAL_TRIG 0x1B95 549de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TRIGB_CNTL 0x1B96 550de2bdb3dSTom St Denis #define mmCRTC0_CRTC_TRIGB_MANUAL_TRIG 0x1B97 551de2bdb3dSTom St Denis #define mmCRTC0_CRTC_UPDATE_LOCK 0x1BB5 552de2bdb3dSTom St Denis #define mmCRTC0_CRTC_VBI_END 0x1B86 553de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_BLANK_START_END 0x1B8D 554de2bdb3dSTom St Denis #define mmCRTC0_CRTC_VERT_SYNC_CONTROL 0x1BAC 555de2bdb3dSTom St Denis #define mmCRTC0_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 556de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_SYNC_A 0x1B8E 557de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_SYNC_A_CNTL 0x1B8F 558de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_SYNC_B 0x1B90 559de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_SYNC_B_CNTL 0x1B91 560de2bdb3dSTom St Denis #define mmCRTC0_CRTC_VSYNC_NOM_INT_STATUS 0x1B8C 561de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_TOTAL 0x1B87 562de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_TOTAL_CONTROL 0x1B8A 563de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_TOTAL_INT_STATUS 0x1B8B 564de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_TOTAL_MAX 0x1B89 565de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_TOTAL_MIN 0x1B88 566de2bdb3dSTom St Denis #define mmCRTC0_CRTC_V_UPDATE_INT_STATUS 0x1BC4 567de2bdb3dSTom St Denis #define mmCRTC0_DCFE_DBG_SEL 0x1B7E 568de2bdb3dSTom St Denis #define mmCRTC0_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F 569de2bdb3dSTom St Denis #define mmCRTC0_MASTER_UPDATE_LOCK 0x1BBD 570de2bdb3dSTom St Denis #define mmCRTC0_MASTER_UPDATE_MODE 0x1BBE 571de2bdb3dSTom St Denis #define mmCRTC0_PIXEL_RATE_CNTL 0x0140 572de2bdb3dSTom St Denis #define mmCRTC1_CRTC_3D_STRUCTURE_CONTROL 0x1E78 573de2bdb3dSTom St Denis #define mmCRTC1_CRTC_ALLOW_STOP_OFF_V_CNT 0x1EC3 574de2bdb3dSTom St Denis #define mmCRTC1_CRTC_BLACK_COLOR 0x1EA2 575de2bdb3dSTom St Denis #define mmCRTC1_CRTC_BLANK_CONTROL 0x1E9D 576de2bdb3dSTom St Denis #define mmCRTC1_CRTC_BLANK_DATA_COLOR 0x1EA1 577de2bdb3dSTom St Denis #define mmCRTC1_CRTC_CONTROL 0x1E9C 578de2bdb3dSTom St Denis #define mmCRTC1_CRTC_COUNT_CONTROL 0x1EA9 579de2bdb3dSTom St Denis #define mmCRTC1_CRTC_COUNT_RESET 0x1EAA 580de2bdb3dSTom St Denis #define mmCRTC1_CRTC_DCFE_CLOCK_CONTROL 0x1E7C 581de2bdb3dSTom St Denis #define mmCRTC1_CRTC_DOUBLE_BUFFER_CONTROL 0x1EB6 582de2bdb3dSTom St Denis #define mmCRTC1_CRTC_DTMTEST_CNTL 0x1E92 583de2bdb3dSTom St Denis #define mmCRTC1_CRTC_DTMTEST_STATUS_POSITION 0x1E93 584de2bdb3dSTom St Denis #define mmCRTC1_CRTC_FLOW_CONTROL 0x1E99 585de2bdb3dSTom St Denis #define mmCRTC1_CRTC_FORCE_COUNT_NOW_CNTL 0x1E98 586de2bdb3dSTom St Denis #define mmCRTC1_CRTC_GSL_CONTROL 0x1E7B 587de2bdb3dSTom St Denis #define mmCRTC1_CRTC_GSL_VSYNC_GAP 0x1E79 588de2bdb3dSTom St Denis #define mmCRTC1_CRTC_GSL_WINDOW 0x1E7A 589de2bdb3dSTom St Denis #define mmCRTC1_CRTC_H_BLANK_EARLY_NUM 0x1E7D 590de2bdb3dSTom St Denis #define mmCRTC1_CRTC_H_BLANK_START_END 0x1E81 591de2bdb3dSTom St Denis #define mmCRTC1_CRTC_H_SYNC_A 0x1E82 592de2bdb3dSTom St Denis #define mmCRTC1_CRTC_H_SYNC_A_CNTL 0x1E83 593de2bdb3dSTom St Denis #define mmCRTC1_CRTC_H_SYNC_B 0x1E84 594de2bdb3dSTom St Denis #define mmCRTC1_CRTC_H_SYNC_B_CNTL 0x1E85 595de2bdb3dSTom St Denis #define mmCRTC1_CRTC_H_TOTAL 0x1E80 596de2bdb3dSTom St Denis #define mmCRTC1_CRTC_INTERLACE_CONTROL 0x1E9E 597de2bdb3dSTom St Denis #define mmCRTC1_CRTC_INTERLACE_STATUS 0x1E9F 598de2bdb3dSTom St Denis #define mmCRTC1_CRTC_INTERRUPT_CONTROL 0x1EB4 599de2bdb3dSTom St Denis #define mmCRTC1_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1EAB 600de2bdb3dSTom St Denis #define mmCRTC1_CRTC_MASTER_EN 0x1EC2 601de2bdb3dSTom St Denis #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT 0x1EBF 602de2bdb3dSTom St Denis #define mmCRTC1_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1EC0 603de2bdb3dSTom St Denis #define mmCRTC1_CRTC_MVP_STATUS 0x1EC1 604de2bdb3dSTom St Denis #define mmCRTC1_CRTC_NOM_VERT_POSITION 0x1EA5 605de2bdb3dSTom St Denis #define mmCRTC1_CRTC_OVERSCAN_COLOR 0x1EA0 606de2bdb3dSTom St Denis #define mmCRTC1_CRTC_SNAPSHOT_CONTROL 0x1EB0 607de2bdb3dSTom St Denis #define mmCRTC1_CRTC_SNAPSHOT_FRAME 0x1EB2 608de2bdb3dSTom St Denis #define mmCRTC1_CRTC_SNAPSHOT_POSITION 0x1EB1 609de2bdb3dSTom St Denis #define mmCRTC1_CRTC_SNAPSHOT_STATUS 0x1EAF 610de2bdb3dSTom St Denis #define mmCRTC1_CRTC_START_LINE_CONTROL 0x1EB3 611de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STATUS 0x1EA3 612de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STATUS_FRAME_COUNT 0x1EA6 613de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STATUS_HV_COUNT 0x1EA8 614de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STATUS_POSITION 0x1EA4 615de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STATUS_VF_COUNT 0x1EA7 616de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STEREO_CONTROL 0x1EAE 617de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STEREO_FORCE_NEXT_EYE 0x1E9B 618de2bdb3dSTom St Denis #define mmCRTC1_CRTC_STEREO_STATUS 0x1EAD 619de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TEST_DEBUG_DATA 0x1EC7 620de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TEST_DEBUG_INDEX 0x1EC6 621de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TEST_PATTERN_COLOR 0x1EBC 622de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TEST_PATTERN_CONTROL 0x1EBA 623de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TEST_PATTERN_PARAMETERS 0x1EBB 624de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TRIGA_CNTL 0x1E94 625de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TRIGA_MANUAL_TRIG 0x1E95 626de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TRIGB_CNTL 0x1E96 627de2bdb3dSTom St Denis #define mmCRTC1_CRTC_TRIGB_MANUAL_TRIG 0x1E97 628de2bdb3dSTom St Denis #define mmCRTC1_CRTC_UPDATE_LOCK 0x1EB5 629de2bdb3dSTom St Denis #define mmCRTC1_CRTC_VBI_END 0x1E86 630de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_BLANK_START_END 0x1E8D 631de2bdb3dSTom St Denis #define mmCRTC1_CRTC_VERT_SYNC_CONTROL 0x1EAC 632de2bdb3dSTom St Denis #define mmCRTC1_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x1EB7 633de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_SYNC_A 0x1E8E 634de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_SYNC_A_CNTL 0x1E8F 635de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_SYNC_B 0x1E90 636de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_SYNC_B_CNTL 0x1E91 637de2bdb3dSTom St Denis #define mmCRTC1_CRTC_VSYNC_NOM_INT_STATUS 0x1E8C 638de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_TOTAL 0x1E87 639de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_TOTAL_CONTROL 0x1E8A 640de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_TOTAL_INT_STATUS 0x1E8B 641de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_TOTAL_MAX 0x1E89 642de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_TOTAL_MIN 0x1E88 643de2bdb3dSTom St Denis #define mmCRTC1_CRTC_V_UPDATE_INT_STATUS 0x1EC4 644de2bdb3dSTom St Denis #define mmCRTC1_DCFE_DBG_SEL 0x1E7E 645de2bdb3dSTom St Denis #define mmCRTC1_DCFE_MEM_LIGHT_SLEEP_CNTL 0x1E7F 646de2bdb3dSTom St Denis #define mmCRTC1_MASTER_UPDATE_LOCK 0x1EBD 647de2bdb3dSTom St Denis #define mmCRTC1_MASTER_UPDATE_MODE 0x1EBE 648de2bdb3dSTom St Denis #define mmCRTC1_PIXEL_RATE_CNTL 0x0144 649de2bdb3dSTom St Denis #define mmCRTC2_CRTC_3D_STRUCTURE_CONTROL 0x4178 650de2bdb3dSTom St Denis #define mmCRTC2_CRTC_ALLOW_STOP_OFF_V_CNT 0x41C3 651de2bdb3dSTom St Denis #define mmCRTC2_CRTC_BLACK_COLOR 0x41A2 652de2bdb3dSTom St Denis #define mmCRTC2_CRTC_BLANK_CONTROL 0x419D 653de2bdb3dSTom St Denis #define mmCRTC2_CRTC_BLANK_DATA_COLOR 0x41A1 654de2bdb3dSTom St Denis #define mmCRTC2_CRTC_CONTROL 0x419C 655de2bdb3dSTom St Denis #define mmCRTC2_CRTC_COUNT_CONTROL 0x41A9 656de2bdb3dSTom St Denis #define mmCRTC2_CRTC_COUNT_RESET 0x41AA 657de2bdb3dSTom St Denis #define mmCRTC2_CRTC_DCFE_CLOCK_CONTROL 0x417C 658de2bdb3dSTom St Denis #define mmCRTC2_CRTC_DOUBLE_BUFFER_CONTROL 0x41B6 659de2bdb3dSTom St Denis #define mmCRTC2_CRTC_DTMTEST_CNTL 0x4192 660de2bdb3dSTom St Denis #define mmCRTC2_CRTC_DTMTEST_STATUS_POSITION 0x4193 661de2bdb3dSTom St Denis #define mmCRTC2_CRTC_FLOW_CONTROL 0x4199 662de2bdb3dSTom St Denis #define mmCRTC2_CRTC_FORCE_COUNT_NOW_CNTL 0x4198 663de2bdb3dSTom St Denis #define mmCRTC2_CRTC_GSL_CONTROL 0x417B 664de2bdb3dSTom St Denis #define mmCRTC2_CRTC_GSL_VSYNC_GAP 0x4179 665de2bdb3dSTom St Denis #define mmCRTC2_CRTC_GSL_WINDOW 0x417A 666de2bdb3dSTom St Denis #define mmCRTC2_CRTC_H_BLANK_EARLY_NUM 0x417D 667de2bdb3dSTom St Denis #define mmCRTC2_CRTC_H_BLANK_START_END 0x4181 668de2bdb3dSTom St Denis #define mmCRTC2_CRTC_H_SYNC_A 0x4182 669de2bdb3dSTom St Denis #define mmCRTC2_CRTC_H_SYNC_A_CNTL 0x4183 670de2bdb3dSTom St Denis #define mmCRTC2_CRTC_H_SYNC_B 0x4184 671de2bdb3dSTom St Denis #define mmCRTC2_CRTC_H_SYNC_B_CNTL 0x4185 672de2bdb3dSTom St Denis #define mmCRTC2_CRTC_H_TOTAL 0x4180 673de2bdb3dSTom St Denis #define mmCRTC2_CRTC_INTERLACE_CONTROL 0x419E 674de2bdb3dSTom St Denis #define mmCRTC2_CRTC_INTERLACE_STATUS 0x419F 675de2bdb3dSTom St Denis #define mmCRTC2_CRTC_INTERRUPT_CONTROL 0x41B4 676de2bdb3dSTom St Denis #define mmCRTC2_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x41AB 677de2bdb3dSTom St Denis #define mmCRTC2_CRTC_MASTER_EN 0x41C2 678de2bdb3dSTom St Denis #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT 0x41BF 679de2bdb3dSTom St Denis #define mmCRTC2_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x41C0 680de2bdb3dSTom St Denis #define mmCRTC2_CRTC_MVP_STATUS 0x41C1 681de2bdb3dSTom St Denis #define mmCRTC2_CRTC_NOM_VERT_POSITION 0x41A5 682de2bdb3dSTom St Denis #define mmCRTC2_CRTC_OVERSCAN_COLOR 0x41A0 683de2bdb3dSTom St Denis #define mmCRTC2_CRTC_SNAPSHOT_CONTROL 0x41B0 684de2bdb3dSTom St Denis #define mmCRTC2_CRTC_SNAPSHOT_FRAME 0x41B2 685de2bdb3dSTom St Denis #define mmCRTC2_CRTC_SNAPSHOT_POSITION 0x41B1 686de2bdb3dSTom St Denis #define mmCRTC2_CRTC_SNAPSHOT_STATUS 0x41AF 687de2bdb3dSTom St Denis #define mmCRTC2_CRTC_START_LINE_CONTROL 0x41B3 688de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STATUS 0x41A3 689de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STATUS_FRAME_COUNT 0x41A6 690de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STATUS_HV_COUNT 0x41A8 691de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STATUS_POSITION 0x41A4 692de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STATUS_VF_COUNT 0x41A7 693de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STEREO_CONTROL 0x41AE 694de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STEREO_FORCE_NEXT_EYE 0x419B 695de2bdb3dSTom St Denis #define mmCRTC2_CRTC_STEREO_STATUS 0x41AD 696de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TEST_DEBUG_DATA 0x41C7 697de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TEST_DEBUG_INDEX 0x41C6 698de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TEST_PATTERN_COLOR 0x41BC 699de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TEST_PATTERN_CONTROL 0x41BA 700de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TEST_PATTERN_PARAMETERS 0x41BB 701de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TRIGA_CNTL 0x4194 702de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TRIGA_MANUAL_TRIG 0x4195 703de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TRIGB_CNTL 0x4196 704de2bdb3dSTom St Denis #define mmCRTC2_CRTC_TRIGB_MANUAL_TRIG 0x4197 705de2bdb3dSTom St Denis #define mmCRTC2_CRTC_UPDATE_LOCK 0x41B5 706de2bdb3dSTom St Denis #define mmCRTC2_CRTC_VBI_END 0x4186 707de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_BLANK_START_END 0x418D 708de2bdb3dSTom St Denis #define mmCRTC2_CRTC_VERT_SYNC_CONTROL 0x41AC 709de2bdb3dSTom St Denis #define mmCRTC2_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x41B7 710de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_SYNC_A 0x418E 711de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_SYNC_A_CNTL 0x418F 712de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_SYNC_B 0x4190 713de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_SYNC_B_CNTL 0x4191 714de2bdb3dSTom St Denis #define mmCRTC2_CRTC_VSYNC_NOM_INT_STATUS 0x418C 715de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_TOTAL 0x4187 716de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_TOTAL_CONTROL 0x418A 717de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_TOTAL_INT_STATUS 0x418B 718de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_TOTAL_MAX 0x4189 719de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_TOTAL_MIN 0x4188 720de2bdb3dSTom St Denis #define mmCRTC2_CRTC_V_UPDATE_INT_STATUS 0x41C4 721de2bdb3dSTom St Denis #define mmCRTC2_DCFE_DBG_SEL 0x417E 722de2bdb3dSTom St Denis #define mmCRTC2_DCFE_MEM_LIGHT_SLEEP_CNTL 0x417F 723de2bdb3dSTom St Denis #define mmCRTC2_MASTER_UPDATE_LOCK 0x41BD 724de2bdb3dSTom St Denis #define mmCRTC2_MASTER_UPDATE_MODE 0x41BE 725de2bdb3dSTom St Denis #define mmCRTC2_PIXEL_RATE_CNTL 0x0148 726de2bdb3dSTom St Denis #define mmCRTC3_CRTC_3D_STRUCTURE_CONTROL 0x4478 727de2bdb3dSTom St Denis #define mmCRTC3_CRTC_ALLOW_STOP_OFF_V_CNT 0x44C3 728de2bdb3dSTom St Denis #define mmCRTC3_CRTC_BLACK_COLOR 0x44A2 729de2bdb3dSTom St Denis #define mmCRTC3_CRTC_BLANK_CONTROL 0x449D 730de2bdb3dSTom St Denis #define mmCRTC3_CRTC_BLANK_DATA_COLOR 0x44A1 731de2bdb3dSTom St Denis #define mmCRTC3_CRTC_CONTROL 0x449C 732de2bdb3dSTom St Denis #define mmCRTC3_CRTC_COUNT_CONTROL 0x44A9 733de2bdb3dSTom St Denis #define mmCRTC3_CRTC_COUNT_RESET 0x44AA 734de2bdb3dSTom St Denis #define mmCRTC3_CRTC_DCFE_CLOCK_CONTROL 0x447C 735de2bdb3dSTom St Denis #define mmCRTC3_CRTC_DOUBLE_BUFFER_CONTROL 0x44B6 736de2bdb3dSTom St Denis #define mmCRTC3_CRTC_DTMTEST_CNTL 0x4492 737de2bdb3dSTom St Denis #define mmCRTC3_CRTC_DTMTEST_STATUS_POSITION 0x4493 738de2bdb3dSTom St Denis #define mmCRTC3_CRTC_FLOW_CONTROL 0x4499 739de2bdb3dSTom St Denis #define mmCRTC3_CRTC_FORCE_COUNT_NOW_CNTL 0x4498 740de2bdb3dSTom St Denis #define mmCRTC3_CRTC_GSL_CONTROL 0x447B 741de2bdb3dSTom St Denis #define mmCRTC3_CRTC_GSL_VSYNC_GAP 0x4479 742de2bdb3dSTom St Denis #define mmCRTC3_CRTC_GSL_WINDOW 0x447A 743de2bdb3dSTom St Denis #define mmCRTC3_CRTC_H_BLANK_EARLY_NUM 0x447D 744de2bdb3dSTom St Denis #define mmCRTC3_CRTC_H_BLANK_START_END 0x4481 745de2bdb3dSTom St Denis #define mmCRTC3_CRTC_H_SYNC_A 0x4482 746de2bdb3dSTom St Denis #define mmCRTC3_CRTC_H_SYNC_A_CNTL 0x4483 747de2bdb3dSTom St Denis #define mmCRTC3_CRTC_H_SYNC_B 0x4484 748de2bdb3dSTom St Denis #define mmCRTC3_CRTC_H_SYNC_B_CNTL 0x4485 749de2bdb3dSTom St Denis #define mmCRTC3_CRTC_H_TOTAL 0x4480 750de2bdb3dSTom St Denis #define mmCRTC3_CRTC_INTERLACE_CONTROL 0x449E 751de2bdb3dSTom St Denis #define mmCRTC3_CRTC_INTERLACE_STATUS 0x449F 752de2bdb3dSTom St Denis #define mmCRTC3_CRTC_INTERRUPT_CONTROL 0x44B4 753de2bdb3dSTom St Denis #define mmCRTC3_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x44AB 754de2bdb3dSTom St Denis #define mmCRTC3_CRTC_MASTER_EN 0x44C2 755de2bdb3dSTom St Denis #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT 0x44BF 756de2bdb3dSTom St Denis #define mmCRTC3_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x44C0 757de2bdb3dSTom St Denis #define mmCRTC3_CRTC_MVP_STATUS 0x44C1 758de2bdb3dSTom St Denis #define mmCRTC3_CRTC_NOM_VERT_POSITION 0x44A5 759de2bdb3dSTom St Denis #define mmCRTC3_CRTC_OVERSCAN_COLOR 0x44A0 760de2bdb3dSTom St Denis #define mmCRTC3_CRTC_SNAPSHOT_CONTROL 0x44B0 761de2bdb3dSTom St Denis #define mmCRTC3_CRTC_SNAPSHOT_FRAME 0x44B2 762de2bdb3dSTom St Denis #define mmCRTC3_CRTC_SNAPSHOT_POSITION 0x44B1 763de2bdb3dSTom St Denis #define mmCRTC3_CRTC_SNAPSHOT_STATUS 0x44AF 764de2bdb3dSTom St Denis #define mmCRTC3_CRTC_START_LINE_CONTROL 0x44B3 765de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STATUS 0x44A3 766de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STATUS_FRAME_COUNT 0x44A6 767de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STATUS_HV_COUNT 0x44A8 768de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STATUS_POSITION 0x44A4 769de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STATUS_VF_COUNT 0x44A7 770de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STEREO_CONTROL 0x44AE 771de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STEREO_FORCE_NEXT_EYE 0x449B 772de2bdb3dSTom St Denis #define mmCRTC3_CRTC_STEREO_STATUS 0x44AD 773de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TEST_DEBUG_DATA 0x44C7 774de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TEST_DEBUG_INDEX 0x44C6 775de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TEST_PATTERN_COLOR 0x44BC 776de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TEST_PATTERN_CONTROL 0x44BA 777de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TEST_PATTERN_PARAMETERS 0x44BB 778de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TRIGA_CNTL 0x4494 779de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TRIGA_MANUAL_TRIG 0x4495 780de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TRIGB_CNTL 0x4496 781de2bdb3dSTom St Denis #define mmCRTC3_CRTC_TRIGB_MANUAL_TRIG 0x4497 782de2bdb3dSTom St Denis #define mmCRTC3_CRTC_UPDATE_LOCK 0x44B5 783de2bdb3dSTom St Denis #define mmCRTC3_CRTC_VBI_END 0x4486 784de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_BLANK_START_END 0x448D 785de2bdb3dSTom St Denis #define mmCRTC3_CRTC_VERT_SYNC_CONTROL 0x44AC 786de2bdb3dSTom St Denis #define mmCRTC3_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x44B7 787de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_SYNC_A 0x448E 788de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_SYNC_A_CNTL 0x448F 789de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_SYNC_B 0x4490 790de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_SYNC_B_CNTL 0x4491 791de2bdb3dSTom St Denis #define mmCRTC3_CRTC_VSYNC_NOM_INT_STATUS 0x448C 792de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_TOTAL 0x4487 793de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_TOTAL_CONTROL 0x448A 794de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_TOTAL_INT_STATUS 0x448B 795de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_TOTAL_MAX 0x4489 796de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_TOTAL_MIN 0x4488 797de2bdb3dSTom St Denis #define mmCRTC3_CRTC_V_UPDATE_INT_STATUS 0x44C4 798de2bdb3dSTom St Denis #define mmCRTC3_DCFE_DBG_SEL 0x447E 799de2bdb3dSTom St Denis #define mmCRTC3_DCFE_MEM_LIGHT_SLEEP_CNTL 0x447F 800de2bdb3dSTom St Denis #define mmCRTC_3D_STRUCTURE_CONTROL 0x1B78 801de2bdb3dSTom St Denis #define mmCRTC3_MASTER_UPDATE_LOCK 0x44BD 802de2bdb3dSTom St Denis #define mmCRTC3_MASTER_UPDATE_MODE 0x44BE 803de2bdb3dSTom St Denis #define mmCRTC3_PIXEL_RATE_CNTL 0x014C 804de2bdb3dSTom St Denis #define mmCRTC4_CRTC_3D_STRUCTURE_CONTROL 0x4778 805de2bdb3dSTom St Denis #define mmCRTC4_CRTC_ALLOW_STOP_OFF_V_CNT 0x47C3 806de2bdb3dSTom St Denis #define mmCRTC4_CRTC_BLACK_COLOR 0x47A2 807de2bdb3dSTom St Denis #define mmCRTC4_CRTC_BLANK_CONTROL 0x479D 808de2bdb3dSTom St Denis #define mmCRTC4_CRTC_BLANK_DATA_COLOR 0x47A1 809de2bdb3dSTom St Denis #define mmCRTC4_CRTC_CONTROL 0x479C 810de2bdb3dSTom St Denis #define mmCRTC4_CRTC_COUNT_CONTROL 0x47A9 811de2bdb3dSTom St Denis #define mmCRTC4_CRTC_COUNT_RESET 0x47AA 812de2bdb3dSTom St Denis #define mmCRTC4_CRTC_DCFE_CLOCK_CONTROL 0x477C 813de2bdb3dSTom St Denis #define mmCRTC4_CRTC_DOUBLE_BUFFER_CONTROL 0x47B6 814de2bdb3dSTom St Denis #define mmCRTC4_CRTC_DTMTEST_CNTL 0x4792 815de2bdb3dSTom St Denis #define mmCRTC4_CRTC_DTMTEST_STATUS_POSITION 0x4793 816de2bdb3dSTom St Denis #define mmCRTC4_CRTC_FLOW_CONTROL 0x4799 817de2bdb3dSTom St Denis #define mmCRTC4_CRTC_FORCE_COUNT_NOW_CNTL 0x4798 818de2bdb3dSTom St Denis #define mmCRTC4_CRTC_GSL_CONTROL 0x477B 819de2bdb3dSTom St Denis #define mmCRTC4_CRTC_GSL_VSYNC_GAP 0x4779 820de2bdb3dSTom St Denis #define mmCRTC4_CRTC_GSL_WINDOW 0x477A 821de2bdb3dSTom St Denis #define mmCRTC4_CRTC_H_BLANK_EARLY_NUM 0x477D 822de2bdb3dSTom St Denis #define mmCRTC4_CRTC_H_BLANK_START_END 0x4781 823de2bdb3dSTom St Denis #define mmCRTC4_CRTC_H_SYNC_A 0x4782 824de2bdb3dSTom St Denis #define mmCRTC4_CRTC_H_SYNC_A_CNTL 0x4783 825de2bdb3dSTom St Denis #define mmCRTC4_CRTC_H_SYNC_B 0x4784 826de2bdb3dSTom St Denis #define mmCRTC4_CRTC_H_SYNC_B_CNTL 0x4785 827de2bdb3dSTom St Denis #define mmCRTC4_CRTC_H_TOTAL 0x4780 828de2bdb3dSTom St Denis #define mmCRTC4_CRTC_INTERLACE_CONTROL 0x479E 829de2bdb3dSTom St Denis #define mmCRTC4_CRTC_INTERLACE_STATUS 0x479F 830de2bdb3dSTom St Denis #define mmCRTC4_CRTC_INTERRUPT_CONTROL 0x47B4 831de2bdb3dSTom St Denis #define mmCRTC4_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x47AB 832de2bdb3dSTom St Denis #define mmCRTC4_CRTC_MASTER_EN 0x47C2 833de2bdb3dSTom St Denis #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT 0x47BF 834de2bdb3dSTom St Denis #define mmCRTC4_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x47C0 835de2bdb3dSTom St Denis #define mmCRTC4_CRTC_MVP_STATUS 0x47C1 836de2bdb3dSTom St Denis #define mmCRTC4_CRTC_NOM_VERT_POSITION 0x47A5 837de2bdb3dSTom St Denis #define mmCRTC4_CRTC_OVERSCAN_COLOR 0x47A0 838de2bdb3dSTom St Denis #define mmCRTC4_CRTC_SNAPSHOT_CONTROL 0x47B0 839de2bdb3dSTom St Denis #define mmCRTC4_CRTC_SNAPSHOT_FRAME 0x47B2 840de2bdb3dSTom St Denis #define mmCRTC4_CRTC_SNAPSHOT_POSITION 0x47B1 841de2bdb3dSTom St Denis #define mmCRTC4_CRTC_SNAPSHOT_STATUS 0x47AF 842de2bdb3dSTom St Denis #define mmCRTC4_CRTC_START_LINE_CONTROL 0x47B3 843de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STATUS 0x47A3 844de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STATUS_FRAME_COUNT 0x47A6 845de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STATUS_HV_COUNT 0x47A8 846de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STATUS_POSITION 0x47A4 847de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STATUS_VF_COUNT 0x47A7 848de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STEREO_CONTROL 0x47AE 849de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STEREO_FORCE_NEXT_EYE 0x479B 850de2bdb3dSTom St Denis #define mmCRTC4_CRTC_STEREO_STATUS 0x47AD 851de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TEST_DEBUG_DATA 0x47C7 852de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TEST_DEBUG_INDEX 0x47C6 853de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TEST_PATTERN_COLOR 0x47BC 854de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TEST_PATTERN_CONTROL 0x47BA 855de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TEST_PATTERN_PARAMETERS 0x47BB 856de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TRIGA_CNTL 0x4794 857de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TRIGA_MANUAL_TRIG 0x4795 858de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TRIGB_CNTL 0x4796 859de2bdb3dSTom St Denis #define mmCRTC4_CRTC_TRIGB_MANUAL_TRIG 0x4797 860de2bdb3dSTom St Denis #define mmCRTC4_CRTC_UPDATE_LOCK 0x47B5 861de2bdb3dSTom St Denis #define mmCRTC4_CRTC_VBI_END 0x4786 862de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_BLANK_START_END 0x478D 863de2bdb3dSTom St Denis #define mmCRTC4_CRTC_VERT_SYNC_CONTROL 0x47AC 864de2bdb3dSTom St Denis #define mmCRTC4_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x47B7 865de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_SYNC_A 0x478E 866de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_SYNC_A_CNTL 0x478F 867de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_SYNC_B 0x4790 868de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_SYNC_B_CNTL 0x4791 869de2bdb3dSTom St Denis #define mmCRTC4_CRTC_VSYNC_NOM_INT_STATUS 0x478C 870de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_TOTAL 0x4787 871de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_TOTAL_CONTROL 0x478A 872de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_TOTAL_INT_STATUS 0x478B 873de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_TOTAL_MAX 0x4789 874de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_TOTAL_MIN 0x4788 875de2bdb3dSTom St Denis #define mmCRTC4_CRTC_V_UPDATE_INT_STATUS 0x47C4 876de2bdb3dSTom St Denis #define mmCRTC4_DCFE_DBG_SEL 0x477E 877de2bdb3dSTom St Denis #define mmCRTC4_DCFE_MEM_LIGHT_SLEEP_CNTL 0x477F 878de2bdb3dSTom St Denis #define mmCRTC4_MASTER_UPDATE_LOCK 0x47BD 879de2bdb3dSTom St Denis #define mmCRTC4_MASTER_UPDATE_MODE 0x47BE 880de2bdb3dSTom St Denis #define mmCRTC4_PIXEL_RATE_CNTL 0x0150 881de2bdb3dSTom St Denis #define mmCRTC5_CRTC_3D_STRUCTURE_CONTROL 0x4A78 882de2bdb3dSTom St Denis #define mmCRTC5_CRTC_ALLOW_STOP_OFF_V_CNT 0x4AC3 883de2bdb3dSTom St Denis #define mmCRTC5_CRTC_BLACK_COLOR 0x4AA2 884de2bdb3dSTom St Denis #define mmCRTC5_CRTC_BLANK_CONTROL 0x4A9D 885de2bdb3dSTom St Denis #define mmCRTC5_CRTC_BLANK_DATA_COLOR 0x4AA1 886de2bdb3dSTom St Denis #define mmCRTC5_CRTC_CONTROL 0x4A9C 887de2bdb3dSTom St Denis #define mmCRTC5_CRTC_COUNT_CONTROL 0x4AA9 888de2bdb3dSTom St Denis #define mmCRTC5_CRTC_COUNT_RESET 0x4AAA 889de2bdb3dSTom St Denis #define mmCRTC5_CRTC_DCFE_CLOCK_CONTROL 0x4A7C 890de2bdb3dSTom St Denis #define mmCRTC5_CRTC_DOUBLE_BUFFER_CONTROL 0x4AB6 891de2bdb3dSTom St Denis #define mmCRTC5_CRTC_DTMTEST_CNTL 0x4A92 892de2bdb3dSTom St Denis #define mmCRTC5_CRTC_DTMTEST_STATUS_POSITION 0x4A93 893de2bdb3dSTom St Denis #define mmCRTC5_CRTC_FLOW_CONTROL 0x4A99 894de2bdb3dSTom St Denis #define mmCRTC5_CRTC_FORCE_COUNT_NOW_CNTL 0x4A98 895de2bdb3dSTom St Denis #define mmCRTC5_CRTC_GSL_CONTROL 0x4A7B 896de2bdb3dSTom St Denis #define mmCRTC5_CRTC_GSL_VSYNC_GAP 0x4A79 897de2bdb3dSTom St Denis #define mmCRTC5_CRTC_GSL_WINDOW 0x4A7A 898de2bdb3dSTom St Denis #define mmCRTC5_CRTC_H_BLANK_EARLY_NUM 0x4A7D 899de2bdb3dSTom St Denis #define mmCRTC5_CRTC_H_BLANK_START_END 0x4A81 900de2bdb3dSTom St Denis #define mmCRTC5_CRTC_H_SYNC_A 0x4A82 901de2bdb3dSTom St Denis #define mmCRTC5_CRTC_H_SYNC_A_CNTL 0x4A83 902de2bdb3dSTom St Denis #define mmCRTC5_CRTC_H_SYNC_B 0x4A84 903de2bdb3dSTom St Denis #define mmCRTC5_CRTC_H_SYNC_B_CNTL 0x4A85 904de2bdb3dSTom St Denis #define mmCRTC5_CRTC_H_TOTAL 0x4A80 905de2bdb3dSTom St Denis #define mmCRTC5_CRTC_INTERLACE_CONTROL 0x4A9E 906de2bdb3dSTom St Denis #define mmCRTC5_CRTC_INTERLACE_STATUS 0x4A9F 907de2bdb3dSTom St Denis #define mmCRTC5_CRTC_INTERRUPT_CONTROL 0x4AB4 908de2bdb3dSTom St Denis #define mmCRTC5_CRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x4AAB 909de2bdb3dSTom St Denis #define mmCRTC5_CRTC_MASTER_EN 0x4AC2 910de2bdb3dSTom St Denis #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT 0x4ABF 911de2bdb3dSTom St Denis #define mmCRTC5_CRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x4AC0 912de2bdb3dSTom St Denis #define mmCRTC5_CRTC_MVP_STATUS 0x4AC1 913de2bdb3dSTom St Denis #define mmCRTC5_CRTC_NOM_VERT_POSITION 0x4AA5 914de2bdb3dSTom St Denis #define mmCRTC5_CRTC_OVERSCAN_COLOR 0x4AA0 915de2bdb3dSTom St Denis #define mmCRTC5_CRTC_SNAPSHOT_CONTROL 0x4AB0 916de2bdb3dSTom St Denis #define mmCRTC5_CRTC_SNAPSHOT_FRAME 0x4AB2 917de2bdb3dSTom St Denis #define mmCRTC5_CRTC_SNAPSHOT_POSITION 0x4AB1 918de2bdb3dSTom St Denis #define mmCRTC5_CRTC_SNAPSHOT_STATUS 0x4AAF 919de2bdb3dSTom St Denis #define mmCRTC5_CRTC_START_LINE_CONTROL 0x4AB3 920de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STATUS 0x4AA3 921de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STATUS_FRAME_COUNT 0x4AA6 922de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STATUS_HV_COUNT 0x4AA8 923de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STATUS_POSITION 0x4AA4 924de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STATUS_VF_COUNT 0x4AA7 925de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STEREO_CONTROL 0x4AAE 926de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STEREO_FORCE_NEXT_EYE 0x4A9B 927de2bdb3dSTom St Denis #define mmCRTC5_CRTC_STEREO_STATUS 0x4AAD 928de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TEST_DEBUG_DATA 0x4AC7 929de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TEST_DEBUG_INDEX 0x4AC6 930de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TEST_PATTERN_COLOR 0x4ABC 931de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TEST_PATTERN_CONTROL 0x4ABA 932de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TEST_PATTERN_PARAMETERS 0x4ABB 933de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TRIGA_CNTL 0x4A94 934de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TRIGA_MANUAL_TRIG 0x4A95 935de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TRIGB_CNTL 0x4A96 936de2bdb3dSTom St Denis #define mmCRTC5_CRTC_TRIGB_MANUAL_TRIG 0x4A97 937de2bdb3dSTom St Denis #define mmCRTC5_CRTC_UPDATE_LOCK 0x4AB5 938de2bdb3dSTom St Denis #define mmCRTC5_CRTC_VBI_END 0x4A86 939de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_BLANK_START_END 0x4A8D 940de2bdb3dSTom St Denis #define mmCRTC5_CRTC_VERT_SYNC_CONTROL 0x4AAC 941de2bdb3dSTom St Denis #define mmCRTC5_CRTC_VGA_PARAMETER_CAPTURE_MODE 0x4AB7 942de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_SYNC_A 0x4A8E 943de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_SYNC_A_CNTL 0x4A8F 944de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_SYNC_B 0x4A90 945de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_SYNC_B_CNTL 0x4A91 946de2bdb3dSTom St Denis #define mmCRTC5_CRTC_VSYNC_NOM_INT_STATUS 0x4A8C 947de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_TOTAL 0x4A87 948de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_TOTAL_CONTROL 0x4A8A 949de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_TOTAL_INT_STATUS 0x4A8B 950de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_TOTAL_MAX 0x4A89 951de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_TOTAL_MIN 0x4A88 952de2bdb3dSTom St Denis #define mmCRTC5_CRTC_V_UPDATE_INT_STATUS 0x4AC4 953de2bdb3dSTom St Denis #define mmCRTC5_DCFE_DBG_SEL 0x4A7E 954de2bdb3dSTom St Denis #define mmCRTC5_DCFE_MEM_LIGHT_SLEEP_CNTL 0x4A7F 955de2bdb3dSTom St Denis #define mmCRTC5_MASTER_UPDATE_LOCK 0x4ABD 956de2bdb3dSTom St Denis #define mmCRTC5_MASTER_UPDATE_MODE 0x4ABE 957de2bdb3dSTom St Denis #define mmCRTC5_PIXEL_RATE_CNTL 0x0154 958de2bdb3dSTom St Denis #define mmCRTC8_DATA 0x00ED 959de2bdb3dSTom St Denis #define mmCRTC8_IDX 0x00ED 960de2bdb3dSTom St Denis #define mmCRTC_ALLOW_STOP_OFF_V_CNT 0x1BC3 961de2bdb3dSTom St Denis #define mmCRTC_BLACK_COLOR 0x1BA2 962de2bdb3dSTom St Denis #define mmCRTC_BLANK_CONTROL 0x1B9D 963de2bdb3dSTom St Denis #define mmCRTC_BLANK_DATA_COLOR 0x1BA1 964de2bdb3dSTom St Denis #define mmCRTC_CONTROL 0x1B9C 965de2bdb3dSTom St Denis #define mmCRTC_COUNT_CONTROL 0x1BA9 966de2bdb3dSTom St Denis #define mmCRTC_COUNT_RESET 0x1BAA 967de2bdb3dSTom St Denis #define mmCRTC_DCFE_CLOCK_CONTROL 0x1B7C 968de2bdb3dSTom St Denis #define mmCRTC_DOUBLE_BUFFER_CONTROL 0x1BB6 969de2bdb3dSTom St Denis #define mmCRTC_DTMTEST_CNTL 0x1B92 970de2bdb3dSTom St Denis #define mmCRTC_DTMTEST_STATUS_POSITION 0x1B93 971de2bdb3dSTom St Denis #define mmCRTC_FLOW_CONTROL 0x1B99 972de2bdb3dSTom St Denis #define mmCRTC_FORCE_COUNT_NOW_CNTL 0x1B98 973de2bdb3dSTom St Denis #define mmCRTC_GSL_CONTROL 0x1B7B 974de2bdb3dSTom St Denis #define mmCRTC_GSL_VSYNC_GAP 0x1B79 975de2bdb3dSTom St Denis #define mmCRTC_GSL_WINDOW 0x1B7A 976de2bdb3dSTom St Denis #define mmCRTC_H_BLANK_EARLY_NUM 0x1B7D 977de2bdb3dSTom St Denis #define mmCRTC_H_BLANK_START_END 0x1B81 978de2bdb3dSTom St Denis #define mmCRTC_H_SYNC_A 0x1B82 979de2bdb3dSTom St Denis #define mmCRTC_H_SYNC_A_CNTL 0x1B83 980de2bdb3dSTom St Denis #define mmCRTC_H_SYNC_B 0x1B84 981de2bdb3dSTom St Denis #define mmCRTC_H_SYNC_B_CNTL 0x1B85 982de2bdb3dSTom St Denis #define mmCRTC_H_TOTAL 0x1B80 983de2bdb3dSTom St Denis #define mmCRTC_INTERLACE_CONTROL 0x1B9E 984de2bdb3dSTom St Denis #define mmCRTC_INTERLACE_STATUS 0x1B9F 985de2bdb3dSTom St Denis #define mmCRTC_INTERRUPT_CONTROL 0x1BB4 986de2bdb3dSTom St Denis #define mmCRTC_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1BAB 987de2bdb3dSTom St Denis #define mmCRTC_MASTER_EN 0x1BC2 988de2bdb3dSTom St Denis #define mmCRTC_MVP_INBAND_CNTL_INSERT 0x1BBF 989de2bdb3dSTom St Denis #define mmCRTC_MVP_INBAND_CNTL_INSERT_TIMER 0x1BC0 990de2bdb3dSTom St Denis #define mmCRTC_MVP_STATUS 0x1BC1 991de2bdb3dSTom St Denis #define mmCRTC_NOM_VERT_POSITION 0x1BA5 992de2bdb3dSTom St Denis #define mmCRTC_OVERSCAN_COLOR 0x1BA0 993de2bdb3dSTom St Denis #define mmCRTC_SNAPSHOT_CONTROL 0x1BB0 994de2bdb3dSTom St Denis #define mmCRTC_SNAPSHOT_FRAME 0x1BB2 995de2bdb3dSTom St Denis #define mmCRTC_SNAPSHOT_POSITION 0x1BB1 996de2bdb3dSTom St Denis #define mmCRTC_SNAPSHOT_STATUS 0x1BAF 997de2bdb3dSTom St Denis #define mmCRTC_START_LINE_CONTROL 0x1BB3 998de2bdb3dSTom St Denis #define mmCRTC_STATUS 0x1BA3 999de2bdb3dSTom St Denis #define mmCRTC_STATUS_FRAME_COUNT 0x1BA6 1000de2bdb3dSTom St Denis #define mmCRTC_STATUS_HV_COUNT 0x1BA8 1001de2bdb3dSTom St Denis #define mmCRTC_STATUS_POSITION 0x1BA4 1002de2bdb3dSTom St Denis #define mmCRTC_STATUS_VF_COUNT 0x1BA7 1003de2bdb3dSTom St Denis #define mmCRTC_STEREO_CONTROL 0x1BAE 1004de2bdb3dSTom St Denis #define mmCRTC_STEREO_FORCE_NEXT_EYE 0x1B9B 1005de2bdb3dSTom St Denis #define mmCRTC_STEREO_STATUS 0x1BAD 1006de2bdb3dSTom St Denis #define mmCRTC_TEST_DEBUG_DATA 0x1BC7 1007de2bdb3dSTom St Denis #define mmCRTC_TEST_DEBUG_INDEX 0x1BC6 1008de2bdb3dSTom St Denis #define mmCRTC_TEST_PATTERN_COLOR 0x1BBC 1009de2bdb3dSTom St Denis #define mmCRTC_TEST_PATTERN_CONTROL 0x1BBA 1010de2bdb3dSTom St Denis #define mmCRTC_TEST_PATTERN_PARAMETERS 0x1BBB 1011de2bdb3dSTom St Denis #define mmCRTC_TRIGA_CNTL 0x1B94 1012de2bdb3dSTom St Denis #define mmCRTC_TRIGA_MANUAL_TRIG 0x1B95 1013de2bdb3dSTom St Denis #define mmCRTC_TRIGB_CNTL 0x1B96 1014de2bdb3dSTom St Denis #define mmCRTC_TRIGB_MANUAL_TRIG 0x1B97 1015de2bdb3dSTom St Denis #define mmCRTC_UPDATE_LOCK 0x1BB5 1016de2bdb3dSTom St Denis #define mmCRTC_VBI_END 0x1B86 1017de2bdb3dSTom St Denis #define mmCRTC_V_BLANK_START_END 0x1B8D 1018de2bdb3dSTom St Denis #define mmCRTC_VERT_SYNC_CONTROL 0x1BAC 1019de2bdb3dSTom St Denis #define mmCRTC_VGA_PARAMETER_CAPTURE_MODE 0x1BB7 1020de2bdb3dSTom St Denis #define mmCRTC_V_SYNC_A 0x1B8E 1021de2bdb3dSTom St Denis #define mmCRTC_V_SYNC_A_CNTL 0x1B8F 1022de2bdb3dSTom St Denis #define mmCRTC_V_SYNC_B 0x1B90 1023de2bdb3dSTom St Denis #define mmCRTC_V_SYNC_B_CNTL 0x1B91 1024de2bdb3dSTom St Denis #define mmCRTC_VSYNC_NOM_INT_STATUS 0x1B8C 1025de2bdb3dSTom St Denis #define mmCRTC_V_TOTAL 0x1B87 1026de2bdb3dSTom St Denis #define mmCRTC_V_TOTAL_CONTROL 0x1B8A 1027de2bdb3dSTom St Denis #define mmCRTC_V_TOTAL_INT_STATUS 0x1B8B 1028de2bdb3dSTom St Denis #define mmCRTC_V_TOTAL_MAX 0x1B89 1029de2bdb3dSTom St Denis #define mmCRTC_V_TOTAL_MIN 0x1B88 1030de2bdb3dSTom St Denis #define mmCRTC_V_UPDATE_INT_STATUS 0x1BC4 1031de2bdb3dSTom St Denis #define mmCUR_COLOR1 0x1A6C 1032de2bdb3dSTom St Denis #define mmCUR_COLOR2 0x1A6D 1033de2bdb3dSTom St Denis #define mmCUR_CONTROL 0x1A66 1034de2bdb3dSTom St Denis #define mmCUR_HOT_SPOT 0x1A6B 1035de2bdb3dSTom St Denis #define mmCUR_POSITION 0x1A6A 1036de2bdb3dSTom St Denis #define mmCUR_REQUEST_FILTER_CNTL 0x1A99 1037de2bdb3dSTom St Denis #define mmCUR_SIZE 0x1A68 1038de2bdb3dSTom St Denis #define mmCUR_SURFACE_ADDRESS 0x1A67 1039de2bdb3dSTom St Denis #define mmCUR_SURFACE_ADDRESS_HIGH 0x1A69 1040de2bdb3dSTom St Denis #define mmCUR_UPDATE 0x1A6E 1041de2bdb3dSTom St Denis #define mmD1VGA_CONTROL 0x00CC 1042de2bdb3dSTom St Denis #define mmD2VGA_CONTROL 0x00CE 1043de2bdb3dSTom St Denis #define mmD3VGA_CONTROL 0x00F8 1044de2bdb3dSTom St Denis #define mmD4VGA_CONTROL 0x00F9 1045de2bdb3dSTom St Denis #define mmD5VGA_CONTROL 0x00FA 1046de2bdb3dSTom St Denis #define mmD6VGA_CONTROL 0x00FB 1047de2bdb3dSTom St Denis #define mmDAC_AUTODETECT_CONTROL 0x19EE 1048de2bdb3dSTom St Denis #define mmDAC_AUTODETECT_CONTROL2 0x19EF 1049de2bdb3dSTom St Denis #define mmDAC_AUTODETECT_CONTROL3 0x19F0 1050de2bdb3dSTom St Denis #define mmDAC_AUTODETECT_INT_CONTROL 0x19F2 1051de2bdb3dSTom St Denis #define mmDAC_AUTODETECT_STATUS 0x19F1 1052de2bdb3dSTom St Denis #define mmDAC_CLK_ENABLE 0x0128 1053de2bdb3dSTom St Denis #define mmDAC_COMPARATOR_ENABLE 0x19F7 1054de2bdb3dSTom St Denis #define mmDAC_COMPARATOR_OUTPUT 0x19F8 1055de2bdb3dSTom St Denis #define mmDAC_CONTROL 0x19F6 1056de2bdb3dSTom St Denis #define mmDAC_CRC_CONTROL 0x19E7 1057de2bdb3dSTom St Denis #define mmDAC_CRC_EN 0x19E6 1058de2bdb3dSTom St Denis #define mmDAC_CRC_SIG_CONTROL 0x19EB 1059de2bdb3dSTom St Denis #define mmDAC_CRC_SIG_CONTROL_MASK 0x19E9 1060de2bdb3dSTom St Denis #define mmDAC_CRC_SIG_RGB 0x19EA 1061de2bdb3dSTom St Denis #define mmDAC_CRC_SIG_RGB_MASK 0x19E8 1062de2bdb3dSTom St Denis #define mmDAC_DATA 0x00F2 1063de2bdb3dSTom St Denis #define mmDAC_DFT_CONFIG 0x19FA 1064de2bdb3dSTom St Denis #define mmDAC_ENABLE 0x19E4 1065de2bdb3dSTom St Denis #define mmDAC_FIFO_STATUS 0x19FB 1066de2bdb3dSTom St Denis #define mmDAC_FORCE_DATA 0x19F4 1067de2bdb3dSTom St Denis #define mmDAC_FORCE_OUTPUT_CNTL 0x19F3 1068de2bdb3dSTom St Denis #define mmDAC_MACRO_CNTL_RESERVED0 0x19FC 1069de2bdb3dSTom St Denis #define mmDAC_MACRO_CNTL_RESERVED1 0x19FD 1070de2bdb3dSTom St Denis #define mmDAC_MACRO_CNTL_RESERVED2 0x19FE 1071de2bdb3dSTom St Denis #define mmDAC_MACRO_CNTL_RESERVED3 0x19FF 1072de2bdb3dSTom St Denis #define mmDAC_MASK 0x00F1 1073de2bdb3dSTom St Denis #define mmDAC_POWERDOWN 0x19F5 1074de2bdb3dSTom St Denis #define mmDAC_PWR_CNTL 0x19F9 1075de2bdb3dSTom St Denis #define mmDAC_R_INDEX 0x00F1 1076de2bdb3dSTom St Denis #define mmDAC_SOURCE_SELECT 0x19E5 1077de2bdb3dSTom St Denis #define mmDAC_STEREOSYNC_SELECT 0x19ED 1078de2bdb3dSTom St Denis #define mmDAC_SYNC_TRISTATE_CONTROL 0x19EC 1079de2bdb3dSTom St Denis #define mmDAC_W_INDEX 0x00F2 1080de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_CNTL_MISC 0x1641 1081de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_OFFSET_SLOPE_0 0x163A 1082de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_OFFSET_SLOPE_1 0x163B 1083de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_OFFSET_SLOPE_2 0x163C 1084de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_OFFSET_SLOPE_3 0x163D 1085de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_OFFSET_SLOPE_4 0x163E 1086de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_THRES_12 0x163F 1087de2bdb3dSTom St Denis #define mmDC_ABM1_ACE_THRES_34 0x1640 1088de2bdb3dSTom St Denis #define mmDC_ABM1_BL_MASTER_LOCK 0x169C 1089de2bdb3dSTom St Denis #define mmDC_ABM1_CNTL 0x1638 1090de2bdb3dSTom St Denis #define mmDC_ABM1_DEBUG_MISC 0x1649 1091de2bdb3dSTom St Denis #define mmDC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1656 1092de2bdb3dSTom St Denis #define mmDC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1659 1093de2bdb3dSTom St Denis #define mmDC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1657 1094de2bdb3dSTom St Denis #define mmDC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x165A 1095de2bdb3dSTom St Denis #define mmDC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1658 1096de2bdb3dSTom St Denis #define mmDC_ABM1_HGLS_REG_READ_PROGRESS 0x164A 1097de2bdb3dSTom St Denis #define mmDC_ABM1_HG_MISC_CTRL 0x164B 1098de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_10 0x1664 1099de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_1 0x165B 1100de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_11 0x1665 1101de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_12 0x1666 1102de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_13 0x1667 1103de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_14 0x1668 1104de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_15 0x1669 1105de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_16 0x166A 1106de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_17 0x166B 1107de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_18 0x166C 1108de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_19 0x166D 1109de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_20 0x166E 1110de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_2 0x165C 1111de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_21 0x166F 1112de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_22 0x1670 1113de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_23 0x1671 1114de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_24 0x1672 1115de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_3 0x165D 1116de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_4 0x165E 1117de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_5 0x165F 1118de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_6 0x1660 1119de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_7 0x1661 1120de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_8 0x1662 1121de2bdb3dSTom St Denis #define mmDC_ABM1_HG_RESULT_9 0x1663 1122de2bdb3dSTom St Denis #define mmDC_ABM1_HG_SAMPLE_RATE 0x1654 1123de2bdb3dSTom St Denis #define mmDC_ABM1_IPCSC_COEFF_SEL 0x1639 1124de2bdb3dSTom St Denis #define mmDC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x164E 1125de2bdb3dSTom St Denis #define mmDC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1653 1126de2bdb3dSTom St Denis #define mmDC_ABM1_LS_MIN_MAX_LUMA 0x164D 1127de2bdb3dSTom St Denis #define mmDC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1651 1128de2bdb3dSTom St Denis #define mmDC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1652 1129de2bdb3dSTom St Denis #define mmDC_ABM1_LS_OVR_SCAN_BIN 0x1650 1130de2bdb3dSTom St Denis #define mmDC_ABM1_LS_PIXEL_COUNT 0x164F 1131de2bdb3dSTom St Denis #define mmDC_ABM1_LS_SAMPLE_RATE 0x1655 1132de2bdb3dSTom St Denis #define mmDC_ABM1_LS_SUM_OF_LUMA 0x164C 1133de2bdb3dSTom St Denis #define mmDC_ABM1_OVERSCAN_PIXEL_VALUE 0x169B 1134de2bdb3dSTom St Denis #define mmDCCG_AUDIO_DTO0_MODULE 0x016D 1135de2bdb3dSTom St Denis #define mmDCCG_AUDIO_DTO0_PHASE 0x016C 1136de2bdb3dSTom St Denis #define mmDCCG_AUDIO_DTO1_MODULE 0x0171 1137de2bdb3dSTom St Denis #define mmDCCG_AUDIO_DTO1_PHASE 0x0170 1138de2bdb3dSTom St Denis #define mmDCCG_AUDIO_DTO_SOURCE 0x016B 1139de2bdb3dSTom St Denis #define mmDCCG_CAC_STATUS 0x0137 1140de2bdb3dSTom St Denis #define mmDCCG_GATE_DISABLE_CNTL 0x0134 1141de2bdb3dSTom St Denis #define mmDCCG_GTC_CNTL 0x0120 1142de2bdb3dSTom St Denis #define mmDCCG_GTC_CURRENT 0x0123 1143de2bdb3dSTom St Denis #define mmDCCG_GTC_DTO_MODULO 0x0122 1144de2bdb3dSTom St Denis #define mmDCCG_PERFMON_CNTL 0x0133 1145de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_ANALOG 0x1708 1146de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_CNTL 0x1707 1147de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_DEBUG_CNTL 0x170B 1148de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_DISPCLK_CURRENT_DTO_PHASE 0x170F 1149de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_DISPCLK_DTO_CNTL 0x170E 1150de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_DS_CNTL 0x1705 1151de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_FB_DIV 0x1701 1152de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_IDCLK_CNTL 0x1706 1153de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_POST_DIV 0x1702 1154de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_REF_DIV 0x1700 1155de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_SS_AMOUNT_DSFRAC 0x1703 1156de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_SS_CNTL 0x1704 1157de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_UNLOCK_DETECT_CNTL 0x170A 1158de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_UPDATE_CNTL 0x170D 1159de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_UPDATE_LOCK 0x170C 1160de2bdb3dSTom St Denis #define mmDCCG_PLL0_PLL_VREG_CNTL 0x1709 1161de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_ANALOG 0x1718 1162de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_CNTL 0x1717 1163de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_DEBUG_CNTL 0x171B 1164de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_DISPCLK_CURRENT_DTO_PHASE 0x171F 1165de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_DISPCLK_DTO_CNTL 0x171E 1166de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_DS_CNTL 0x1715 1167de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_FB_DIV 0x1711 1168de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_IDCLK_CNTL 0x1716 1169de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_POST_DIV 0x1712 1170de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_REF_DIV 0x1710 1171de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_SS_AMOUNT_DSFRAC 0x1713 1172de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_SS_CNTL 0x1714 1173de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_UNLOCK_DETECT_CNTL 0x171A 1174de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_UPDATE_CNTL 0x171D 1175de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_UPDATE_LOCK 0x171C 1176de2bdb3dSTom St Denis #define mmDCCG_PLL1_PLL_VREG_CNTL 0x1719 1177de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_ANALOG 0x1728 1178de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_CNTL 0x1727 1179de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_DEBUG_CNTL 0x172B 1180de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_DISPCLK_CURRENT_DTO_PHASE 0x172F 1181de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_DISPCLK_DTO_CNTL 0x172E 1182de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_DS_CNTL 0x1725 1183de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_FB_DIV 0x1721 1184de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_IDCLK_CNTL 0x1726 1185de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_POST_DIV 0x1722 1186de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_REF_DIV 0x1720 1187de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_SS_AMOUNT_DSFRAC 0x1723 1188de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_SS_CNTL 0x1724 1189de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_UNLOCK_DETECT_CNTL 0x172A 1190de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_UPDATE_CNTL 0x172D 1191de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_UPDATE_LOCK 0x172C 1192de2bdb3dSTom St Denis #define mmDCCG_PLL2_PLL_VREG_CNTL 0x1729 1193de2bdb3dSTom St Denis #define mmDCCG_SOFT_RESET 0x015F 1194de2bdb3dSTom St Denis #define mmDCCG_TEST_CLK_SEL 0x017E 1195de2bdb3dSTom St Denis #define mmDCCG_TEST_DEBUG_DATA 0x017D 1196de2bdb3dSTom St Denis #define mmDCCG_TEST_DEBUG_INDEX 0x017C 1197de2bdb3dSTom St Denis #define mmDCCG_VPCLK_CNTL 0x031F 1198de2bdb3dSTom St Denis #define mmDCDEBUG_BUS_CLK1_SEL 0x1860 1199de2bdb3dSTom St Denis #define mmDCDEBUG_BUS_CLK2_SEL 0x1861 1200de2bdb3dSTom St Denis #define mmDCDEBUG_BUS_CLK3_SEL 0x1862 1201de2bdb3dSTom St Denis #define mmDCDEBUG_BUS_CLK4_SEL 0x1863 1202de2bdb3dSTom St Denis #define mmDCDEBUG_OUT_CNTL 0x186B 1203de2bdb3dSTom St Denis #define mmDCDEBUG_OUT_DATA 0x186E 1204de2bdb3dSTom St Denis #define mmDCDEBUG_OUT_PIN_OVERRIDE 0x186A 1205de2bdb3dSTom St Denis #define mmDC_DMCU_SCRATCH 0x1618 1206de2bdb3dSTom St Denis #define mmDC_DVODATA_CONFIG 0x1905 1207de2bdb3dSTom St Denis #define mmDCFE0_SOFT_RESET 0x0158 1208de2bdb3dSTom St Denis #define mmDCFE1_SOFT_RESET 0x0159 1209de2bdb3dSTom St Denis #define mmDCFE2_SOFT_RESET 0x015A 1210de2bdb3dSTom St Denis #define mmDCFE3_SOFT_RESET 0x015B 1211de2bdb3dSTom St Denis #define mmDCFE4_SOFT_RESET 0x015C 1212de2bdb3dSTom St Denis #define mmDCFE5_SOFT_RESET 0x015D 1213de2bdb3dSTom St Denis #define mmDCFE_DBG_SEL 0x1B7E 1214de2bdb3dSTom St Denis #define mmDCFE_MEM_LIGHT_SLEEP_CNTL 0x1B7F 1215de2bdb3dSTom St Denis #define mmDC_GENERICA 0x1900 1216de2bdb3dSTom St Denis #define mmDC_GENERICB 0x1901 1217de2bdb3dSTom St Denis #define mmDC_GPIO_DDC1_A 0x194D 1218de2bdb3dSTom St Denis #define mmDC_GPIO_DDC1_EN 0x194E 1219de2bdb3dSTom St Denis #define mmDC_GPIO_DDC1_MASK 0x194C 1220de2bdb3dSTom St Denis #define mmDC_GPIO_DDC1_Y 0x194F 1221de2bdb3dSTom St Denis #define mmDC_GPIO_DDC2_A 0x1951 1222de2bdb3dSTom St Denis #define mmDC_GPIO_DDC2_EN 0x1952 1223de2bdb3dSTom St Denis #define mmDC_GPIO_DDC2_MASK 0x1950 1224de2bdb3dSTom St Denis #define mmDC_GPIO_DDC2_Y 0x1953 1225de2bdb3dSTom St Denis #define mmDC_GPIO_DDC3_A 0x1955 1226de2bdb3dSTom St Denis #define mmDC_GPIO_DDC3_EN 0x1956 1227de2bdb3dSTom St Denis #define mmDC_GPIO_DDC3_MASK 0x1954 1228de2bdb3dSTom St Denis #define mmDC_GPIO_DDC3_Y 0x1957 1229de2bdb3dSTom St Denis #define mmDC_GPIO_DDC4_A 0x1959 1230de2bdb3dSTom St Denis #define mmDC_GPIO_DDC4_EN 0x195A 1231de2bdb3dSTom St Denis #define mmDC_GPIO_DDC4_MASK 0x1958 1232de2bdb3dSTom St Denis #define mmDC_GPIO_DDC4_Y 0x195B 1233de2bdb3dSTom St Denis #define mmDC_GPIO_DDC5_A 0x195D 1234de2bdb3dSTom St Denis #define mmDC_GPIO_DDC5_EN 0x195E 1235de2bdb3dSTom St Denis #define mmDC_GPIO_DDC5_MASK 0x195C 1236de2bdb3dSTom St Denis #define mmDC_GPIO_DDC5_Y 0x195F 1237de2bdb3dSTom St Denis #define mmDC_GPIO_DDC6_A 0x1961 1238de2bdb3dSTom St Denis #define mmDC_GPIO_DDC6_EN 0x1962 1239de2bdb3dSTom St Denis #define mmDC_GPIO_DDC6_MASK 0x1960 1240de2bdb3dSTom St Denis #define mmDC_GPIO_DDC6_Y 0x1963 1241de2bdb3dSTom St Denis #define mmDC_GPIO_DDCVGA_A 0x1971 1242de2bdb3dSTom St Denis #define mmDC_GPIO_DDCVGA_EN 0x1972 1243de2bdb3dSTom St Denis #define mmDC_GPIO_DDCVGA_MASK 0x1970 1244de2bdb3dSTom St Denis #define mmDC_GPIO_DDCVGA_Y 0x1973 1245de2bdb3dSTom St Denis #define mmDC_GPIO_DEBUG 0x1904 1246de2bdb3dSTom St Denis #define mmDC_GPIO_DVODATA_A 0x1949 1247de2bdb3dSTom St Denis #define mmDC_GPIO_DVODATA_EN 0x194A 1248de2bdb3dSTom St Denis #define mmDC_GPIO_DVODATA_MASK 0x1948 1249de2bdb3dSTom St Denis #define mmDC_GPIO_DVODATA_Y 0x194B 1250de2bdb3dSTom St Denis #define mmDC_GPIO_GENERIC_A 0x1945 1251de2bdb3dSTom St Denis #define mmDC_GPIO_GENERIC_EN 0x1946 1252de2bdb3dSTom St Denis #define mmDC_GPIO_GENERIC_MASK 0x1944 1253de2bdb3dSTom St Denis #define mmDC_GPIO_GENERIC_Y 0x1947 1254de2bdb3dSTom St Denis #define mmDC_GPIO_GENLK_A 0x1969 1255de2bdb3dSTom St Denis #define mmDC_GPIO_GENLK_EN 0x196A 1256de2bdb3dSTom St Denis #define mmDC_GPIO_GENLK_MASK 0x1968 1257de2bdb3dSTom St Denis #define mmDC_GPIO_GENLK_Y 0x196B 1258de2bdb3dSTom St Denis #define mmDC_GPIO_HPD_A 0x196D 1259de2bdb3dSTom St Denis #define mmDC_GPIO_HPD_EN 0x196E 1260de2bdb3dSTom St Denis #define mmDC_GPIO_HPD_MASK 0x196C 1261de2bdb3dSTom St Denis #define mmDC_GPIO_HPD_Y 0x196F 1262de2bdb3dSTom St Denis #define mmDC_GPIO_I2CPAD_A 0x1975 1263de2bdb3dSTom St Denis #define mmDC_GPIO_I2CPAD_EN 0x1976 1264de2bdb3dSTom St Denis #define mmDC_GPIO_I2CPAD_MASK 0x1974 1265de2bdb3dSTom St Denis #define mmDC_GPIO_I2CPAD_STRENGTH 0x197A 1266de2bdb3dSTom St Denis #define mmDC_GPIO_I2CPAD_Y 0x1977 1267de2bdb3dSTom St Denis #define mmDC_GPIO_PAD_STRENGTH_1 0x1978 1268de2bdb3dSTom St Denis #define mmDC_GPIO_PAD_STRENGTH_2 0x1979 1269de2bdb3dSTom St Denis #define mmDC_GPIO_PWRSEQ_A 0x1941 1270de2bdb3dSTom St Denis #define mmDC_GPIO_PWRSEQ_EN 0x1942 1271de2bdb3dSTom St Denis #define mmDC_GPIO_PWRSEQ_MASK 0x1940 1272de2bdb3dSTom St Denis #define mmDC_GPIO_PWRSEQ_Y 0x1943 1273de2bdb3dSTom St Denis #define mmDC_GPIO_SYNCA_A 0x1965 1274de2bdb3dSTom St Denis #define mmDC_GPIO_SYNCA_EN 0x1966 1275de2bdb3dSTom St Denis #define mmDC_GPIO_SYNCA_MASK 0x1964 1276de2bdb3dSTom St Denis #define mmDC_GPIO_SYNCA_Y 0x1967 1277de2bdb3dSTom St Denis #define mmDC_GPU_TIMER_READ 0x1929 1278de2bdb3dSTom St Denis #define mmDC_GPU_TIMER_READ_CNTL 0x192A 1279de2bdb3dSTom St Denis #define mmDC_GPU_TIMER_START_POSITION_P_FLIP 0x1928 1280de2bdb3dSTom St Denis #define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x1927 1281de2bdb3dSTom St Denis #define mmDC_HPD1_CONTROL 0x1809 1282de2bdb3dSTom St Denis #define mmDC_HPD1_FAST_TRAIN_CNTL 0x1864 1283de2bdb3dSTom St Denis #define mmDC_HPD1_INT_CONTROL 0x1808 1284de2bdb3dSTom St Denis #define mmDC_HPD1_INT_STATUS 0x1807 1285de2bdb3dSTom St Denis #define mmDC_HPD1_TOGGLE_FILT_CNTL 0x18BC 1286de2bdb3dSTom St Denis #define mmDC_HPD2_CONTROL 0x180C 1287de2bdb3dSTom St Denis #define mmDC_HPD2_FAST_TRAIN_CNTL 0x1865 1288de2bdb3dSTom St Denis #define mmDC_HPD2_INT_CONTROL 0x180B 1289de2bdb3dSTom St Denis #define mmDC_HPD2_INT_STATUS 0x180A 1290de2bdb3dSTom St Denis #define mmDC_HPD2_TOGGLE_FILT_CNTL 0x18BD 1291de2bdb3dSTom St Denis #define mmDC_HPD3_CONTROL 0x180F 1292de2bdb3dSTom St Denis #define mmDC_HPD3_FAST_TRAIN_CNTL 0x1866 1293de2bdb3dSTom St Denis #define mmDC_HPD3_INT_CONTROL 0x180E 1294de2bdb3dSTom St Denis #define mmDC_HPD3_INT_STATUS 0x180D 1295de2bdb3dSTom St Denis #define mmDC_HPD3_TOGGLE_FILT_CNTL 0x18BE 1296de2bdb3dSTom St Denis #define mmDC_HPD4_CONTROL 0x1812 1297de2bdb3dSTom St Denis #define mmDC_HPD4_FAST_TRAIN_CNTL 0x1867 1298de2bdb3dSTom St Denis #define mmDC_HPD4_INT_CONTROL 0x1811 1299de2bdb3dSTom St Denis #define mmDC_HPD4_INT_STATUS 0x1810 1300de2bdb3dSTom St Denis #define mmDC_HPD4_TOGGLE_FILT_CNTL 0x18FC 1301de2bdb3dSTom St Denis #define mmDC_HPD5_CONTROL 0x1815 1302de2bdb3dSTom St Denis #define mmDC_HPD5_FAST_TRAIN_CNTL 0x1868 1303de2bdb3dSTom St Denis #define mmDC_HPD5_INT_CONTROL 0x1814 1304de2bdb3dSTom St Denis #define mmDC_HPD5_INT_STATUS 0x1813 1305de2bdb3dSTom St Denis #define mmDC_HPD5_TOGGLE_FILT_CNTL 0x18FD 1306de2bdb3dSTom St Denis #define mmDC_HPD6_CONTROL 0x1818 1307de2bdb3dSTom St Denis #define mmDC_HPD6_FAST_TRAIN_CNTL 0x1869 1308de2bdb3dSTom St Denis #define mmDC_HPD6_INT_CONTROL 0x1817 1309de2bdb3dSTom St Denis #define mmDC_HPD6_INT_STATUS 0x1816 1310de2bdb3dSTom St Denis #define mmDC_HPD6_TOGGLE_FILT_CNTL 0x18FE 1311de2bdb3dSTom St Denis #define mmDC_I2C_ARBITRATION 0x181A 1312de2bdb3dSTom St Denis #define mmDC_I2C_CONTROL 0x1819 1313de2bdb3dSTom St Denis #define mmDC_I2C_DATA 0x1833 1314de2bdb3dSTom St Denis #define mmDC_I2C_DDC1_HW_STATUS 0x181D 1315de2bdb3dSTom St Denis #define mmDC_I2C_DDC1_SETUP 0x1824 1316de2bdb3dSTom St Denis #define mmDC_I2C_DDC1_SPEED 0x1823 1317de2bdb3dSTom St Denis #define mmDC_I2C_DDC2_HW_STATUS 0x181E 1318de2bdb3dSTom St Denis #define mmDC_I2C_DDC2_SETUP 0x1826 1319de2bdb3dSTom St Denis #define mmDC_I2C_DDC2_SPEED 0x1825 1320de2bdb3dSTom St Denis #define mmDC_I2C_DDC3_HW_STATUS 0x181F 1321de2bdb3dSTom St Denis #define mmDC_I2C_DDC3_SETUP 0x1828 1322de2bdb3dSTom St Denis #define mmDC_I2C_DDC3_SPEED 0x1827 1323de2bdb3dSTom St Denis #define mmDC_I2C_DDC4_HW_STATUS 0x1820 1324de2bdb3dSTom St Denis #define mmDC_I2C_DDC4_SETUP 0x182A 1325de2bdb3dSTom St Denis #define mmDC_I2C_DDC4_SPEED 0x1829 1326de2bdb3dSTom St Denis #define mmDC_I2C_DDC5_HW_STATUS 0x1821 1327de2bdb3dSTom St Denis #define mmDC_I2C_DDC5_SETUP 0x182C 1328de2bdb3dSTom St Denis #define mmDC_I2C_DDC5_SPEED 0x182B 1329de2bdb3dSTom St Denis #define mmDC_I2C_DDC6_HW_STATUS 0x1822 1330de2bdb3dSTom St Denis #define mmDC_I2C_DDC6_SETUP 0x182E 1331de2bdb3dSTom St Denis #define mmDC_I2C_DDC6_SPEED 0x182D 1332de2bdb3dSTom St Denis #define mmDC_I2C_DDCVGA_HW_STATUS 0x1855 1333de2bdb3dSTom St Denis #define mmDC_I2C_DDCVGA_SETUP 0x1857 1334de2bdb3dSTom St Denis #define mmDC_I2C_DDCVGA_SPEED 0x1856 1335de2bdb3dSTom St Denis #define mmDC_I2C_EDID_DETECT_CTRL 0x186F 1336de2bdb3dSTom St Denis #define mmDC_I2C_INTERRUPT_CONTROL 0x181B 1337de2bdb3dSTom St Denis #define mmDC_I2C_SW_STATUS 0x181C 1338de2bdb3dSTom St Denis #define mmDC_I2C_TRANSACTION0 0x182F 1339de2bdb3dSTom St Denis #define mmDC_I2C_TRANSACTION1 0x1830 1340de2bdb3dSTom St Denis #define mmDC_I2C_TRANSACTION2 0x1831 1341de2bdb3dSTom St Denis #define mmDC_I2C_TRANSACTION3 0x1832 1342de2bdb3dSTom St Denis #define mmDCI_CLK_CNTL 0x031E 1343de2bdb3dSTom St Denis #define mmDCI_CLK_RAMP_CNTL 0x0324 1344de2bdb3dSTom St Denis #define mmDCI_DEBUG_CONFIG 0x0323 1345de2bdb3dSTom St Denis #define mmDCI_MEM_PWR_CNTL 0x0326 1346de2bdb3dSTom St Denis #define mmDCI_MEM_PWR_STATE 0x031B 1347de2bdb3dSTom St Denis #define mmDCI_MEM_PWR_STATE2 0x0322 1348de2bdb3dSTom St Denis #define mmDCIO_DEBUG 0x192E 1349de2bdb3dSTom St Denis #define mmDCIO_GSL0_CNTL 0x1924 1350de2bdb3dSTom St Denis #define mmDCIO_GSL1_CNTL 0x1925 1351de2bdb3dSTom St Denis #define mmDCIO_GSL2_CNTL 0x1926 1352de2bdb3dSTom St Denis #define mmDCIO_GSL_GENLK_PAD_CNTL 0x1922 1353de2bdb3dSTom St Denis #define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x1923 1354de2bdb3dSTom St Denis #define mmDCIO_IMPCAL_CNTL_AB 0x190D 1355de2bdb3dSTom St Denis #define mmDCIO_IMPCAL_CNTL_CD 0x1911 1356de2bdb3dSTom St Denis #define mmDCIO_IMPCAL_CNTL_EF 0x1915 1357de2bdb3dSTom St Denis #define mmDCIO_TEST_DEBUG_DATA 0x1930 1358de2bdb3dSTom St Denis #define mmDCIO_TEST_DEBUG_INDEX 0x192F 1359de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_ANG_BIST_CNTL 0x198C 1360de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_CHANNEL_XBAR_CNTL 0x198E 1361de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_DATA_SYNCHRONIZATION 0x198A 1362de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_LINK_CNTL 0x198D 1363de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL1 0x1986 1364de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_PLL_CONTROL2 0x1987 1365de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_PLL_FBDIV 0x1985 1366de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_CNTL 0x1989 1367de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_PLL_SS_STEP_SIZE 0x1988 1368de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_POWER_CONTROL 0x1984 1369de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_REG_TEST_OUTPUT 0x198B 1370de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL1 0x1980 1371de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL2 0x1981 1372de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL3 0x1982 1373de2bdb3dSTom St Denis #define mmDCIO_UNIPHY0_UNIPHY_TX_CONTROL4 0x1983 1374de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_ANG_BIST_CNTL 0x199C 1375de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_CHANNEL_XBAR_CNTL 0x199E 1376de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_DATA_SYNCHRONIZATION 0x199A 1377de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_LINK_CNTL 0x199D 1378de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL1 0x1996 1379de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_PLL_CONTROL2 0x1997 1380de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_PLL_FBDIV 0x1995 1381de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_CNTL 0x1999 1382de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_PLL_SS_STEP_SIZE 0x1998 1383de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_POWER_CONTROL 0x1994 1384de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_REG_TEST_OUTPUT 0x199B 1385de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL1 0x1990 1386de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL2 0x1991 1387de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL3 0x1992 1388de2bdb3dSTom St Denis #define mmDCIO_UNIPHY1_UNIPHY_TX_CONTROL4 0x1993 1389de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_ANG_BIST_CNTL 0x19AC 1390de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_CHANNEL_XBAR_CNTL 0x19AE 1391de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_DATA_SYNCHRONIZATION 0x19AA 1392de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_LINK_CNTL 0x19AD 1393de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL1 0x19A6 1394de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_PLL_CONTROL2 0x19A7 1395de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_PLL_FBDIV 0x19A5 1396de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_CNTL 0x19A9 1397de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_PLL_SS_STEP_SIZE 0x19A8 1398de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_POWER_CONTROL 0x19A4 1399de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_REG_TEST_OUTPUT 0x19AB 1400de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL1 0x19A0 1401de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL2 0x19A1 1402de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL3 0x19A2 1403de2bdb3dSTom St Denis #define mmDCIO_UNIPHY2_UNIPHY_TX_CONTROL4 0x19A3 1404de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_ANG_BIST_CNTL 0x19BC 1405de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_CHANNEL_XBAR_CNTL 0x19BE 1406de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_DATA_SYNCHRONIZATION 0x19BA 1407de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_LINK_CNTL 0x19BD 1408de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL1 0x19B6 1409de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_PLL_CONTROL2 0x19B7 1410de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_PLL_FBDIV 0x19B5 1411de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_CNTL 0x19B9 1412de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_PLL_SS_STEP_SIZE 0x19B8 1413de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_POWER_CONTROL 0x19B4 1414de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_REG_TEST_OUTPUT 0x19BB 1415de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL1 0x19B0 1416de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL2 0x19B1 1417de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL3 0x19B2 1418de2bdb3dSTom St Denis #define mmDCIO_UNIPHY3_UNIPHY_TX_CONTROL4 0x19B3 1419de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_ANG_BIST_CNTL 0x19CC 1420de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_CHANNEL_XBAR_CNTL 0x19CE 1421de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_DATA_SYNCHRONIZATION 0x19CA 1422de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_LINK_CNTL 0x19CD 1423de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL1 0x19C6 1424de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_PLL_CONTROL2 0x19C7 1425de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_PLL_FBDIV 0x19C5 1426de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_CNTL 0x19C9 1427de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_PLL_SS_STEP_SIZE 0x19C8 1428de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_POWER_CONTROL 0x19C4 1429de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_REG_TEST_OUTPUT 0x19CB 1430de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL1 0x19C0 1431de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL2 0x19C1 1432de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL3 0x19C2 1433de2bdb3dSTom St Denis #define mmDCIO_UNIPHY4_UNIPHY_TX_CONTROL4 0x19C3 1434de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_ANG_BIST_CNTL 0x19DC 1435de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_CHANNEL_XBAR_CNTL 0x19DE 1436de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_DATA_SYNCHRONIZATION 0x19DA 1437de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_LINK_CNTL 0x19DD 1438de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL1 0x19D6 1439de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_PLL_CONTROL2 0x19D7 1440de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_PLL_FBDIV 0x19D5 1441de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_CNTL 0x19D9 1442de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_PLL_SS_STEP_SIZE 0x19D8 1443de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_POWER_CONTROL 0x19D4 1444de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_REG_TEST_OUTPUT 0x19DB 1445de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL1 0x19D0 1446de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL2 0x19D1 1447de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL3 0x19D2 1448de2bdb3dSTom St Denis #define mmDCIO_UNIPHY5_UNIPHY_TX_CONTROL4 0x19D3 1449de2bdb3dSTom St Denis #define mmDCI_SOFT_RESET 0x015E 1450de2bdb3dSTom St Denis #define mmDCI_TEST_DEBUG_DATA 0x0321 1451de2bdb3dSTom St Denis #define mmDCI_TEST_DEBUG_INDEX 0x0320 1452de2bdb3dSTom St Denis #define mmDC_LUT_30_COLOR 0x1A7C 1453de2bdb3dSTom St Denis #define mmDC_LUT_AUTOFILL 0x1A7F 1454de2bdb3dSTom St Denis #define mmDC_LUT_BLACK_OFFSET_BLUE 0x1A81 1455de2bdb3dSTom St Denis #define mmDC_LUT_BLACK_OFFSET_GREEN 0x1A82 1456de2bdb3dSTom St Denis #define mmDC_LUT_BLACK_OFFSET_RED 0x1A83 1457de2bdb3dSTom St Denis #define mmDC_LUT_CONTROL 0x1A80 1458de2bdb3dSTom St Denis #define mmDC_LUT_PWL_DATA 0x1A7B 1459de2bdb3dSTom St Denis #define mmDC_LUT_RW_INDEX 0x1A79 1460de2bdb3dSTom St Denis #define mmDC_LUT_RW_MODE 0x1A78 1461de2bdb3dSTom St Denis #define mmDC_LUT_SEQ_COLOR 0x1A7A 1462de2bdb3dSTom St Denis #define mmDC_LUT_VGA_ACCESS_ENABLE 0x1A7D 1463de2bdb3dSTom St Denis #define mmDC_LUT_WHITE_OFFSET_BLUE 0x1A84 1464de2bdb3dSTom St Denis #define mmDC_LUT_WHITE_OFFSET_GREEN 0x1A85 1465de2bdb3dSTom St Denis #define mmDC_LUT_WHITE_OFFSET_RED 0x1A86 1466de2bdb3dSTom St Denis #define mmDC_LUT_WRITE_EN_MASK 0x1A7E 1467de2bdb3dSTom St Denis #define mmDC_MVP_LB_CONTROL 0x1ADB 1468de2bdb3dSTom St Denis #define mmDCO_CLK_CNTL 0x192B 1469de2bdb3dSTom St Denis #define mmDCO_CLK_RAMP_CNTL 0x192C 1470de2bdb3dSTom St Denis #define mmDCO_LIGHT_SLEEP_DIS 0x1907 1471de2bdb3dSTom St Denis #define mmDCO_MEM_POWER_STATE 0x1906 1472de2bdb3dSTom St Denis #define mmDCO_SOFT_RESET 0x0167 1473de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXA_TRANS_C11_C12 0x1A43 1474de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXA_TRANS_C13_C14 0x1A44 1475de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXA_TRANS_C21_C22 0x1A45 1476de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXA_TRANS_C23_C24 0x1A46 1477de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXA_TRANS_C31_C32 0x1A47 1478de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXA_TRANS_C33_C34 0x1A48 1479de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXB_TRANS_C11_C12 0x1A49 1480de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXB_TRANS_C13_C14 0x1A4A 1481de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXB_TRANS_C21_C22 0x1A4B 1482de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXB_TRANS_C23_C24 0x1A4C 1483de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXB_TRANS_C31_C32 0x1A4D 1484de2bdb3dSTom St Denis #define mmDCP0_COMM_MATRIXB_TRANS_C33_C34 0x1A4E 1485de2bdb3dSTom St Denis #define mmDCP0_CUR_COLOR1 0x1A6C 1486de2bdb3dSTom St Denis #define mmDCP0_CUR_COLOR2 0x1A6D 1487de2bdb3dSTom St Denis #define mmDCP0_CUR_CONTROL 0x1A66 1488de2bdb3dSTom St Denis #define mmDCP0_CUR_HOT_SPOT 0x1A6B 1489de2bdb3dSTom St Denis #define mmDCP0_CUR_POSITION 0x1A6A 1490de2bdb3dSTom St Denis #define mmDCP0_CUR_REQUEST_FILTER_CNTL 0x1A99 1491de2bdb3dSTom St Denis #define mmDCP0_CUR_SIZE 0x1A68 1492de2bdb3dSTom St Denis #define mmDCP0_CUR_SURFACE_ADDRESS 0x1A67 1493de2bdb3dSTom St Denis #define mmDCP0_CUR_SURFACE_ADDRESS_HIGH 0x1A69 1494de2bdb3dSTom St Denis #define mmDCP0_CUR_UPDATE 0x1A6E 1495de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_30_COLOR 0x1A7C 1496de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_AUTOFILL 0x1A7F 1497de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_BLACK_OFFSET_BLUE 0x1A81 1498de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_BLACK_OFFSET_GREEN 0x1A82 1499de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_BLACK_OFFSET_RED 0x1A83 1500de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_CONTROL 0x1A80 1501de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_PWL_DATA 0x1A7B 1502de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_RW_INDEX 0x1A79 1503de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_RW_MODE 0x1A78 1504de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_SEQ_COLOR 0x1A7A 1505de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_VGA_ACCESS_ENABLE 0x1A7D 1506de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_WHITE_OFFSET_BLUE 0x1A84 1507de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_WHITE_OFFSET_GREEN 0x1A85 1508de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_WHITE_OFFSET_RED 0x1A86 1509de2bdb3dSTom St Denis #define mmDCP0_DC_LUT_WRITE_EN_MASK 0x1A7E 1510de2bdb3dSTom St Denis #define mmDCP0_DCP_CRC_CONTROL 0x1A87 1511de2bdb3dSTom St Denis #define mmDCP0_DCP_CRC_CURRENT 0x1A89 1512de2bdb3dSTom St Denis #define mmDCP0_DCP_CRC_LAST 0x1A8B 1513de2bdb3dSTom St Denis #define mmDCP0_DCP_CRC_MASK 0x1A88 1514de2bdb3dSTom St Denis #define mmDCP0_DCP_DEBUG 0x1A8D 1515de2bdb3dSTom St Denis #define mmDCP0_DCP_DEBUG2 0x1A98 1516de2bdb3dSTom St Denis #define mmDCP0_DCP_FP_CONVERTED_FIELD 0x1A65 1517de2bdb3dSTom St Denis #define mmDCP0_DCP_GSL_CONTROL 0x1A90 1518de2bdb3dSTom St Denis #define mmDCP0_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 1519de2bdb3dSTom St Denis #define mmDCP0_DCP_RANDOM_SEEDS 0x1A61 1520de2bdb3dSTom St Denis #define mmDCP0_DCP_SPATIAL_DITHER_CNTL 0x1A60 1521de2bdb3dSTom St Denis #define mmDCP0_DCP_TEST_DEBUG_DATA 0x1A96 1522de2bdb3dSTom St Denis #define mmDCP0_DCP_TEST_DEBUG_INDEX 0x1A95 1523de2bdb3dSTom St Denis #define mmDCP0_DEGAMMA_CONTROL 0x1A58 1524de2bdb3dSTom St Denis #define mmDCP0_DENORM_CONTROL 0x1A50 1525de2bdb3dSTom St Denis #define mmDCP0_GAMUT_REMAP_C11_C12 0x1A5A 1526de2bdb3dSTom St Denis #define mmDCP0_GAMUT_REMAP_C13_C14 0x1A5B 1527de2bdb3dSTom St Denis #define mmDCP0_GAMUT_REMAP_C21_C22 0x1A5C 1528de2bdb3dSTom St Denis #define mmDCP0_GAMUT_REMAP_C23_C24 0x1A5D 1529de2bdb3dSTom St Denis #define mmDCP0_GAMUT_REMAP_C31_C32 0x1A5E 1530de2bdb3dSTom St Denis #define mmDCP0_GAMUT_REMAP_C33_C34 0x1A5F 1531de2bdb3dSTom St Denis #define mmDCP0_GAMUT_REMAP_CONTROL 0x1A59 1532de2bdb3dSTom St Denis #define mmDCP0_GRPH_COMPRESS_PITCH 0x1A1A 1533de2bdb3dSTom St Denis #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 1534de2bdb3dSTom St Denis #define mmDCP0_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B 1535de2bdb3dSTom St Denis #define mmDCP0_GRPH_CONTROL 0x1A01 1536de2bdb3dSTom St Denis #define mmDCP0_GRPH_DFQ_CONTROL 0x1A14 1537de2bdb3dSTom St Denis #define mmDCP0_GRPH_DFQ_STATUS 0x1A15 1538de2bdb3dSTom St Denis #define mmDCP0_GRPH_ENABLE 0x1A00 1539de2bdb3dSTom St Denis #define mmDCP0_GRPH_FLIP_CONTROL 0x1A12 1540de2bdb3dSTom St Denis #define mmDCP0_GRPH_INTERRUPT_CONTROL 0x1A17 1541de2bdb3dSTom St Denis #define mmDCP0_GRPH_INTERRUPT_STATUS 0x1A16 1542de2bdb3dSTom St Denis #define mmDCP0_GRPH_LUT_10BIT_BYPASS 0x1A02 1543de2bdb3dSTom St Denis #define mmDCP0_GRPH_PITCH 0x1A06 1544de2bdb3dSTom St Denis #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 1545de2bdb3dSTom St Denis #define mmDCP0_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 1546de2bdb3dSTom St Denis #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 1547de2bdb3dSTom St Denis #define mmDCP0_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 1548de2bdb3dSTom St Denis #define mmDCP0_GRPH_STEREOSYNC_FLIP 0x1A97 1549de2bdb3dSTom St Denis #define mmDCP0_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 1550de2bdb3dSTom St Denis #define mmDCP0_GRPH_SURFACE_ADDRESS_INUSE 0x1A13 1551de2bdb3dSTom St Denis #define mmDCP0_GRPH_SURFACE_OFFSET_X 0x1A09 1552de2bdb3dSTom St Denis #define mmDCP0_GRPH_SURFACE_OFFSET_Y 0x1A0A 1553de2bdb3dSTom St Denis #define mmDCP0_GRPH_SWAP_CNTL 0x1A03 1554de2bdb3dSTom St Denis #define mmDCP0_GRPH_UPDATE 0x1A11 1555de2bdb3dSTom St Denis #define mmDCP0_GRPH_X_END 0x1A0D 1556de2bdb3dSTom St Denis #define mmDCP0_GRPH_X_START 0x1A0B 1557de2bdb3dSTom St Denis #define mmDCP0_GRPH_Y_END 0x1A0E 1558de2bdb3dSTom St Denis #define mmDCP0_GRPH_Y_START 0x1A0C 1559de2bdb3dSTom St Denis #define mmDCP0_INPUT_CSC_C11_C12 0x1A36 1560de2bdb3dSTom St Denis #define mmDCP0_INPUT_CSC_C13_C14 0x1A37 1561de2bdb3dSTom St Denis #define mmDCP0_INPUT_CSC_C21_C22 0x1A38 1562de2bdb3dSTom St Denis #define mmDCP0_INPUT_CSC_C23_C24 0x1A39 1563de2bdb3dSTom St Denis #define mmDCP0_INPUT_CSC_C31_C32 0x1A3A 1564de2bdb3dSTom St Denis #define mmDCP0_INPUT_CSC_C33_C34 0x1A3B 1565de2bdb3dSTom St Denis #define mmDCP0_INPUT_CSC_CONTROL 0x1A35 1566de2bdb3dSTom St Denis #define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10 1567de2bdb3dSTom St Denis #define mmDCP0_KEY_CONTROL 0x1A53 1568de2bdb3dSTom St Denis #define mmDCP0_KEY_RANGE_ALPHA 0x1A54 1569de2bdb3dSTom St Denis #define mmDCP0_KEY_RANGE_BLUE 0x1A57 1570de2bdb3dSTom St Denis #define mmDCP0_KEY_RANGE_GREEN 0x1A56 1571de2bdb3dSTom St Denis #define mmDCP0_KEY_RANGE_RED 0x1A55 1572de2bdb3dSTom St Denis #define mmDCP0_OUTPUT_CSC_C11_C12 0x1A3D 1573de2bdb3dSTom St Denis #define mmDCP0_OUTPUT_CSC_C13_C14 0x1A3E 1574de2bdb3dSTom St Denis #define mmDCP0_OUTPUT_CSC_C21_C22 0x1A3F 1575de2bdb3dSTom St Denis #define mmDCP0_OUTPUT_CSC_C23_C24 0x1A40 1576de2bdb3dSTom St Denis #define mmDCP0_OUTPUT_CSC_C31_C32 0x1A41 1577de2bdb3dSTom St Denis #define mmDCP0_OUTPUT_CSC_C33_C34 0x1A42 1578de2bdb3dSTom St Denis #define mmDCP0_OUTPUT_CSC_CONTROL 0x1A3C 1579de2bdb3dSTom St Denis #define mmDCP0_OUT_ROUND_CONTROL 0x1A51 1580de2bdb3dSTom St Denis #define mmDCP0_OVL_CONTROL1 0x1A1D 1581de2bdb3dSTom St Denis #define mmDCP0_OVL_CONTROL2 0x1A1E 1582de2bdb3dSTom St Denis #define mmDCP0_OVL_DFQ_CONTROL 0x1A29 1583de2bdb3dSTom St Denis #define mmDCP0_OVL_DFQ_STATUS 0x1A2A 1584de2bdb3dSTom St Denis #define mmDCP0_OVL_ENABLE 0x1A1C 1585de2bdb3dSTom St Denis #define mmDCP0_OVL_END 0x1A26 1586de2bdb3dSTom St Denis #define mmDCP0_OVL_PITCH 0x1A21 1587de2bdb3dSTom St Denis #define mmDCP0_OVLSCL_EDGE_PIXEL_CNTL 0x1A2C 1588de2bdb3dSTom St Denis #define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS 0x1A92 1589de2bdb3dSTom St Denis #define mmDCP0_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 1590de2bdb3dSTom St Denis #define mmDCP0_OVL_START 0x1A25 1591de2bdb3dSTom St Denis #define mmDCP0_OVL_STEREOSYNC_FLIP 0x1A93 1592de2bdb3dSTom St Denis #define mmDCP0_OVL_SURFACE_ADDRESS 0x1A20 1593de2bdb3dSTom St Denis #define mmDCP0_OVL_SURFACE_ADDRESS_HIGH 0x1A22 1594de2bdb3dSTom St Denis #define mmDCP0_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B 1595de2bdb3dSTom St Denis #define mmDCP0_OVL_SURFACE_ADDRESS_INUSE 0x1A28 1596de2bdb3dSTom St Denis #define mmDCP0_OVL_SURFACE_OFFSET_X 0x1A23 1597de2bdb3dSTom St Denis #define mmDCP0_OVL_SURFACE_OFFSET_Y 0x1A24 1598de2bdb3dSTom St Denis #define mmDCP0_OVL_SWAP_CNTL 0x1A1F 1599de2bdb3dSTom St Denis #define mmDCP0_OVL_UPDATE 0x1A27 1600de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_GRPH_CONTROL 0x1A2D 1601de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_OVL_CONTROL 0x1A31 1602de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_VALUES_GRPH_B 0x1A30 1603de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_VALUES_GRPH_G 0x1A2F 1604de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_VALUES_GRPH_R 0x1A2E 1605de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_VALUES_OVL_CB 0x1A32 1606de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_VALUES_OVL_CR 0x1A34 1607de2bdb3dSTom St Denis #define mmDCP0_PRESCALE_VALUES_OVL_Y 0x1A33 1608de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_END_CNTL1 0x1AA6 1609de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_END_CNTL2 0x1AA7 1610de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_0_1 0x1AA8 1611de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_10_11 0x1AAD 1612de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_12_13 0x1AAE 1613de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_14_15 0x1AAF 1614de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_2_3 0x1AA9 1615de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_4_5 0x1AAA 1616de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_6_7 0x1AAB 1617de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_REGION_8_9 0x1AAC 1618de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 1619de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLA_START_CNTL 0x1AA4 1620de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_END_CNTL1 0x1AB2 1621de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_END_CNTL2 0x1AB3 1622de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_0_1 0x1AB4 1623de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_10_11 0x1AB9 1624de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_12_13 0x1ABA 1625de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_14_15 0x1ABB 1626de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_2_3 0x1AB5 1627de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_4_5 0x1AB6 1628de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_6_7 0x1AB7 1629de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_REGION_8_9 0x1AB8 1630de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 1631de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CNTLB_START_CNTL 0x1AB0 1632de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_CONTROL 0x1AA0 1633de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_LUT_DATA 0x1AA2 1634de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_LUT_INDEX 0x1AA1 1635de2bdb3dSTom St Denis #define mmDCP0_REGAMMA_LUT_WRITE_EN_MASK 0x1AA3 1636de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXA_TRANS_C11_C12 0x1D43 1637de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXA_TRANS_C13_C14 0x1D44 1638de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXA_TRANS_C21_C22 0x1D45 1639de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXA_TRANS_C23_C24 0x1D46 1640de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXA_TRANS_C31_C32 0x1D47 1641de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXA_TRANS_C33_C34 0x1D48 1642de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXB_TRANS_C11_C12 0x1D49 1643de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXB_TRANS_C13_C14 0x1D4A 1644de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXB_TRANS_C21_C22 0x1D4B 1645de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXB_TRANS_C23_C24 0x1D4C 1646de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXB_TRANS_C31_C32 0x1D4D 1647de2bdb3dSTom St Denis #define mmDCP1_COMM_MATRIXB_TRANS_C33_C34 0x1D4E 1648de2bdb3dSTom St Denis #define mmDCP1_CUR_COLOR1 0x1D6C 1649de2bdb3dSTom St Denis #define mmDCP1_CUR_COLOR2 0x1D6D 1650de2bdb3dSTom St Denis #define mmDCP1_CUR_CONTROL 0x1D66 1651de2bdb3dSTom St Denis #define mmDCP1_CUR_HOT_SPOT 0x1D6B 1652de2bdb3dSTom St Denis #define mmDCP1_CUR_POSITION 0x1D6A 1653de2bdb3dSTom St Denis #define mmDCP1_CUR_REQUEST_FILTER_CNTL 0x1D99 1654de2bdb3dSTom St Denis #define mmDCP1_CUR_SIZE 0x1D68 1655de2bdb3dSTom St Denis #define mmDCP1_CUR_SURFACE_ADDRESS 0x1D67 1656de2bdb3dSTom St Denis #define mmDCP1_CUR_SURFACE_ADDRESS_HIGH 0x1D69 1657de2bdb3dSTom St Denis #define mmDCP1_CUR_UPDATE 0x1D6E 1658de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_30_COLOR 0x1D7C 1659de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_AUTOFILL 0x1D7F 1660de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_BLACK_OFFSET_BLUE 0x1D81 1661de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_BLACK_OFFSET_GREEN 0x1D82 1662de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_BLACK_OFFSET_RED 0x1D83 1663de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_CONTROL 0x1D80 1664de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_PWL_DATA 0x1D7B 1665de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_RW_INDEX 0x1D79 1666de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_RW_MODE 0x1D78 1667de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_SEQ_COLOR 0x1D7A 1668de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_VGA_ACCESS_ENABLE 0x1D7D 1669de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_WHITE_OFFSET_BLUE 0x1D84 1670de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_WHITE_OFFSET_GREEN 0x1D85 1671de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_WHITE_OFFSET_RED 0x1D86 1672de2bdb3dSTom St Denis #define mmDCP1_DC_LUT_WRITE_EN_MASK 0x1D7E 1673de2bdb3dSTom St Denis #define mmDCP1_DCP_CRC_CONTROL 0x1D87 1674de2bdb3dSTom St Denis #define mmDCP1_DCP_CRC_CURRENT 0x1D89 1675de2bdb3dSTom St Denis #define mmDCP1_DCP_CRC_LAST 0x1D8B 1676de2bdb3dSTom St Denis #define mmDCP1_DCP_CRC_MASK 0x1D88 1677de2bdb3dSTom St Denis #define mmDCP1_DCP_DEBUG 0x1D8D 1678de2bdb3dSTom St Denis #define mmDCP1_DCP_DEBUG2 0x1D98 1679de2bdb3dSTom St Denis #define mmDCP1_DCP_FP_CONVERTED_FIELD 0x1D65 1680de2bdb3dSTom St Denis #define mmDCP1_DCP_GSL_CONTROL 0x1D90 1681de2bdb3dSTom St Denis #define mmDCP1_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1D91 1682de2bdb3dSTom St Denis #define mmDCP1_DCP_RANDOM_SEEDS 0x1D61 1683de2bdb3dSTom St Denis #define mmDCP1_DCP_SPATIAL_DITHER_CNTL 0x1D60 1684de2bdb3dSTom St Denis #define mmDCP1_DCP_TEST_DEBUG_DATA 0x1D96 1685de2bdb3dSTom St Denis #define mmDCP1_DCP_TEST_DEBUG_INDEX 0x1D95 1686de2bdb3dSTom St Denis #define mmDCP1_DEGAMMA_CONTROL 0x1D58 1687de2bdb3dSTom St Denis #define mmDCP1_DENORM_CONTROL 0x1D50 1688de2bdb3dSTom St Denis #define mmDCP1_GAMUT_REMAP_C11_C12 0x1D5A 1689de2bdb3dSTom St Denis #define mmDCP1_GAMUT_REMAP_C13_C14 0x1D5B 1690de2bdb3dSTom St Denis #define mmDCP1_GAMUT_REMAP_C21_C22 0x1D5C 1691de2bdb3dSTom St Denis #define mmDCP1_GAMUT_REMAP_C23_C24 0x1D5D 1692de2bdb3dSTom St Denis #define mmDCP1_GAMUT_REMAP_C31_C32 0x1D5E 1693de2bdb3dSTom St Denis #define mmDCP1_GAMUT_REMAP_C33_C34 0x1D5F 1694de2bdb3dSTom St Denis #define mmDCP1_GAMUT_REMAP_CONTROL 0x1D59 1695de2bdb3dSTom St Denis #define mmDCP1_GRPH_COMPRESS_PITCH 0x1D1A 1696de2bdb3dSTom St Denis #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS 0x1D19 1697de2bdb3dSTom St Denis #define mmDCP1_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1D1B 1698de2bdb3dSTom St Denis #define mmDCP1_GRPH_CONTROL 0x1D01 1699de2bdb3dSTom St Denis #define mmDCP1_GRPH_DFQ_CONTROL 0x1D14 1700de2bdb3dSTom St Denis #define mmDCP1_GRPH_DFQ_STATUS 0x1D15 1701de2bdb3dSTom St Denis #define mmDCP1_GRPH_ENABLE 0x1D00 1702de2bdb3dSTom St Denis #define mmDCP1_GRPH_FLIP_CONTROL 0x1D12 1703de2bdb3dSTom St Denis #define mmDCP1_GRPH_INTERRUPT_CONTROL 0x1D17 1704de2bdb3dSTom St Denis #define mmDCP1_GRPH_INTERRUPT_STATUS 0x1D16 1705de2bdb3dSTom St Denis #define mmDCP1_GRPH_LUT_10BIT_BYPASS 0x1D02 1706de2bdb3dSTom St Denis #define mmDCP1_GRPH_PITCH 0x1D06 1707de2bdb3dSTom St Denis #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS 0x1D04 1708de2bdb3dSTom St Denis #define mmDCP1_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1D07 1709de2bdb3dSTom St Denis #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS 0x1D05 1710de2bdb3dSTom St Denis #define mmDCP1_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D08 1711de2bdb3dSTom St Denis #define mmDCP1_GRPH_STEREOSYNC_FLIP 0x1D97 1712de2bdb3dSTom St Denis #define mmDCP1_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1D18 1713de2bdb3dSTom St Denis #define mmDCP1_GRPH_SURFACE_ADDRESS_INUSE 0x1D13 1714de2bdb3dSTom St Denis #define mmDCP1_GRPH_SURFACE_OFFSET_X 0x1D09 1715de2bdb3dSTom St Denis #define mmDCP1_GRPH_SURFACE_OFFSET_Y 0x1D0A 1716de2bdb3dSTom St Denis #define mmDCP1_GRPH_SWAP_CNTL 0x1D03 1717de2bdb3dSTom St Denis #define mmDCP1_GRPH_UPDATE 0x1D11 1718de2bdb3dSTom St Denis #define mmDCP1_GRPH_X_END 0x1D0D 1719de2bdb3dSTom St Denis #define mmDCP1_GRPH_X_START 0x1D0B 1720de2bdb3dSTom St Denis #define mmDCP1_GRPH_Y_END 0x1D0E 1721de2bdb3dSTom St Denis #define mmDCP1_GRPH_Y_START 0x1D0C 1722de2bdb3dSTom St Denis #define mmDCP1_INPUT_CSC_C11_C12 0x1D36 1723de2bdb3dSTom St Denis #define mmDCP1_INPUT_CSC_C13_C14 0x1D37 1724de2bdb3dSTom St Denis #define mmDCP1_INPUT_CSC_C21_C22 0x1D38 1725de2bdb3dSTom St Denis #define mmDCP1_INPUT_CSC_C23_C24 0x1D39 1726de2bdb3dSTom St Denis #define mmDCP1_INPUT_CSC_C31_C32 0x1D3A 1727de2bdb3dSTom St Denis #define mmDCP1_INPUT_CSC_C33_C34 0x1D3B 1728de2bdb3dSTom St Denis #define mmDCP1_INPUT_CSC_CONTROL 0x1D35 1729de2bdb3dSTom St Denis #define mmDCP1_INPUT_GAMMA_CONTROL 0x1D10 1730de2bdb3dSTom St Denis #define mmDCP1_KEY_CONTROL 0x1D53 1731de2bdb3dSTom St Denis #define mmDCP1_KEY_RANGE_ALPHA 0x1D54 1732de2bdb3dSTom St Denis #define mmDCP1_KEY_RANGE_BLUE 0x1D57 1733de2bdb3dSTom St Denis #define mmDCP1_KEY_RANGE_GREEN 0x1D56 1734de2bdb3dSTom St Denis #define mmDCP1_KEY_RANGE_RED 0x1D55 1735de2bdb3dSTom St Denis #define mmDCP1_OUTPUT_CSC_C11_C12 0x1D3D 1736de2bdb3dSTom St Denis #define mmDCP1_OUTPUT_CSC_C13_C14 0x1D3E 1737de2bdb3dSTom St Denis #define mmDCP1_OUTPUT_CSC_C21_C22 0x1D3F 1738de2bdb3dSTom St Denis #define mmDCP1_OUTPUT_CSC_C23_C24 0x1D40 1739de2bdb3dSTom St Denis #define mmDCP1_OUTPUT_CSC_C31_C32 0x1D41 1740de2bdb3dSTom St Denis #define mmDCP1_OUTPUT_CSC_C33_C34 0x1D42 1741de2bdb3dSTom St Denis #define mmDCP1_OUTPUT_CSC_CONTROL 0x1D3C 1742de2bdb3dSTom St Denis #define mmDCP1_OUT_ROUND_CONTROL 0x1D51 1743de2bdb3dSTom St Denis #define mmDCP1_OVL_CONTROL1 0x1D1D 1744de2bdb3dSTom St Denis #define mmDCP1_OVL_CONTROL2 0x1D1E 1745de2bdb3dSTom St Denis #define mmDCP1_OVL_DFQ_CONTROL 0x1D29 1746de2bdb3dSTom St Denis #define mmDCP1_OVL_DFQ_STATUS 0x1D2A 1747de2bdb3dSTom St Denis #define mmDCP1_OVL_ENABLE 0x1D1C 1748de2bdb3dSTom St Denis #define mmDCP1_OVL_END 0x1D26 1749de2bdb3dSTom St Denis #define mmDCP1_OVL_PITCH 0x1D21 1750de2bdb3dSTom St Denis #define mmDCP1_OVLSCL_EDGE_PIXEL_CNTL 0x1D2C 1751de2bdb3dSTom St Denis #define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS 0x1D92 1752de2bdb3dSTom St Denis #define mmDCP1_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1D94 1753de2bdb3dSTom St Denis #define mmDCP1_OVL_START 0x1D25 1754de2bdb3dSTom St Denis #define mmDCP1_OVL_STEREOSYNC_FLIP 0x1D93 1755de2bdb3dSTom St Denis #define mmDCP1_OVL_SURFACE_ADDRESS 0x1D20 1756de2bdb3dSTom St Denis #define mmDCP1_OVL_SURFACE_ADDRESS_HIGH 0x1D22 1757de2bdb3dSTom St Denis #define mmDCP1_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x1D2B 1758de2bdb3dSTom St Denis #define mmDCP1_OVL_SURFACE_ADDRESS_INUSE 0x1D28 1759de2bdb3dSTom St Denis #define mmDCP1_OVL_SURFACE_OFFSET_X 0x1D23 1760de2bdb3dSTom St Denis #define mmDCP1_OVL_SURFACE_OFFSET_Y 0x1D24 1761de2bdb3dSTom St Denis #define mmDCP1_OVL_SWAP_CNTL 0x1D1F 1762de2bdb3dSTom St Denis #define mmDCP1_OVL_UPDATE 0x1D27 1763de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_GRPH_CONTROL 0x1D2D 1764de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_OVL_CONTROL 0x1D31 1765de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_VALUES_GRPH_B 0x1D30 1766de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_VALUES_GRPH_G 0x1D2F 1767de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_VALUES_GRPH_R 0x1D2E 1768de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_VALUES_OVL_CB 0x1D32 1769de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_VALUES_OVL_CR 0x1D34 1770de2bdb3dSTom St Denis #define mmDCP1_PRESCALE_VALUES_OVL_Y 0x1D33 1771de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_END_CNTL1 0x1DA6 1772de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_END_CNTL2 0x1DA7 1773de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_0_1 0x1DA8 1774de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_10_11 0x1DAD 1775de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_12_13 0x1DAE 1776de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_14_15 0x1DAF 1777de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_2_3 0x1DA9 1778de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_4_5 0x1DAA 1779de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_6_7 0x1DAB 1780de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_REGION_8_9 0x1DAC 1781de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_SLOPE_CNTL 0x1DA5 1782de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLA_START_CNTL 0x1DA4 1783de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_END_CNTL1 0x1DB2 1784de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_END_CNTL2 0x1DB3 1785de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_0_1 0x1DB4 1786de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_10_11 0x1DB9 1787de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_12_13 0x1DBA 1788de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_14_15 0x1DBB 1789de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_2_3 0x1DB5 1790de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_4_5 0x1DB6 1791de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_6_7 0x1DB7 1792de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_REGION_8_9 0x1DB8 1793de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_SLOPE_CNTL 0x1DB1 1794de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CNTLB_START_CNTL 0x1DB0 1795de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_CONTROL 0x1DA0 1796de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_LUT_DATA 0x1DA2 1797de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_LUT_INDEX 0x1DA1 1798de2bdb3dSTom St Denis #define mmDCP1_REGAMMA_LUT_WRITE_EN_MASK 0x1DA3 1799de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXA_TRANS_C11_C12 0x4043 1800de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXA_TRANS_C13_C14 0x4044 1801de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXA_TRANS_C21_C22 0x4045 1802de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXA_TRANS_C23_C24 0x4046 1803de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXA_TRANS_C31_C32 0x4047 1804de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXA_TRANS_C33_C34 0x4048 1805de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXB_TRANS_C11_C12 0x4049 1806de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXB_TRANS_C13_C14 0x404A 1807de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXB_TRANS_C21_C22 0x404B 1808de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXB_TRANS_C23_C24 0x404C 1809de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXB_TRANS_C31_C32 0x404D 1810de2bdb3dSTom St Denis #define mmDCP2_COMM_MATRIXB_TRANS_C33_C34 0x404E 1811de2bdb3dSTom St Denis #define mmDCP2_CUR_COLOR1 0x406C 1812de2bdb3dSTom St Denis #define mmDCP2_CUR_COLOR2 0x406D 1813de2bdb3dSTom St Denis #define mmDCP2_CUR_CONTROL 0x4066 1814de2bdb3dSTom St Denis #define mmDCP2_CUR_HOT_SPOT 0x406B 1815de2bdb3dSTom St Denis #define mmDCP2_CUR_POSITION 0x406A 1816de2bdb3dSTom St Denis #define mmDCP2_CUR_REQUEST_FILTER_CNTL 0x4099 1817de2bdb3dSTom St Denis #define mmDCP2_CUR_SIZE 0x4068 1818de2bdb3dSTom St Denis #define mmDCP2_CUR_SURFACE_ADDRESS 0x4067 1819de2bdb3dSTom St Denis #define mmDCP2_CUR_SURFACE_ADDRESS_HIGH 0x4069 1820de2bdb3dSTom St Denis #define mmDCP2_CUR_UPDATE 0x406E 1821de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_30_COLOR 0x407C 1822de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_AUTOFILL 0x407F 1823de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_BLACK_OFFSET_BLUE 0x4081 1824de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_BLACK_OFFSET_GREEN 0x4082 1825de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_BLACK_OFFSET_RED 0x4083 1826de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_CONTROL 0x4080 1827de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_PWL_DATA 0x407B 1828de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_RW_INDEX 0x4079 1829de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_RW_MODE 0x4078 1830de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_SEQ_COLOR 0x407A 1831de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_VGA_ACCESS_ENABLE 0x407D 1832de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_WHITE_OFFSET_BLUE 0x4084 1833de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_WHITE_OFFSET_GREEN 0x4085 1834de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_WHITE_OFFSET_RED 0x4086 1835de2bdb3dSTom St Denis #define mmDCP2_DC_LUT_WRITE_EN_MASK 0x407E 1836de2bdb3dSTom St Denis #define mmDCP2_DCP_CRC_CONTROL 0x4087 1837de2bdb3dSTom St Denis #define mmDCP2_DCP_CRC_CURRENT 0x4089 1838de2bdb3dSTom St Denis #define mmDCP2_DCP_CRC_LAST 0x408B 1839de2bdb3dSTom St Denis #define mmDCP2_DCP_CRC_MASK 0x4088 1840de2bdb3dSTom St Denis #define mmDCP2_DCP_DEBUG 0x408D 1841de2bdb3dSTom St Denis #define mmDCP2_DCP_DEBUG2 0x4098 1842de2bdb3dSTom St Denis #define mmDCP2_DCP_FP_CONVERTED_FIELD 0x4065 1843de2bdb3dSTom St Denis #define mmDCP2_DCP_GSL_CONTROL 0x4090 1844de2bdb3dSTom St Denis #define mmDCP2_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4091 1845de2bdb3dSTom St Denis #define mmDCP2_DCP_RANDOM_SEEDS 0x4061 1846de2bdb3dSTom St Denis #define mmDCP2_DCP_SPATIAL_DITHER_CNTL 0x4060 1847de2bdb3dSTom St Denis #define mmDCP2_DCP_TEST_DEBUG_DATA 0x4096 1848de2bdb3dSTom St Denis #define mmDCP2_DCP_TEST_DEBUG_INDEX 0x4095 1849de2bdb3dSTom St Denis #define mmDCP2_DEGAMMA_CONTROL 0x4058 1850de2bdb3dSTom St Denis #define mmDCP2_DENORM_CONTROL 0x4050 1851de2bdb3dSTom St Denis #define mmDCP2_GAMUT_REMAP_C11_C12 0x405A 1852de2bdb3dSTom St Denis #define mmDCP2_GAMUT_REMAP_C13_C14 0x405B 1853de2bdb3dSTom St Denis #define mmDCP2_GAMUT_REMAP_C21_C22 0x405C 1854de2bdb3dSTom St Denis #define mmDCP2_GAMUT_REMAP_C23_C24 0x405D 1855de2bdb3dSTom St Denis #define mmDCP2_GAMUT_REMAP_C31_C32 0x405E 1856de2bdb3dSTom St Denis #define mmDCP2_GAMUT_REMAP_C33_C34 0x405F 1857de2bdb3dSTom St Denis #define mmDCP2_GAMUT_REMAP_CONTROL 0x4059 1858de2bdb3dSTom St Denis #define mmDCP2_GRPH_COMPRESS_PITCH 0x401A 1859de2bdb3dSTom St Denis #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS 0x4019 1860de2bdb3dSTom St Denis #define mmDCP2_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x401B 1861de2bdb3dSTom St Denis #define mmDCP2_GRPH_CONTROL 0x4001 1862de2bdb3dSTom St Denis #define mmDCP2_GRPH_DFQ_CONTROL 0x4014 1863de2bdb3dSTom St Denis #define mmDCP2_GRPH_DFQ_STATUS 0x4015 1864de2bdb3dSTom St Denis #define mmDCP2_GRPH_ENABLE 0x4000 1865de2bdb3dSTom St Denis #define mmDCP2_GRPH_FLIP_CONTROL 0x4012 1866de2bdb3dSTom St Denis #define mmDCP2_GRPH_INTERRUPT_CONTROL 0x4017 1867de2bdb3dSTom St Denis #define mmDCP2_GRPH_INTERRUPT_STATUS 0x4016 1868de2bdb3dSTom St Denis #define mmDCP2_GRPH_LUT_10BIT_BYPASS 0x4002 1869de2bdb3dSTom St Denis #define mmDCP2_GRPH_PITCH 0x4006 1870de2bdb3dSTom St Denis #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS 0x4004 1871de2bdb3dSTom St Denis #define mmDCP2_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4007 1872de2bdb3dSTom St Denis #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS 0x4005 1873de2bdb3dSTom St Denis #define mmDCP2_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4008 1874de2bdb3dSTom St Denis #define mmDCP2_GRPH_STEREOSYNC_FLIP 0x4097 1875de2bdb3dSTom St Denis #define mmDCP2_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4018 1876de2bdb3dSTom St Denis #define mmDCP2_GRPH_SURFACE_ADDRESS_INUSE 0x4013 1877de2bdb3dSTom St Denis #define mmDCP2_GRPH_SURFACE_OFFSET_X 0x4009 1878de2bdb3dSTom St Denis #define mmDCP2_GRPH_SURFACE_OFFSET_Y 0x400A 1879de2bdb3dSTom St Denis #define mmDCP2_GRPH_SWAP_CNTL 0x4003 1880de2bdb3dSTom St Denis #define mmDCP2_GRPH_UPDATE 0x4011 1881de2bdb3dSTom St Denis #define mmDCP2_GRPH_X_END 0x400D 1882de2bdb3dSTom St Denis #define mmDCP2_GRPH_X_START 0x400B 1883de2bdb3dSTom St Denis #define mmDCP2_GRPH_Y_END 0x400E 1884de2bdb3dSTom St Denis #define mmDCP2_GRPH_Y_START 0x400C 1885de2bdb3dSTom St Denis #define mmDCP2_INPUT_CSC_C11_C12 0x4036 1886de2bdb3dSTom St Denis #define mmDCP2_INPUT_CSC_C13_C14 0x4037 1887de2bdb3dSTom St Denis #define mmDCP2_INPUT_CSC_C21_C22 0x4038 1888de2bdb3dSTom St Denis #define mmDCP2_INPUT_CSC_C23_C24 0x4039 1889de2bdb3dSTom St Denis #define mmDCP2_INPUT_CSC_C31_C32 0x403A 1890de2bdb3dSTom St Denis #define mmDCP2_INPUT_CSC_C33_C34 0x403B 1891de2bdb3dSTom St Denis #define mmDCP2_INPUT_CSC_CONTROL 0x4035 1892de2bdb3dSTom St Denis #define mmDCP2_INPUT_GAMMA_CONTROL 0x4010 1893de2bdb3dSTom St Denis #define mmDCP2_KEY_CONTROL 0x4053 1894de2bdb3dSTom St Denis #define mmDCP2_KEY_RANGE_ALPHA 0x4054 1895de2bdb3dSTom St Denis #define mmDCP2_KEY_RANGE_BLUE 0x4057 1896de2bdb3dSTom St Denis #define mmDCP2_KEY_RANGE_GREEN 0x4056 1897de2bdb3dSTom St Denis #define mmDCP2_KEY_RANGE_RED 0x4055 1898de2bdb3dSTom St Denis #define mmDCP2_OUTPUT_CSC_C11_C12 0x403D 1899de2bdb3dSTom St Denis #define mmDCP2_OUTPUT_CSC_C13_C14 0x403E 1900de2bdb3dSTom St Denis #define mmDCP2_OUTPUT_CSC_C21_C22 0x403F 1901de2bdb3dSTom St Denis #define mmDCP2_OUTPUT_CSC_C23_C24 0x4040 1902de2bdb3dSTom St Denis #define mmDCP2_OUTPUT_CSC_C31_C32 0x4041 1903de2bdb3dSTom St Denis #define mmDCP2_OUTPUT_CSC_C33_C34 0x4042 1904de2bdb3dSTom St Denis #define mmDCP2_OUTPUT_CSC_CONTROL 0x403C 1905de2bdb3dSTom St Denis #define mmDCP2_OUT_ROUND_CONTROL 0x4051 1906de2bdb3dSTom St Denis #define mmDCP2_OVL_CONTROL1 0x401D 1907de2bdb3dSTom St Denis #define mmDCP2_OVL_CONTROL2 0x401E 1908de2bdb3dSTom St Denis #define mmDCP2_OVL_DFQ_CONTROL 0x4029 1909de2bdb3dSTom St Denis #define mmDCP2_OVL_DFQ_STATUS 0x402A 1910de2bdb3dSTom St Denis #define mmDCP2_OVL_ENABLE 0x401C 1911de2bdb3dSTom St Denis #define mmDCP2_OVL_END 0x4026 1912de2bdb3dSTom St Denis #define mmDCP2_OVL_PITCH 0x4021 1913de2bdb3dSTom St Denis #define mmDCP2_OVLSCL_EDGE_PIXEL_CNTL 0x402C 1914de2bdb3dSTom St Denis #define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS 0x4092 1915de2bdb3dSTom St Denis #define mmDCP2_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4094 1916de2bdb3dSTom St Denis #define mmDCP2_OVL_START 0x4025 1917de2bdb3dSTom St Denis #define mmDCP2_OVL_STEREOSYNC_FLIP 0x4093 1918de2bdb3dSTom St Denis #define mmDCP2_OVL_SURFACE_ADDRESS 0x4020 1919de2bdb3dSTom St Denis #define mmDCP2_OVL_SURFACE_ADDRESS_HIGH 0x4022 1920de2bdb3dSTom St Denis #define mmDCP2_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x402B 1921de2bdb3dSTom St Denis #define mmDCP2_OVL_SURFACE_ADDRESS_INUSE 0x4028 1922de2bdb3dSTom St Denis #define mmDCP2_OVL_SURFACE_OFFSET_X 0x4023 1923de2bdb3dSTom St Denis #define mmDCP2_OVL_SURFACE_OFFSET_Y 0x4024 1924de2bdb3dSTom St Denis #define mmDCP2_OVL_SWAP_CNTL 0x401F 1925de2bdb3dSTom St Denis #define mmDCP2_OVL_UPDATE 0x4027 1926de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_GRPH_CONTROL 0x402D 1927de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_OVL_CONTROL 0x4031 1928de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_VALUES_GRPH_B 0x4030 1929de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_VALUES_GRPH_G 0x402F 1930de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_VALUES_GRPH_R 0x402E 1931de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_VALUES_OVL_CB 0x4032 1932de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_VALUES_OVL_CR 0x4034 1933de2bdb3dSTom St Denis #define mmDCP2_PRESCALE_VALUES_OVL_Y 0x4033 1934de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_END_CNTL1 0x40A6 1935de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_END_CNTL2 0x40A7 1936de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_0_1 0x40A8 1937de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_10_11 0x40AD 1938de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_12_13 0x40AE 1939de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_14_15 0x40AF 1940de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_2_3 0x40A9 1941de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_4_5 0x40AA 1942de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_6_7 0x40AB 1943de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_REGION_8_9 0x40AC 1944de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_SLOPE_CNTL 0x40A5 1945de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLA_START_CNTL 0x40A4 1946de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_END_CNTL1 0x40B2 1947de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_END_CNTL2 0x40B3 1948de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_0_1 0x40B4 1949de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_10_11 0x40B9 1950de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_12_13 0x40BA 1951de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_14_15 0x40BB 1952de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_2_3 0x40B5 1953de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_4_5 0x40B6 1954de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_6_7 0x40B7 1955de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_REGION_8_9 0x40B8 1956de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_SLOPE_CNTL 0x40B1 1957de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CNTLB_START_CNTL 0x40B0 1958de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_CONTROL 0x40A0 1959de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_LUT_DATA 0x40A2 1960de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_LUT_INDEX 0x40A1 1961de2bdb3dSTom St Denis #define mmDCP2_REGAMMA_LUT_WRITE_EN_MASK 0x40A3 1962de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXA_TRANS_C11_C12 0x4343 1963de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXA_TRANS_C13_C14 0x4344 1964de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXA_TRANS_C21_C22 0x4345 1965de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXA_TRANS_C23_C24 0x4346 1966de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXA_TRANS_C31_C32 0x4347 1967de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXA_TRANS_C33_C34 0x4348 1968de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXB_TRANS_C11_C12 0x4349 1969de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXB_TRANS_C13_C14 0x434A 1970de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXB_TRANS_C21_C22 0x434B 1971de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXB_TRANS_C23_C24 0x434C 1972de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXB_TRANS_C31_C32 0x434D 1973de2bdb3dSTom St Denis #define mmDCP3_COMM_MATRIXB_TRANS_C33_C34 0x434E 1974de2bdb3dSTom St Denis #define mmDCP3_CUR_COLOR1 0x436C 1975de2bdb3dSTom St Denis #define mmDCP3_CUR_COLOR2 0x436D 1976de2bdb3dSTom St Denis #define mmDCP3_CUR_CONTROL 0x4366 1977de2bdb3dSTom St Denis #define mmDCP3_CUR_HOT_SPOT 0x436B 1978de2bdb3dSTom St Denis #define mmDCP3_CUR_POSITION 0x436A 1979de2bdb3dSTom St Denis #define mmDCP3_CUR_REQUEST_FILTER_CNTL 0x4399 1980de2bdb3dSTom St Denis #define mmDCP3_CUR_SIZE 0x4368 1981de2bdb3dSTom St Denis #define mmDCP3_CUR_SURFACE_ADDRESS 0x4367 1982de2bdb3dSTom St Denis #define mmDCP3_CUR_SURFACE_ADDRESS_HIGH 0x4369 1983de2bdb3dSTom St Denis #define mmDCP3_CUR_UPDATE 0x436E 1984de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_30_COLOR 0x437C 1985de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_AUTOFILL 0x437F 1986de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_BLACK_OFFSET_BLUE 0x4381 1987de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_BLACK_OFFSET_GREEN 0x4382 1988de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_BLACK_OFFSET_RED 0x4383 1989de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_CONTROL 0x4380 1990de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_PWL_DATA 0x437B 1991de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_RW_INDEX 0x4379 1992de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_RW_MODE 0x4378 1993de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_SEQ_COLOR 0x437A 1994de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_VGA_ACCESS_ENABLE 0x437D 1995de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_WHITE_OFFSET_BLUE 0x4384 1996de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_WHITE_OFFSET_GREEN 0x4385 1997de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_WHITE_OFFSET_RED 0x4386 1998de2bdb3dSTom St Denis #define mmDCP3_DC_LUT_WRITE_EN_MASK 0x437E 1999de2bdb3dSTom St Denis #define mmDCP3_DCP_CRC_CONTROL 0x4387 2000de2bdb3dSTom St Denis #define mmDCP3_DCP_CRC_CURRENT 0x4389 2001de2bdb3dSTom St Denis #define mmDCP3_DCP_CRC_LAST 0x438B 2002de2bdb3dSTom St Denis #define mmDCP3_DCP_CRC_MASK 0x4388 2003de2bdb3dSTom St Denis #define mmDCP3_DCP_DEBUG 0x438D 2004de2bdb3dSTom St Denis #define mmDCP3_DCP_DEBUG2 0x4398 2005de2bdb3dSTom St Denis #define mmDCP3_DCP_FP_CONVERTED_FIELD 0x4365 2006de2bdb3dSTom St Denis #define mmDCP3_DCP_GSL_CONTROL 0x4390 2007de2bdb3dSTom St Denis #define mmDCP3_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4391 2008de2bdb3dSTom St Denis #define mmDCP3_DCP_RANDOM_SEEDS 0x4361 2009de2bdb3dSTom St Denis #define mmDCP3_DCP_SPATIAL_DITHER_CNTL 0x4360 2010de2bdb3dSTom St Denis #define mmDCP3_DCP_TEST_DEBUG_DATA 0x4396 2011de2bdb3dSTom St Denis #define mmDCP3_DCP_TEST_DEBUG_INDEX 0x4395 2012de2bdb3dSTom St Denis #define mmDCP3_DEGAMMA_CONTROL 0x4358 2013de2bdb3dSTom St Denis #define mmDCP3_DENORM_CONTROL 0x4350 2014de2bdb3dSTom St Denis #define mmDCP3_GAMUT_REMAP_C11_C12 0x435A 2015de2bdb3dSTom St Denis #define mmDCP3_GAMUT_REMAP_C13_C14 0x435B 2016de2bdb3dSTom St Denis #define mmDCP3_GAMUT_REMAP_C21_C22 0x435C 2017de2bdb3dSTom St Denis #define mmDCP3_GAMUT_REMAP_C23_C24 0x435D 2018de2bdb3dSTom St Denis #define mmDCP3_GAMUT_REMAP_C31_C32 0x435E 2019de2bdb3dSTom St Denis #define mmDCP3_GAMUT_REMAP_C33_C34 0x435F 2020de2bdb3dSTom St Denis #define mmDCP3_GAMUT_REMAP_CONTROL 0x4359 2021de2bdb3dSTom St Denis #define mmDCP3_GRPH_COMPRESS_PITCH 0x431A 2022de2bdb3dSTom St Denis #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS 0x4319 2023de2bdb3dSTom St Denis #define mmDCP3_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x431B 2024de2bdb3dSTom St Denis #define mmDCP3_GRPH_CONTROL 0x4301 2025de2bdb3dSTom St Denis #define mmDCP3_GRPH_DFQ_CONTROL 0x4314 2026de2bdb3dSTom St Denis #define mmDCP3_GRPH_DFQ_STATUS 0x4315 2027de2bdb3dSTom St Denis #define mmDCP3_GRPH_ENABLE 0x4300 2028de2bdb3dSTom St Denis #define mmDCP3_GRPH_FLIP_CONTROL 0x4312 2029de2bdb3dSTom St Denis #define mmDCP3_GRPH_INTERRUPT_CONTROL 0x4317 2030de2bdb3dSTom St Denis #define mmDCP3_GRPH_INTERRUPT_STATUS 0x4316 2031de2bdb3dSTom St Denis #define mmDCP3_GRPH_LUT_10BIT_BYPASS 0x4302 2032de2bdb3dSTom St Denis #define mmDCP3_GRPH_PITCH 0x4306 2033de2bdb3dSTom St Denis #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS 0x4304 2034de2bdb3dSTom St Denis #define mmDCP3_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4307 2035de2bdb3dSTom St Denis #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS 0x4305 2036de2bdb3dSTom St Denis #define mmDCP3_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4308 2037de2bdb3dSTom St Denis #define mmDCP3_GRPH_STEREOSYNC_FLIP 0x4397 2038de2bdb3dSTom St Denis #define mmDCP3_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4318 2039de2bdb3dSTom St Denis #define mmDCP3_GRPH_SURFACE_ADDRESS_INUSE 0x4313 2040de2bdb3dSTom St Denis #define mmDCP3_GRPH_SURFACE_OFFSET_X 0x4309 2041de2bdb3dSTom St Denis #define mmDCP3_GRPH_SURFACE_OFFSET_Y 0x430A 2042de2bdb3dSTom St Denis #define mmDCP3_GRPH_SWAP_CNTL 0x4303 2043de2bdb3dSTom St Denis #define mmDCP3_GRPH_UPDATE 0x4311 2044de2bdb3dSTom St Denis #define mmDCP3_GRPH_X_END 0x430D 2045de2bdb3dSTom St Denis #define mmDCP3_GRPH_X_START 0x430B 2046de2bdb3dSTom St Denis #define mmDCP3_GRPH_Y_END 0x430E 2047de2bdb3dSTom St Denis #define mmDCP3_GRPH_Y_START 0x430C 2048de2bdb3dSTom St Denis #define mmDCP3_INPUT_CSC_C11_C12 0x4336 2049de2bdb3dSTom St Denis #define mmDCP3_INPUT_CSC_C13_C14 0x4337 2050de2bdb3dSTom St Denis #define mmDCP3_INPUT_CSC_C21_C22 0x4338 2051de2bdb3dSTom St Denis #define mmDCP3_INPUT_CSC_C23_C24 0x4339 2052de2bdb3dSTom St Denis #define mmDCP3_INPUT_CSC_C31_C32 0x433A 2053de2bdb3dSTom St Denis #define mmDCP3_INPUT_CSC_C33_C34 0x433B 2054de2bdb3dSTom St Denis #define mmDCP3_INPUT_CSC_CONTROL 0x4335 2055de2bdb3dSTom St Denis #define mmDCP3_INPUT_GAMMA_CONTROL 0x4310 2056de2bdb3dSTom St Denis #define mmDCP3_KEY_CONTROL 0x4353 2057de2bdb3dSTom St Denis #define mmDCP3_KEY_RANGE_ALPHA 0x4354 2058de2bdb3dSTom St Denis #define mmDCP3_KEY_RANGE_BLUE 0x4357 2059de2bdb3dSTom St Denis #define mmDCP3_KEY_RANGE_GREEN 0x4356 2060de2bdb3dSTom St Denis #define mmDCP3_KEY_RANGE_RED 0x4355 2061de2bdb3dSTom St Denis #define mmDCP3_OUTPUT_CSC_C11_C12 0x433D 2062de2bdb3dSTom St Denis #define mmDCP3_OUTPUT_CSC_C13_C14 0x433E 2063de2bdb3dSTom St Denis #define mmDCP3_OUTPUT_CSC_C21_C22 0x433F 2064de2bdb3dSTom St Denis #define mmDCP3_OUTPUT_CSC_C23_C24 0x4340 2065de2bdb3dSTom St Denis #define mmDCP3_OUTPUT_CSC_C31_C32 0x4341 2066de2bdb3dSTom St Denis #define mmDCP3_OUTPUT_CSC_C33_C34 0x4342 2067de2bdb3dSTom St Denis #define mmDCP3_OUTPUT_CSC_CONTROL 0x433C 2068de2bdb3dSTom St Denis #define mmDCP3_OUT_ROUND_CONTROL 0x4351 2069de2bdb3dSTom St Denis #define mmDCP3_OVL_CONTROL1 0x431D 2070de2bdb3dSTom St Denis #define mmDCP3_OVL_CONTROL2 0x431E 2071de2bdb3dSTom St Denis #define mmDCP3_OVL_DFQ_CONTROL 0x4329 2072de2bdb3dSTom St Denis #define mmDCP3_OVL_DFQ_STATUS 0x432A 2073de2bdb3dSTom St Denis #define mmDCP3_OVL_ENABLE 0x431C 2074de2bdb3dSTom St Denis #define mmDCP3_OVL_END 0x4326 2075de2bdb3dSTom St Denis #define mmDCP3_OVL_PITCH 0x4321 2076de2bdb3dSTom St Denis #define mmDCP3_OVLSCL_EDGE_PIXEL_CNTL 0x432C 2077de2bdb3dSTom St Denis #define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS 0x4392 2078de2bdb3dSTom St Denis #define mmDCP3_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4394 2079de2bdb3dSTom St Denis #define mmDCP3_OVL_START 0x4325 2080de2bdb3dSTom St Denis #define mmDCP3_OVL_STEREOSYNC_FLIP 0x4393 2081de2bdb3dSTom St Denis #define mmDCP3_OVL_SURFACE_ADDRESS 0x4320 2082de2bdb3dSTom St Denis #define mmDCP3_OVL_SURFACE_ADDRESS_HIGH 0x4322 2083de2bdb3dSTom St Denis #define mmDCP3_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x432B 2084de2bdb3dSTom St Denis #define mmDCP3_OVL_SURFACE_ADDRESS_INUSE 0x4328 2085de2bdb3dSTom St Denis #define mmDCP3_OVL_SURFACE_OFFSET_X 0x4323 2086de2bdb3dSTom St Denis #define mmDCP3_OVL_SURFACE_OFFSET_Y 0x4324 2087de2bdb3dSTom St Denis #define mmDCP3_OVL_SWAP_CNTL 0x431F 2088de2bdb3dSTom St Denis #define mmDCP3_OVL_UPDATE 0x4327 2089de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_GRPH_CONTROL 0x432D 2090de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_OVL_CONTROL 0x4331 2091de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_VALUES_GRPH_B 0x4330 2092de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_VALUES_GRPH_G 0x432F 2093de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_VALUES_GRPH_R 0x432E 2094de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_VALUES_OVL_CB 0x4332 2095de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_VALUES_OVL_CR 0x4334 2096de2bdb3dSTom St Denis #define mmDCP3_PRESCALE_VALUES_OVL_Y 0x4333 2097de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_END_CNTL1 0x43A6 2098de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_END_CNTL2 0x43A7 2099de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_0_1 0x43A8 2100de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_10_11 0x43AD 2101de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_12_13 0x43AE 2102de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_14_15 0x43AF 2103de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_2_3 0x43A9 2104de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_4_5 0x43AA 2105de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_6_7 0x43AB 2106de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_REGION_8_9 0x43AC 2107de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_SLOPE_CNTL 0x43A5 2108de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLA_START_CNTL 0x43A4 2109de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_END_CNTL1 0x43B2 2110de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_END_CNTL2 0x43B3 2111de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_0_1 0x43B4 2112de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_10_11 0x43B9 2113de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_12_13 0x43BA 2114de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_14_15 0x43BB 2115de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_2_3 0x43B5 2116de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_4_5 0x43B6 2117de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_6_7 0x43B7 2118de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_REGION_8_9 0x43B8 2119de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_SLOPE_CNTL 0x43B1 2120de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CNTLB_START_CNTL 0x43B0 2121de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_CONTROL 0x43A0 2122de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_LUT_DATA 0x43A2 2123de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_LUT_INDEX 0x43A1 2124de2bdb3dSTom St Denis #define mmDCP3_REGAMMA_LUT_WRITE_EN_MASK 0x43A3 2125de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXA_TRANS_C11_C12 0x4643 2126de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXA_TRANS_C13_C14 0x4644 2127de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXA_TRANS_C21_C22 0x4645 2128de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXA_TRANS_C23_C24 0x4646 2129de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXA_TRANS_C31_C32 0x4647 2130de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXA_TRANS_C33_C34 0x4648 2131de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXB_TRANS_C11_C12 0x4649 2132de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXB_TRANS_C13_C14 0x464A 2133de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXB_TRANS_C21_C22 0x464B 2134de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXB_TRANS_C23_C24 0x464C 2135de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXB_TRANS_C31_C32 0x464D 2136de2bdb3dSTom St Denis #define mmDCP4_COMM_MATRIXB_TRANS_C33_C34 0x464E 2137de2bdb3dSTom St Denis #define mmDCP4_CUR_COLOR1 0x466C 2138de2bdb3dSTom St Denis #define mmDCP4_CUR_COLOR2 0x466D 2139de2bdb3dSTom St Denis #define mmDCP4_CUR_CONTROL 0x4666 2140de2bdb3dSTom St Denis #define mmDCP4_CUR_HOT_SPOT 0x466B 2141de2bdb3dSTom St Denis #define mmDCP4_CUR_POSITION 0x466A 2142de2bdb3dSTom St Denis #define mmDCP4_CUR_REQUEST_FILTER_CNTL 0x4699 2143de2bdb3dSTom St Denis #define mmDCP4_CUR_SIZE 0x4668 2144de2bdb3dSTom St Denis #define mmDCP4_CUR_SURFACE_ADDRESS 0x4667 2145de2bdb3dSTom St Denis #define mmDCP4_CUR_SURFACE_ADDRESS_HIGH 0x4669 2146de2bdb3dSTom St Denis #define mmDCP4_CUR_UPDATE 0x466E 2147de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_30_COLOR 0x467C 2148de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_AUTOFILL 0x467F 2149de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_BLACK_OFFSET_BLUE 0x4681 2150de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_BLACK_OFFSET_GREEN 0x4682 2151de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_BLACK_OFFSET_RED 0x4683 2152de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_CONTROL 0x4680 2153de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_PWL_DATA 0x467B 2154de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_RW_INDEX 0x4679 2155de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_RW_MODE 0x4678 2156de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_SEQ_COLOR 0x467A 2157de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_VGA_ACCESS_ENABLE 0x467D 2158de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_WHITE_OFFSET_BLUE 0x4684 2159de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_WHITE_OFFSET_GREEN 0x4685 2160de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_WHITE_OFFSET_RED 0x4686 2161de2bdb3dSTom St Denis #define mmDCP4_DC_LUT_WRITE_EN_MASK 0x467E 2162de2bdb3dSTom St Denis #define mmDCP4_DCP_CRC_CONTROL 0x4687 2163de2bdb3dSTom St Denis #define mmDCP4_DCP_CRC_CURRENT 0x4689 2164de2bdb3dSTom St Denis #define mmDCP4_DCP_CRC_LAST 0x468B 2165de2bdb3dSTom St Denis #define mmDCP4_DCP_CRC_MASK 0x4688 2166de2bdb3dSTom St Denis #define mmDCP4_DCP_DEBUG 0x468D 2167de2bdb3dSTom St Denis #define mmDCP4_DCP_DEBUG2 0x4698 2168de2bdb3dSTom St Denis #define mmDCP4_DCP_FP_CONVERTED_FIELD 0x4665 2169de2bdb3dSTom St Denis #define mmDCP4_DCP_GSL_CONTROL 0x4690 2170de2bdb3dSTom St Denis #define mmDCP4_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4691 2171de2bdb3dSTom St Denis #define mmDCP4_DCP_RANDOM_SEEDS 0x4661 2172de2bdb3dSTom St Denis #define mmDCP4_DCP_SPATIAL_DITHER_CNTL 0x4660 2173de2bdb3dSTom St Denis #define mmDCP4_DCP_TEST_DEBUG_DATA 0x4696 2174de2bdb3dSTom St Denis #define mmDCP4_DCP_TEST_DEBUG_INDEX 0x4695 2175de2bdb3dSTom St Denis #define mmDCP4_DEGAMMA_CONTROL 0x4658 2176de2bdb3dSTom St Denis #define mmDCP4_DENORM_CONTROL 0x4650 2177de2bdb3dSTom St Denis #define mmDCP4_GAMUT_REMAP_C11_C12 0x465A 2178de2bdb3dSTom St Denis #define mmDCP4_GAMUT_REMAP_C13_C14 0x465B 2179de2bdb3dSTom St Denis #define mmDCP4_GAMUT_REMAP_C21_C22 0x465C 2180de2bdb3dSTom St Denis #define mmDCP4_GAMUT_REMAP_C23_C24 0x465D 2181de2bdb3dSTom St Denis #define mmDCP4_GAMUT_REMAP_C31_C32 0x465E 2182de2bdb3dSTom St Denis #define mmDCP4_GAMUT_REMAP_C33_C34 0x465F 2183de2bdb3dSTom St Denis #define mmDCP4_GAMUT_REMAP_CONTROL 0x4659 2184de2bdb3dSTom St Denis #define mmDCP4_GRPH_COMPRESS_PITCH 0x461A 2185de2bdb3dSTom St Denis #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS 0x4619 2186de2bdb3dSTom St Denis #define mmDCP4_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x461B 2187de2bdb3dSTom St Denis #define mmDCP4_GRPH_CONTROL 0x4601 2188de2bdb3dSTom St Denis #define mmDCP4_GRPH_DFQ_CONTROL 0x4614 2189de2bdb3dSTom St Denis #define mmDCP4_GRPH_DFQ_STATUS 0x4615 2190de2bdb3dSTom St Denis #define mmDCP4_GRPH_ENABLE 0x4600 2191de2bdb3dSTom St Denis #define mmDCP4_GRPH_FLIP_CONTROL 0x4612 2192de2bdb3dSTom St Denis #define mmDCP4_GRPH_INTERRUPT_CONTROL 0x4617 2193de2bdb3dSTom St Denis #define mmDCP4_GRPH_INTERRUPT_STATUS 0x4616 2194de2bdb3dSTom St Denis #define mmDCP4_GRPH_LUT_10BIT_BYPASS 0x4602 2195de2bdb3dSTom St Denis #define mmDCP4_GRPH_PITCH 0x4606 2196de2bdb3dSTom St Denis #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS 0x4604 2197de2bdb3dSTom St Denis #define mmDCP4_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4607 2198de2bdb3dSTom St Denis #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS 0x4605 2199de2bdb3dSTom St Denis #define mmDCP4_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4608 2200de2bdb3dSTom St Denis #define mmDCP4_GRPH_STEREOSYNC_FLIP 0x4697 2201de2bdb3dSTom St Denis #define mmDCP4_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4618 2202de2bdb3dSTom St Denis #define mmDCP4_GRPH_SURFACE_ADDRESS_INUSE 0x4613 2203de2bdb3dSTom St Denis #define mmDCP4_GRPH_SURFACE_OFFSET_X 0x4609 2204de2bdb3dSTom St Denis #define mmDCP4_GRPH_SURFACE_OFFSET_Y 0x460A 2205de2bdb3dSTom St Denis #define mmDCP4_GRPH_SWAP_CNTL 0x4603 2206de2bdb3dSTom St Denis #define mmDCP4_GRPH_UPDATE 0x4611 2207de2bdb3dSTom St Denis #define mmDCP4_GRPH_X_END 0x460D 2208de2bdb3dSTom St Denis #define mmDCP4_GRPH_X_START 0x460B 2209de2bdb3dSTom St Denis #define mmDCP4_GRPH_Y_END 0x460E 2210de2bdb3dSTom St Denis #define mmDCP4_GRPH_Y_START 0x460C 2211de2bdb3dSTom St Denis #define mmDCP4_INPUT_CSC_C11_C12 0x4636 2212de2bdb3dSTom St Denis #define mmDCP4_INPUT_CSC_C13_C14 0x4637 2213de2bdb3dSTom St Denis #define mmDCP4_INPUT_CSC_C21_C22 0x4638 2214de2bdb3dSTom St Denis #define mmDCP4_INPUT_CSC_C23_C24 0x4639 2215de2bdb3dSTom St Denis #define mmDCP4_INPUT_CSC_C31_C32 0x463A 2216de2bdb3dSTom St Denis #define mmDCP4_INPUT_CSC_C33_C34 0x463B 2217de2bdb3dSTom St Denis #define mmDCP4_INPUT_CSC_CONTROL 0x4635 2218de2bdb3dSTom St Denis #define mmDCP4_INPUT_GAMMA_CONTROL 0x4610 2219de2bdb3dSTom St Denis #define mmDCP4_KEY_CONTROL 0x4653 2220de2bdb3dSTom St Denis #define mmDCP4_KEY_RANGE_ALPHA 0x4654 2221de2bdb3dSTom St Denis #define mmDCP4_KEY_RANGE_BLUE 0x4657 2222de2bdb3dSTom St Denis #define mmDCP4_KEY_RANGE_GREEN 0x4656 2223de2bdb3dSTom St Denis #define mmDCP4_KEY_RANGE_RED 0x4655 2224de2bdb3dSTom St Denis #define mmDCP4_OUTPUT_CSC_C11_C12 0x463D 2225de2bdb3dSTom St Denis #define mmDCP4_OUTPUT_CSC_C13_C14 0x463E 2226de2bdb3dSTom St Denis #define mmDCP4_OUTPUT_CSC_C21_C22 0x463F 2227de2bdb3dSTom St Denis #define mmDCP4_OUTPUT_CSC_C23_C24 0x4640 2228de2bdb3dSTom St Denis #define mmDCP4_OUTPUT_CSC_C31_C32 0x4641 2229de2bdb3dSTom St Denis #define mmDCP4_OUTPUT_CSC_C33_C34 0x4642 2230de2bdb3dSTom St Denis #define mmDCP4_OUTPUT_CSC_CONTROL 0x463C 2231de2bdb3dSTom St Denis #define mmDCP4_OUT_ROUND_CONTROL 0x4651 2232de2bdb3dSTom St Denis #define mmDCP4_OVL_CONTROL1 0x461D 2233de2bdb3dSTom St Denis #define mmDCP4_OVL_CONTROL2 0x461E 2234de2bdb3dSTom St Denis #define mmDCP4_OVL_DFQ_CONTROL 0x4629 2235de2bdb3dSTom St Denis #define mmDCP4_OVL_DFQ_STATUS 0x462A 2236de2bdb3dSTom St Denis #define mmDCP4_OVL_ENABLE 0x461C 2237de2bdb3dSTom St Denis #define mmDCP4_OVL_END 0x4626 2238de2bdb3dSTom St Denis #define mmDCP4_OVL_PITCH 0x4621 2239de2bdb3dSTom St Denis #define mmDCP4_OVLSCL_EDGE_PIXEL_CNTL 0x462C 2240de2bdb3dSTom St Denis #define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS 0x4692 2241de2bdb3dSTom St Denis #define mmDCP4_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4694 2242de2bdb3dSTom St Denis #define mmDCP4_OVL_START 0x4625 2243de2bdb3dSTom St Denis #define mmDCP4_OVL_STEREOSYNC_FLIP 0x4693 2244de2bdb3dSTom St Denis #define mmDCP4_OVL_SURFACE_ADDRESS 0x4620 2245de2bdb3dSTom St Denis #define mmDCP4_OVL_SURFACE_ADDRESS_HIGH 0x4622 2246de2bdb3dSTom St Denis #define mmDCP4_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x462B 2247de2bdb3dSTom St Denis #define mmDCP4_OVL_SURFACE_ADDRESS_INUSE 0x4628 2248de2bdb3dSTom St Denis #define mmDCP4_OVL_SURFACE_OFFSET_X 0x4623 2249de2bdb3dSTom St Denis #define mmDCP4_OVL_SURFACE_OFFSET_Y 0x4624 2250de2bdb3dSTom St Denis #define mmDCP4_OVL_SWAP_CNTL 0x461F 2251de2bdb3dSTom St Denis #define mmDCP4_OVL_UPDATE 0x4627 2252de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_GRPH_CONTROL 0x462D 2253de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_OVL_CONTROL 0x4631 2254de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_VALUES_GRPH_B 0x4630 2255de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_VALUES_GRPH_G 0x462F 2256de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_VALUES_GRPH_R 0x462E 2257de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_VALUES_OVL_CB 0x4632 2258de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_VALUES_OVL_CR 0x4634 2259de2bdb3dSTom St Denis #define mmDCP4_PRESCALE_VALUES_OVL_Y 0x4633 2260de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_END_CNTL1 0x46A6 2261de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_END_CNTL2 0x46A7 2262de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_0_1 0x46A8 2263de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_10_11 0x46AD 2264de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_12_13 0x46AE 2265de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_14_15 0x46AF 2266de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_2_3 0x46A9 2267de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_4_5 0x46AA 2268de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_6_7 0x46AB 2269de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_REGION_8_9 0x46AC 2270de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_SLOPE_CNTL 0x46A5 2271de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLA_START_CNTL 0x46A4 2272de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_END_CNTL1 0x46B2 2273de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_END_CNTL2 0x46B3 2274de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_0_1 0x46B4 2275de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_10_11 0x46B9 2276de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_12_13 0x46BA 2277de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_14_15 0x46BB 2278de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_2_3 0x46B5 2279de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_4_5 0x46B6 2280de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_6_7 0x46B7 2281de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_REGION_8_9 0x46B8 2282de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_SLOPE_CNTL 0x46B1 2283de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CNTLB_START_CNTL 0x46B0 2284de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_CONTROL 0x46A0 2285de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_LUT_DATA 0x46A2 2286de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_LUT_INDEX 0x46A1 2287de2bdb3dSTom St Denis #define mmDCP4_REGAMMA_LUT_WRITE_EN_MASK 0x46A3 2288de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXA_TRANS_C11_C12 0x4943 2289de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXA_TRANS_C13_C14 0x4944 2290de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXA_TRANS_C21_C22 0x4945 2291de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXA_TRANS_C23_C24 0x4946 2292de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXA_TRANS_C31_C32 0x4947 2293de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXA_TRANS_C33_C34 0x4948 2294de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXB_TRANS_C11_C12 0x4949 2295de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXB_TRANS_C13_C14 0x494A 2296de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXB_TRANS_C21_C22 0x494B 2297de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXB_TRANS_C23_C24 0x494C 2298de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXB_TRANS_C31_C32 0x494D 2299de2bdb3dSTom St Denis #define mmDCP5_COMM_MATRIXB_TRANS_C33_C34 0x494E 2300de2bdb3dSTom St Denis #define mmDCP5_CUR_COLOR1 0x496C 2301de2bdb3dSTom St Denis #define mmDCP5_CUR_COLOR2 0x496D 2302de2bdb3dSTom St Denis #define mmDCP5_CUR_CONTROL 0x4966 2303de2bdb3dSTom St Denis #define mmDCP5_CUR_HOT_SPOT 0x496B 2304de2bdb3dSTom St Denis #define mmDCP5_CUR_POSITION 0x496A 2305de2bdb3dSTom St Denis #define mmDCP5_CUR_REQUEST_FILTER_CNTL 0x4999 2306de2bdb3dSTom St Denis #define mmDCP5_CUR_SIZE 0x4968 2307de2bdb3dSTom St Denis #define mmDCP5_CUR_SURFACE_ADDRESS 0x4967 2308de2bdb3dSTom St Denis #define mmDCP5_CUR_SURFACE_ADDRESS_HIGH 0x4969 2309de2bdb3dSTom St Denis #define mmDCP5_CUR_UPDATE 0x496E 2310de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_30_COLOR 0x497C 2311de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_AUTOFILL 0x497F 2312de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_BLACK_OFFSET_BLUE 0x4981 2313de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_BLACK_OFFSET_GREEN 0x4982 2314de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_BLACK_OFFSET_RED 0x4983 2315de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_CONTROL 0x4980 2316de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_PWL_DATA 0x497B 2317de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_RW_INDEX 0x4979 2318de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_RW_MODE 0x4978 2319de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_SEQ_COLOR 0x497A 2320de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_VGA_ACCESS_ENABLE 0x497D 2321de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_WHITE_OFFSET_BLUE 0x4984 2322de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_WHITE_OFFSET_GREEN 0x4985 2323de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_WHITE_OFFSET_RED 0x4986 2324de2bdb3dSTom St Denis #define mmDCP5_DC_LUT_WRITE_EN_MASK 0x497E 2325de2bdb3dSTom St Denis #define mmDCP5_DCP_CRC_CONTROL 0x4987 2326de2bdb3dSTom St Denis #define mmDCP5_DCP_CRC_CURRENT 0x4989 2327de2bdb3dSTom St Denis #define mmDCP5_DCP_CRC_LAST 0x498B 2328de2bdb3dSTom St Denis #define mmDCP5_DCP_CRC_MASK 0x4988 2329de2bdb3dSTom St Denis #define mmDCP5_DCP_DEBUG 0x498D 2330de2bdb3dSTom St Denis #define mmDCP5_DCP_DEBUG2 0x4998 2331de2bdb3dSTom St Denis #define mmDCP5_DCP_FP_CONVERTED_FIELD 0x4965 2332de2bdb3dSTom St Denis #define mmDCP5_DCP_GSL_CONTROL 0x4990 2333de2bdb3dSTom St Denis #define mmDCP5_DCP_LB_DATA_GAP_BETWEEN_CHUNK 0x4991 2334de2bdb3dSTom St Denis #define mmDCP5_DCP_RANDOM_SEEDS 0x4961 2335de2bdb3dSTom St Denis #define mmDCP5_DCP_SPATIAL_DITHER_CNTL 0x4960 2336de2bdb3dSTom St Denis #define mmDCP5_DCP_TEST_DEBUG_DATA 0x4996 2337de2bdb3dSTom St Denis #define mmDCP5_DCP_TEST_DEBUG_INDEX 0x4995 2338de2bdb3dSTom St Denis #define mmDCP5_DEGAMMA_CONTROL 0x4958 2339de2bdb3dSTom St Denis #define mmDCP5_DENORM_CONTROL 0x4950 2340de2bdb3dSTom St Denis #define mmDCP5_GAMUT_REMAP_C11_C12 0x495A 2341de2bdb3dSTom St Denis #define mmDCP5_GAMUT_REMAP_C13_C14 0x495B 2342de2bdb3dSTom St Denis #define mmDCP5_GAMUT_REMAP_C21_C22 0x495C 2343de2bdb3dSTom St Denis #define mmDCP5_GAMUT_REMAP_C23_C24 0x495D 2344de2bdb3dSTom St Denis #define mmDCP5_GAMUT_REMAP_C31_C32 0x495E 2345de2bdb3dSTom St Denis #define mmDCP5_GAMUT_REMAP_C33_C34 0x495F 2346de2bdb3dSTom St Denis #define mmDCP5_GAMUT_REMAP_CONTROL 0x4959 2347de2bdb3dSTom St Denis #define mmDCP5_GRPH_COMPRESS_PITCH 0x491A 2348de2bdb3dSTom St Denis #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS 0x4919 2349de2bdb3dSTom St Denis #define mmDCP5_GRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x491B 2350de2bdb3dSTom St Denis #define mmDCP5_GRPH_CONTROL 0x4901 2351de2bdb3dSTom St Denis #define mmDCP5_GRPH_DFQ_CONTROL 0x4914 2352de2bdb3dSTom St Denis #define mmDCP5_GRPH_DFQ_STATUS 0x4915 2353de2bdb3dSTom St Denis #define mmDCP5_GRPH_ENABLE 0x4900 2354de2bdb3dSTom St Denis #define mmDCP5_GRPH_FLIP_CONTROL 0x4912 2355de2bdb3dSTom St Denis #define mmDCP5_GRPH_INTERRUPT_CONTROL 0x4917 2356de2bdb3dSTom St Denis #define mmDCP5_GRPH_INTERRUPT_STATUS 0x4916 2357de2bdb3dSTom St Denis #define mmDCP5_GRPH_LUT_10BIT_BYPASS 0x4902 2358de2bdb3dSTom St Denis #define mmDCP5_GRPH_PITCH 0x4906 2359de2bdb3dSTom St Denis #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS 0x4904 2360de2bdb3dSTom St Denis #define mmDCP5_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x4907 2361de2bdb3dSTom St Denis #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS 0x4905 2362de2bdb3dSTom St Denis #define mmDCP5_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x4908 2363de2bdb3dSTom St Denis #define mmDCP5_GRPH_STEREOSYNC_FLIP 0x4997 2364de2bdb3dSTom St Denis #define mmDCP5_GRPH_SURFACE_ADDRESS_HIGH_INUSE 0x4918 2365de2bdb3dSTom St Denis #define mmDCP5_GRPH_SURFACE_ADDRESS_INUSE 0x4913 2366de2bdb3dSTom St Denis #define mmDCP5_GRPH_SURFACE_OFFSET_X 0x4909 2367de2bdb3dSTom St Denis #define mmDCP5_GRPH_SURFACE_OFFSET_Y 0x490A 2368de2bdb3dSTom St Denis #define mmDCP5_GRPH_SWAP_CNTL 0x4903 2369de2bdb3dSTom St Denis #define mmDCP5_GRPH_UPDATE 0x4911 2370de2bdb3dSTom St Denis #define mmDCP5_GRPH_X_END 0x490D 2371de2bdb3dSTom St Denis #define mmDCP5_GRPH_X_START 0x490B 2372de2bdb3dSTom St Denis #define mmDCP5_GRPH_Y_END 0x490E 2373de2bdb3dSTom St Denis #define mmDCP5_GRPH_Y_START 0x490C 2374de2bdb3dSTom St Denis #define mmDCP5_INPUT_CSC_C11_C12 0x4936 2375de2bdb3dSTom St Denis #define mmDCP5_INPUT_CSC_C13_C14 0x4937 2376de2bdb3dSTom St Denis #define mmDCP5_INPUT_CSC_C21_C22 0x4938 2377de2bdb3dSTom St Denis #define mmDCP5_INPUT_CSC_C23_C24 0x4939 2378de2bdb3dSTom St Denis #define mmDCP5_INPUT_CSC_C31_C32 0x493A 2379de2bdb3dSTom St Denis #define mmDCP5_INPUT_CSC_C33_C34 0x493B 2380de2bdb3dSTom St Denis #define mmDCP5_INPUT_CSC_CONTROL 0x4935 2381de2bdb3dSTom St Denis #define mmDCP5_INPUT_GAMMA_CONTROL 0x4910 2382de2bdb3dSTom St Denis #define mmDCP5_KEY_CONTROL 0x4953 2383de2bdb3dSTom St Denis #define mmDCP5_KEY_RANGE_ALPHA 0x4954 2384de2bdb3dSTom St Denis #define mmDCP5_KEY_RANGE_BLUE 0x4957 2385de2bdb3dSTom St Denis #define mmDCP5_KEY_RANGE_GREEN 0x4956 2386de2bdb3dSTom St Denis #define mmDCP5_KEY_RANGE_RED 0x4955 2387de2bdb3dSTom St Denis #define mmDCP5_OUTPUT_CSC_C11_C12 0x493D 2388de2bdb3dSTom St Denis #define mmDCP5_OUTPUT_CSC_C13_C14 0x493E 2389de2bdb3dSTom St Denis #define mmDCP5_OUTPUT_CSC_C21_C22 0x493F 2390de2bdb3dSTom St Denis #define mmDCP5_OUTPUT_CSC_C23_C24 0x4940 2391de2bdb3dSTom St Denis #define mmDCP5_OUTPUT_CSC_C31_C32 0x4941 2392de2bdb3dSTom St Denis #define mmDCP5_OUTPUT_CSC_C33_C34 0x4942 2393de2bdb3dSTom St Denis #define mmDCP5_OUTPUT_CSC_CONTROL 0x493C 2394de2bdb3dSTom St Denis #define mmDCP5_OUT_ROUND_CONTROL 0x4951 2395de2bdb3dSTom St Denis #define mmDCP5_OVL_CONTROL1 0x491D 2396de2bdb3dSTom St Denis #define mmDCP5_OVL_CONTROL2 0x491E 2397de2bdb3dSTom St Denis #define mmDCP5_OVL_DFQ_CONTROL 0x4929 2398de2bdb3dSTom St Denis #define mmDCP5_OVL_DFQ_STATUS 0x492A 2399de2bdb3dSTom St Denis #define mmDCP5_OVL_ENABLE 0x491C 2400de2bdb3dSTom St Denis #define mmDCP5_OVL_END 0x4926 2401de2bdb3dSTom St Denis #define mmDCP5_OVL_PITCH 0x4921 2402de2bdb3dSTom St Denis #define mmDCP5_OVLSCL_EDGE_PIXEL_CNTL 0x492C 2403de2bdb3dSTom St Denis #define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS 0x4992 2404de2bdb3dSTom St Denis #define mmDCP5_OVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x4994 2405de2bdb3dSTom St Denis #define mmDCP5_OVL_START 0x4925 2406de2bdb3dSTom St Denis #define mmDCP5_OVL_STEREOSYNC_FLIP 0x4993 2407de2bdb3dSTom St Denis #define mmDCP5_OVL_SURFACE_ADDRESS 0x4920 2408de2bdb3dSTom St Denis #define mmDCP5_OVL_SURFACE_ADDRESS_HIGH 0x4922 2409de2bdb3dSTom St Denis #define mmDCP5_OVL_SURFACE_ADDRESS_HIGH_INUSE 0x492B 2410de2bdb3dSTom St Denis #define mmDCP5_OVL_SURFACE_ADDRESS_INUSE 0x4928 2411de2bdb3dSTom St Denis #define mmDCP5_OVL_SURFACE_OFFSET_X 0x4923 2412de2bdb3dSTom St Denis #define mmDCP5_OVL_SURFACE_OFFSET_Y 0x4924 2413de2bdb3dSTom St Denis #define mmDCP5_OVL_SWAP_CNTL 0x491F 2414de2bdb3dSTom St Denis #define mmDCP5_OVL_UPDATE 0x4927 2415de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_GRPH_CONTROL 0x492D 2416de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_OVL_CONTROL 0x4931 2417de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_VALUES_GRPH_B 0x4930 2418de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_VALUES_GRPH_G 0x492F 2419de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_VALUES_GRPH_R 0x492E 2420de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_VALUES_OVL_CB 0x4932 2421de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_VALUES_OVL_CR 0x4934 2422de2bdb3dSTom St Denis #define mmDCP5_PRESCALE_VALUES_OVL_Y 0x4933 2423de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_END_CNTL1 0x49A6 2424de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_END_CNTL2 0x49A7 2425de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_0_1 0x49A8 2426de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_10_11 0x49AD 2427de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_12_13 0x49AE 2428de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_14_15 0x49AF 2429de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_2_3 0x49A9 2430de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_4_5 0x49AA 2431de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_6_7 0x49AB 2432de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_REGION_8_9 0x49AC 2433de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_SLOPE_CNTL 0x49A5 2434de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLA_START_CNTL 0x49A4 2435de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_END_CNTL1 0x49B2 2436de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_END_CNTL2 0x49B3 2437de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_0_1 0x49B4 2438de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_10_11 0x49B9 2439de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_12_13 0x49BA 2440de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_14_15 0x49BB 2441de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_2_3 0x49B5 2442de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_4_5 0x49B6 2443de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_6_7 0x49B7 2444de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_REGION_8_9 0x49B8 2445de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_SLOPE_CNTL 0x49B1 2446de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CNTLB_START_CNTL 0x49B0 2447de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_CONTROL 0x49A0 2448de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_LUT_DATA 0x49A2 2449de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_LUT_INDEX 0x49A1 2450de2bdb3dSTom St Denis #define mmDCP5_REGAMMA_LUT_WRITE_EN_MASK 0x49A3 2451de2bdb3dSTom St Denis #define mmDC_PAD_EXTERN_SIG 0x1902 2452de2bdb3dSTom St Denis #define mmDCP_CRC_CONTROL 0x1A87 2453de2bdb3dSTom St Denis #define mmDCP_CRC_CURRENT 0x1A89 2454de2bdb3dSTom St Denis #define mmDCP_CRC_LAST 0x1A8B 2455de2bdb3dSTom St Denis #define mmDCP_CRC_MASK 0x1A88 2456de2bdb3dSTom St Denis #define mmDCP_DEBUG 0x1A8D 2457de2bdb3dSTom St Denis #define mmDCP_DEBUG2 0x1A98 2458de2bdb3dSTom St Denis #define mmDCP_FP_CONVERTED_FIELD 0x1A65 2459de2bdb3dSTom St Denis #define mmDC_PGCNTL_STATUS_REG 0x177E 2460de2bdb3dSTom St Denis #define mmDC_PGFSM_CONFIG_REG 0x177C 2461de2bdb3dSTom St Denis #define mmDC_PGFSM_WRITE_REG 0x177D 2462de2bdb3dSTom St Denis #define mmDCP_GSL_CONTROL 0x1A90 2463de2bdb3dSTom St Denis #define mmDCPG_TEST_DEBUG_DATA 0x177B 2464de2bdb3dSTom St Denis #define mmDCPG_TEST_DEBUG_INDEX 0x1779 2465de2bdb3dSTom St Denis #define mmDC_PINSTRAPS 0x1917 2466de2bdb3dSTom St Denis #define mmDCP_LB_DATA_GAP_BETWEEN_CHUNK 0x1A91 2467de2bdb3dSTom St Denis #define mmDCP_RANDOM_SEEDS 0x1A61 2468de2bdb3dSTom St Denis #define mmDCP_SPATIAL_DITHER_CNTL 0x1A60 2469de2bdb3dSTom St Denis #define mmDCP_TEST_DEBUG_DATA 0x1A96 2470de2bdb3dSTom St Denis #define mmDCP_TEST_DEBUG_INDEX 0x1A95 2471de2bdb3dSTom St Denis #define mmDC_RBBMIF_RDWR_CNTL1 0x031A 2472de2bdb3dSTom St Denis #define mmDC_RBBMIF_RDWR_CNTL2 0x031D 2473de2bdb3dSTom St Denis #define mmDC_REF_CLK_CNTL 0x1903 2474de2bdb3dSTom St Denis #define mmDC_XDMA_INTERFACE_CNTL 0x0327 2475de2bdb3dSTom St Denis #define mmDEGAMMA_CONTROL 0x1A58 2476de2bdb3dSTom St Denis #define mmDENORM_CONTROL 0x1A50 2477de2bdb3dSTom St Denis #define mmDENTIST_DISPCLK_CNTL 0x0124 2478de2bdb3dSTom St Denis #define mmDIG0_AFMT_60958_0 0x1C41 2479de2bdb3dSTom St Denis #define mmDIG0_AFMT_60958_1 0x1C42 2480de2bdb3dSTom St Denis #define mmDIG0_AFMT_60958_2 0x1C48 2481de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x1C43 2482de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x1C49 2483de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_DBG_DTO_CNTL 0x1C52 2484de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_INFO0 0x1C3F 2485de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_INFO1 0x1C40 2486de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x1C4B 2487de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x1C17 2488de2bdb3dSTom St Denis #define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x1C4F 2489de2bdb3dSTom St Denis #define mmDIG0_AFMT_AVI_INFO0 0x1C21 2490de2bdb3dSTom St Denis #define mmDIG0_AFMT_AVI_INFO1 0x1C22 2491de2bdb3dSTom St Denis #define mmDIG0_AFMT_AVI_INFO2 0x1C23 2492de2bdb3dSTom St Denis #define mmDIG0_AFMT_AVI_INFO3 0x1C24 2493de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_0 0x1C28 2494de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_1 0x1C29 2495de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_2 0x1C2A 2496de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_3 0x1C2B 2497de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_4 0x1C2C 2498de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_5 0x1C2D 2499de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_6 0x1C2E 2500de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_7 0x1C2F 2501de2bdb3dSTom St Denis #define mmDIG0_AFMT_GENERIC_HDR 0x1C27 2502de2bdb3dSTom St Denis #define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x1C4D 2503de2bdb3dSTom St Denis #define mmDIG0_AFMT_INTERRUPT_STATUS 0x1C14 2504de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC1_0 0x1C18 2505de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC1_1 0x1C19 2506de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC1_2 0x1C1A 2507de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC1_3 0x1C1B 2508de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC1_4 0x1C1C 2509de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC2_0 0x1C1D 2510de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC2_1 0x1C1E 2511de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC2_2 0x1C1F 2512de2bdb3dSTom St Denis #define mmDIG0_AFMT_ISRC2_3 0x1C20 2513de2bdb3dSTom St Denis #define mmDIG0_AFMT_MPEG_INFO0 0x1C25 2514de2bdb3dSTom St Denis #define mmDIG0_AFMT_MPEG_INFO1 0x1C26 2515de2bdb3dSTom St Denis #define mmDIG0_AFMT_RAMP_CONTROL0 0x1C44 2516de2bdb3dSTom St Denis #define mmDIG0_AFMT_RAMP_CONTROL1 0x1C45 2517de2bdb3dSTom St Denis #define mmDIG0_AFMT_RAMP_CONTROL2 0x1C46 2518de2bdb3dSTom St Denis #define mmDIG0_AFMT_RAMP_CONTROL3 0x1C47 2519de2bdb3dSTom St Denis #define mmDIG0_AFMT_STATUS 0x1C4A 2520de2bdb3dSTom St Denis #define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x1C4C 2521de2bdb3dSTom St Denis #define mmDIG0_DIG_BE_CNTL 0x1C50 2522de2bdb3dSTom St Denis #define mmDIG0_DIG_BE_EN_CNTL 0x1C51 2523de2bdb3dSTom St Denis #define mmDIG0_DIG_CLOCK_PATTERN 0x1C03 2524de2bdb3dSTom St Denis #define mmDIG0_DIG_DISPCLK_SWITCH_CNTL 0x1C08 2525de2bdb3dSTom St Denis #define mmDIG0_DIG_DISPCLK_SWITCH_STATUS 0x1C09 2526de2bdb3dSTom St Denis #define mmDIG0_DIG_FE_CNTL 0x1C00 2527de2bdb3dSTom St Denis #define mmDIG0_DIG_FIFO_STATUS 0x1C0A 2528de2bdb3dSTom St Denis #define mmDIG0_DIG_LANE_ENABLE 0x1C8D 2529de2bdb3dSTom St Denis #define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x1C01 2530de2bdb3dSTom St Denis #define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x1C02 2531de2bdb3dSTom St Denis #define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x1C05 2532de2bdb3dSTom St Denis #define mmDIG0_DIG_TEST_PATTERN 0x1C04 2533de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_32_0 0x1C37 2534de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_32_1 0x1C38 2535de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_44_0 0x1C39 2536de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_44_1 0x1C3A 2537de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_48_0 0x1C3B 2538de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_48_1 0x1C3C 2539de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x1C0F 2540de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_STATUS_0 0x1C3D 2541de2bdb3dSTom St Denis #define mmDIG0_HDMI_ACR_STATUS_1 0x1C3E 2542de2bdb3dSTom St Denis #define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x1C0E 2543de2bdb3dSTom St Denis #define mmDIG0_HDMI_CONTROL 0x1C0C 2544de2bdb3dSTom St Denis #define mmDIG0_HDMI_GC 0x1C16 2545de2bdb3dSTom St Denis #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x1C13 2546de2bdb3dSTom St Denis #define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x1C30 2547de2bdb3dSTom St Denis #define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x1C11 2548de2bdb3dSTom St Denis #define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x1C12 2549de2bdb3dSTom St Denis #define mmDIG0_HDMI_STATUS 0x1C0D 2550de2bdb3dSTom St Denis #define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x1C10 2551de2bdb3dSTom St Denis #define mmDIG0_LVDS_DATA_CNTL 0x1C8C 2552de2bdb3dSTom St Denis #define mmDIG0_TMDS_CNTL 0x1C7C 2553de2bdb3dSTom St Denis #define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x1C7E 2554de2bdb3dSTom St Denis #define mmDIG0_TMDS_CONTROL_CHAR 0x1C7D 2555de2bdb3dSTom St Denis #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86 2556de2bdb3dSTom St Denis #define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x1C87 2557de2bdb3dSTom St Denis #define mmDIG0_TMDS_CTL_BITS 0x1C83 2558de2bdb3dSTom St Denis #define mmDIG0_TMDS_DCBALANCER_CONTROL 0x1C84 2559de2bdb3dSTom St Denis #define mmDIG0_TMDS_DEBUG 0x1C82 2560de2bdb3dSTom St Denis #define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x1C7F 2561de2bdb3dSTom St Denis #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 2562de2bdb3dSTom St Denis #define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 2563de2bdb3dSTom St Denis #define mmDIG1_AFMT_60958_0 0x1F41 2564de2bdb3dSTom St Denis #define mmDIG1_AFMT_60958_1 0x1F42 2565de2bdb3dSTom St Denis #define mmDIG1_AFMT_60958_2 0x1F48 2566de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x1F43 2567de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x1F49 2568de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_DBG_DTO_CNTL 0x1F52 2569de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_INFO0 0x1F3F 2570de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_INFO1 0x1F40 2571de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x1F4B 2572de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x1F17 2573de2bdb3dSTom St Denis #define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x1F4F 2574de2bdb3dSTom St Denis #define mmDIG1_AFMT_AVI_INFO0 0x1F21 2575de2bdb3dSTom St Denis #define mmDIG1_AFMT_AVI_INFO1 0x1F22 2576de2bdb3dSTom St Denis #define mmDIG1_AFMT_AVI_INFO2 0x1F23 2577de2bdb3dSTom St Denis #define mmDIG1_AFMT_AVI_INFO3 0x1F24 2578de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_0 0x1F28 2579de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_1 0x1F29 2580de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_2 0x1F2A 2581de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_3 0x1F2B 2582de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_4 0x1F2C 2583de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_5 0x1F2D 2584de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_6 0x1F2E 2585de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_7 0x1F2F 2586de2bdb3dSTom St Denis #define mmDIG1_AFMT_GENERIC_HDR 0x1F27 2587de2bdb3dSTom St Denis #define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x1F4D 2588de2bdb3dSTom St Denis #define mmDIG1_AFMT_INTERRUPT_STATUS 0x1F14 2589de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC1_0 0x1F18 2590de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC1_1 0x1F19 2591de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC1_2 0x1F1A 2592de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC1_3 0x1F1B 2593de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC1_4 0x1F1C 2594de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC2_0 0x1F1D 2595de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC2_1 0x1F1E 2596de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC2_2 0x1F1F 2597de2bdb3dSTom St Denis #define mmDIG1_AFMT_ISRC2_3 0x1F20 2598de2bdb3dSTom St Denis #define mmDIG1_AFMT_MPEG_INFO0 0x1F25 2599de2bdb3dSTom St Denis #define mmDIG1_AFMT_MPEG_INFO1 0x1F26 2600de2bdb3dSTom St Denis #define mmDIG1_AFMT_RAMP_CONTROL0 0x1F44 2601de2bdb3dSTom St Denis #define mmDIG1_AFMT_RAMP_CONTROL1 0x1F45 2602de2bdb3dSTom St Denis #define mmDIG1_AFMT_RAMP_CONTROL2 0x1F46 2603de2bdb3dSTom St Denis #define mmDIG1_AFMT_RAMP_CONTROL3 0x1F47 2604de2bdb3dSTom St Denis #define mmDIG1_AFMT_STATUS 0x1F4A 2605de2bdb3dSTom St Denis #define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x1F4C 2606de2bdb3dSTom St Denis #define mmDIG1_DIG_BE_CNTL 0x1F50 2607de2bdb3dSTom St Denis #define mmDIG1_DIG_BE_EN_CNTL 0x1F51 2608de2bdb3dSTom St Denis #define mmDIG1_DIG_CLOCK_PATTERN 0x1F03 2609de2bdb3dSTom St Denis #define mmDIG1_DIG_DISPCLK_SWITCH_CNTL 0x1F08 2610de2bdb3dSTom St Denis #define mmDIG1_DIG_DISPCLK_SWITCH_STATUS 0x1F09 2611de2bdb3dSTom St Denis #define mmDIG1_DIG_FE_CNTL 0x1F00 2612de2bdb3dSTom St Denis #define mmDIG1_DIG_FIFO_STATUS 0x1F0A 2613de2bdb3dSTom St Denis #define mmDIG1_DIG_LANE_ENABLE 0x1F8D 2614de2bdb3dSTom St Denis #define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x1F01 2615de2bdb3dSTom St Denis #define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x1F02 2616de2bdb3dSTom St Denis #define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x1F05 2617de2bdb3dSTom St Denis #define mmDIG1_DIG_TEST_PATTERN 0x1F04 2618de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_32_0 0x1F37 2619de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_32_1 0x1F38 2620de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_44_0 0x1F39 2621de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_44_1 0x1F3A 2622de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_48_0 0x1F3B 2623de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_48_1 0x1F3C 2624de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x1F0F 2625de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_STATUS_0 0x1F3D 2626de2bdb3dSTom St Denis #define mmDIG1_HDMI_ACR_STATUS_1 0x1F3E 2627de2bdb3dSTom St Denis #define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x1F0E 2628de2bdb3dSTom St Denis #define mmDIG1_HDMI_CONTROL 0x1F0C 2629de2bdb3dSTom St Denis #define mmDIG1_HDMI_GC 0x1F16 2630de2bdb3dSTom St Denis #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x1F13 2631de2bdb3dSTom St Denis #define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x1F30 2632de2bdb3dSTom St Denis #define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x1F11 2633de2bdb3dSTom St Denis #define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x1F12 2634de2bdb3dSTom St Denis #define mmDIG1_HDMI_STATUS 0x1F0D 2635de2bdb3dSTom St Denis #define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x1F10 2636de2bdb3dSTom St Denis #define mmDIG1_LVDS_DATA_CNTL 0x1F8C 2637de2bdb3dSTom St Denis #define mmDIG1_TMDS_CNTL 0x1F7C 2638de2bdb3dSTom St Denis #define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x1F7E 2639de2bdb3dSTom St Denis #define mmDIG1_TMDS_CONTROL_CHAR 0x1F7D 2640de2bdb3dSTom St Denis #define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x1F86 2641de2bdb3dSTom St Denis #define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x1F87 2642de2bdb3dSTom St Denis #define mmDIG1_TMDS_CTL_BITS 0x1F83 2643de2bdb3dSTom St Denis #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84 2644de2bdb3dSTom St Denis #define mmDIG1_TMDS_DEBUG 0x1F82 2645de2bdb3dSTom St Denis #define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x1F7F 2646de2bdb3dSTom St Denis #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x1F80 2647de2bdb3dSTom St Denis #define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x1F81 2648de2bdb3dSTom St Denis #define mmDIG2_AFMT_60958_0 0x4241 2649de2bdb3dSTom St Denis #define mmDIG2_AFMT_60958_1 0x4242 2650de2bdb3dSTom St Denis #define mmDIG2_AFMT_60958_2 0x4248 2651de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x4243 2652de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x4249 2653de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_DBG_DTO_CNTL 0x4252 2654de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_INFO0 0x423F 2655de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_INFO1 0x4240 2656de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x424B 2657de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x4217 2658de2bdb3dSTom St Denis #define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x424F 2659de2bdb3dSTom St Denis #define mmDIG2_AFMT_AVI_INFO0 0x4221 2660de2bdb3dSTom St Denis #define mmDIG2_AFMT_AVI_INFO1 0x4222 2661de2bdb3dSTom St Denis #define mmDIG2_AFMT_AVI_INFO2 0x4223 2662de2bdb3dSTom St Denis #define mmDIG2_AFMT_AVI_INFO3 0x4224 2663de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_0 0x4228 2664de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_1 0x4229 2665de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_2 0x422A 2666de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_3 0x422B 2667de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_4 0x422C 2668de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_5 0x422D 2669de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_6 0x422E 2670de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_7 0x422F 2671de2bdb3dSTom St Denis #define mmDIG2_AFMT_GENERIC_HDR 0x4227 2672de2bdb3dSTom St Denis #define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x424D 2673de2bdb3dSTom St Denis #define mmDIG2_AFMT_INTERRUPT_STATUS 0x4214 2674de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC1_0 0x4218 2675de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC1_1 0x4219 2676de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC1_2 0x421A 2677de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC1_3 0x421B 2678de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC1_4 0x421C 2679de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC2_0 0x421D 2680de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC2_1 0x421E 2681de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC2_2 0x421F 2682de2bdb3dSTom St Denis #define mmDIG2_AFMT_ISRC2_3 0x4220 2683de2bdb3dSTom St Denis #define mmDIG2_AFMT_MPEG_INFO0 0x4225 2684de2bdb3dSTom St Denis #define mmDIG2_AFMT_MPEG_INFO1 0x4226 2685de2bdb3dSTom St Denis #define mmDIG2_AFMT_RAMP_CONTROL0 0x4244 2686de2bdb3dSTom St Denis #define mmDIG2_AFMT_RAMP_CONTROL1 0x4245 2687de2bdb3dSTom St Denis #define mmDIG2_AFMT_RAMP_CONTROL2 0x4246 2688de2bdb3dSTom St Denis #define mmDIG2_AFMT_RAMP_CONTROL3 0x4247 2689de2bdb3dSTom St Denis #define mmDIG2_AFMT_STATUS 0x424A 2690de2bdb3dSTom St Denis #define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x424C 2691de2bdb3dSTom St Denis #define mmDIG2_DIG_BE_CNTL 0x4250 2692de2bdb3dSTom St Denis #define mmDIG2_DIG_BE_EN_CNTL 0x4251 2693de2bdb3dSTom St Denis #define mmDIG2_DIG_CLOCK_PATTERN 0x4203 2694de2bdb3dSTom St Denis #define mmDIG2_DIG_DISPCLK_SWITCH_CNTL 0x4208 2695de2bdb3dSTom St Denis #define mmDIG2_DIG_DISPCLK_SWITCH_STATUS 0x4209 2696de2bdb3dSTom St Denis #define mmDIG2_DIG_FE_CNTL 0x4200 2697de2bdb3dSTom St Denis #define mmDIG2_DIG_FIFO_STATUS 0x420A 2698de2bdb3dSTom St Denis #define mmDIG2_DIG_LANE_ENABLE 0x428D 2699de2bdb3dSTom St Denis #define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x4201 2700de2bdb3dSTom St Denis #define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x4202 2701de2bdb3dSTom St Denis #define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x4205 2702de2bdb3dSTom St Denis #define mmDIG2_DIG_TEST_PATTERN 0x4204 2703de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_32_0 0x4237 2704de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_32_1 0x4238 2705de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_44_0 0x4239 2706de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_44_1 0x423A 2707de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_48_0 0x423B 2708de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_48_1 0x423C 2709de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x420F 2710de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_STATUS_0 0x423D 2711de2bdb3dSTom St Denis #define mmDIG2_HDMI_ACR_STATUS_1 0x423E 2712de2bdb3dSTom St Denis #define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x420E 2713de2bdb3dSTom St Denis #define mmDIG2_HDMI_CONTROL 0x420C 2714de2bdb3dSTom St Denis #define mmDIG2_HDMI_GC 0x4216 2715de2bdb3dSTom St Denis #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x4213 2716de2bdb3dSTom St Denis #define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x4230 2717de2bdb3dSTom St Denis #define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x4211 2718de2bdb3dSTom St Denis #define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x4212 2719de2bdb3dSTom St Denis #define mmDIG2_HDMI_STATUS 0x420D 2720de2bdb3dSTom St Denis #define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x4210 2721de2bdb3dSTom St Denis #define mmDIG2_LVDS_DATA_CNTL 0x428C 2722de2bdb3dSTom St Denis #define mmDIG2_TMDS_CNTL 0x427C 2723de2bdb3dSTom St Denis #define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x427E 2724de2bdb3dSTom St Denis #define mmDIG2_TMDS_CONTROL_CHAR 0x427D 2725de2bdb3dSTom St Denis #define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x4286 2726de2bdb3dSTom St Denis #define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x4287 2727de2bdb3dSTom St Denis #define mmDIG2_TMDS_CTL_BITS 0x4283 2728de2bdb3dSTom St Denis #define mmDIG2_TMDS_DCBALANCER_CONTROL 0x4284 2729de2bdb3dSTom St Denis #define mmDIG2_TMDS_DEBUG 0x4282 2730de2bdb3dSTom St Denis #define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x427F 2731de2bdb3dSTom St Denis #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x4280 2732de2bdb3dSTom St Denis #define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x4281 2733de2bdb3dSTom St Denis #define mmDIG3_AFMT_60958_0 0x4541 2734de2bdb3dSTom St Denis #define mmDIG3_AFMT_60958_1 0x4542 2735de2bdb3dSTom St Denis #define mmDIG3_AFMT_60958_2 0x4548 2736de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x4543 2737de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x4549 2738de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_DBG_DTO_CNTL 0x4552 2739de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_INFO0 0x453F 2740de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_INFO1 0x4540 2741de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x454B 2742de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x4517 2743de2bdb3dSTom St Denis #define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x454F 2744de2bdb3dSTom St Denis #define mmDIG3_AFMT_AVI_INFO0 0x4521 2745de2bdb3dSTom St Denis #define mmDIG3_AFMT_AVI_INFO1 0x4522 2746de2bdb3dSTom St Denis #define mmDIG3_AFMT_AVI_INFO2 0x4523 2747de2bdb3dSTom St Denis #define mmDIG3_AFMT_AVI_INFO3 0x4524 2748de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_0 0x4528 2749de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_1 0x4529 2750de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_2 0x452A 2751de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_3 0x452B 2752de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_4 0x452C 2753de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_5 0x452D 2754de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_6 0x452E 2755de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_7 0x452F 2756de2bdb3dSTom St Denis #define mmDIG3_AFMT_GENERIC_HDR 0x4527 2757de2bdb3dSTom St Denis #define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x454D 2758de2bdb3dSTom St Denis #define mmDIG3_AFMT_INTERRUPT_STATUS 0x4514 2759de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC1_0 0x4518 2760de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC1_1 0x4519 2761de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC1_2 0x451A 2762de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC1_3 0x451B 2763de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC1_4 0x451C 2764de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC2_0 0x451D 2765de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC2_1 0x451E 2766de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC2_2 0x451F 2767de2bdb3dSTom St Denis #define mmDIG3_AFMT_ISRC2_3 0x4520 2768de2bdb3dSTom St Denis #define mmDIG3_AFMT_MPEG_INFO0 0x4525 2769de2bdb3dSTom St Denis #define mmDIG3_AFMT_MPEG_INFO1 0x4526 2770de2bdb3dSTom St Denis #define mmDIG3_AFMT_RAMP_CONTROL0 0x4544 2771de2bdb3dSTom St Denis #define mmDIG3_AFMT_RAMP_CONTROL1 0x4545 2772de2bdb3dSTom St Denis #define mmDIG3_AFMT_RAMP_CONTROL2 0x4546 2773de2bdb3dSTom St Denis #define mmDIG3_AFMT_RAMP_CONTROL3 0x4547 2774de2bdb3dSTom St Denis #define mmDIG3_AFMT_STATUS 0x454A 2775de2bdb3dSTom St Denis #define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x454C 2776de2bdb3dSTom St Denis #define mmDIG3_DIG_BE_CNTL 0x4550 2777de2bdb3dSTom St Denis #define mmDIG3_DIG_BE_EN_CNTL 0x4551 2778de2bdb3dSTom St Denis #define mmDIG3_DIG_CLOCK_PATTERN 0x4503 2779de2bdb3dSTom St Denis #define mmDIG3_DIG_DISPCLK_SWITCH_CNTL 0x4508 2780de2bdb3dSTom St Denis #define mmDIG3_DIG_DISPCLK_SWITCH_STATUS 0x4509 2781de2bdb3dSTom St Denis #define mmDIG3_DIG_FE_CNTL 0x4500 2782de2bdb3dSTom St Denis #define mmDIG3_DIG_FIFO_STATUS 0x450A 2783de2bdb3dSTom St Denis #define mmDIG3_DIG_LANE_ENABLE 0x458D 2784de2bdb3dSTom St Denis #define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x4501 2785de2bdb3dSTom St Denis #define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x4502 2786de2bdb3dSTom St Denis #define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x4505 2787de2bdb3dSTom St Denis #define mmDIG3_DIG_TEST_PATTERN 0x4504 2788de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_32_0 0x4537 2789de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_32_1 0x4538 2790de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_44_0 0x4539 2791de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_44_1 0x453A 2792de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_48_0 0x453B 2793de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_48_1 0x453C 2794de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x450F 2795de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_STATUS_0 0x453D 2796de2bdb3dSTom St Denis #define mmDIG3_HDMI_ACR_STATUS_1 0x453E 2797de2bdb3dSTom St Denis #define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x450E 2798de2bdb3dSTom St Denis #define mmDIG3_HDMI_CONTROL 0x450C 2799de2bdb3dSTom St Denis #define mmDIG3_HDMI_GC 0x4516 2800de2bdb3dSTom St Denis #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x4513 2801de2bdb3dSTom St Denis #define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x4530 2802de2bdb3dSTom St Denis #define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x4511 2803de2bdb3dSTom St Denis #define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x4512 2804de2bdb3dSTom St Denis #define mmDIG3_HDMI_STATUS 0x450D 2805de2bdb3dSTom St Denis #define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x4510 2806de2bdb3dSTom St Denis #define mmDIG3_LVDS_DATA_CNTL 0x458C 2807de2bdb3dSTom St Denis #define mmDIG3_TMDS_CNTL 0x457C 2808de2bdb3dSTom St Denis #define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x457E 2809de2bdb3dSTom St Denis #define mmDIG3_TMDS_CONTROL_CHAR 0x457D 2810de2bdb3dSTom St Denis #define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x4586 2811de2bdb3dSTom St Denis #define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x4587 2812de2bdb3dSTom St Denis #define mmDIG3_TMDS_CTL_BITS 0x4583 2813de2bdb3dSTom St Denis #define mmDIG3_TMDS_DCBALANCER_CONTROL 0x4584 2814de2bdb3dSTom St Denis #define mmDIG3_TMDS_DEBUG 0x4582 2815de2bdb3dSTom St Denis #define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x457F 2816de2bdb3dSTom St Denis #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x4580 2817de2bdb3dSTom St Denis #define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x4581 2818de2bdb3dSTom St Denis #define mmDIG4_AFMT_60958_0 0x4841 2819de2bdb3dSTom St Denis #define mmDIG4_AFMT_60958_1 0x4842 2820de2bdb3dSTom St Denis #define mmDIG4_AFMT_60958_2 0x4848 2821de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x4843 2822de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x4849 2823de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_DBG_DTO_CNTL 0x4852 2824de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_INFO0 0x483F 2825de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_INFO1 0x4840 2826de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x484B 2827de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x4817 2828de2bdb3dSTom St Denis #define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x484F 2829de2bdb3dSTom St Denis #define mmDIG4_AFMT_AVI_INFO0 0x4821 2830de2bdb3dSTom St Denis #define mmDIG4_AFMT_AVI_INFO1 0x4822 2831de2bdb3dSTom St Denis #define mmDIG4_AFMT_AVI_INFO2 0x4823 2832de2bdb3dSTom St Denis #define mmDIG4_AFMT_AVI_INFO3 0x4824 2833de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_0 0x4828 2834de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_1 0x4829 2835de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_2 0x482A 2836de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_3 0x482B 2837de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_4 0x482C 2838de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_5 0x482D 2839de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_6 0x482E 2840de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_7 0x482F 2841de2bdb3dSTom St Denis #define mmDIG4_AFMT_GENERIC_HDR 0x4827 2842de2bdb3dSTom St Denis #define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x484D 2843de2bdb3dSTom St Denis #define mmDIG4_AFMT_INTERRUPT_STATUS 0x4814 2844de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC1_0 0x4818 2845de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC1_1 0x4819 2846de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC1_2 0x481A 2847de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC1_3 0x481B 2848de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC1_4 0x481C 2849de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC2_0 0x481D 2850de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC2_1 0x481E 2851de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC2_2 0x481F 2852de2bdb3dSTom St Denis #define mmDIG4_AFMT_ISRC2_3 0x4820 2853de2bdb3dSTom St Denis #define mmDIG4_AFMT_MPEG_INFO0 0x4825 2854de2bdb3dSTom St Denis #define mmDIG4_AFMT_MPEG_INFO1 0x4826 2855de2bdb3dSTom St Denis #define mmDIG4_AFMT_RAMP_CONTROL0 0x4844 2856de2bdb3dSTom St Denis #define mmDIG4_AFMT_RAMP_CONTROL1 0x4845 2857de2bdb3dSTom St Denis #define mmDIG4_AFMT_RAMP_CONTROL2 0x4846 2858de2bdb3dSTom St Denis #define mmDIG4_AFMT_RAMP_CONTROL3 0x4847 2859de2bdb3dSTom St Denis #define mmDIG4_AFMT_STATUS 0x484A 2860de2bdb3dSTom St Denis #define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x484C 2861de2bdb3dSTom St Denis #define mmDIG4_DIG_BE_CNTL 0x4850 2862de2bdb3dSTom St Denis #define mmDIG4_DIG_BE_EN_CNTL 0x4851 2863de2bdb3dSTom St Denis #define mmDIG4_DIG_CLOCK_PATTERN 0x4803 2864de2bdb3dSTom St Denis #define mmDIG4_DIG_DISPCLK_SWITCH_CNTL 0x4808 2865de2bdb3dSTom St Denis #define mmDIG4_DIG_DISPCLK_SWITCH_STATUS 0x4809 2866de2bdb3dSTom St Denis #define mmDIG4_DIG_FE_CNTL 0x4800 2867de2bdb3dSTom St Denis #define mmDIG4_DIG_FIFO_STATUS 0x480A 2868de2bdb3dSTom St Denis #define mmDIG4_DIG_LANE_ENABLE 0x488D 2869de2bdb3dSTom St Denis #define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x4801 2870de2bdb3dSTom St Denis #define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x4802 2871de2bdb3dSTom St Denis #define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x4805 2872de2bdb3dSTom St Denis #define mmDIG4_DIG_TEST_PATTERN 0x4804 2873de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_32_0 0x4837 2874de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_32_1 0x4838 2875de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_44_0 0x4839 2876de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_44_1 0x483A 2877de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_48_0 0x483B 2878de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_48_1 0x483C 2879de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x480F 2880de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_STATUS_0 0x483D 2881de2bdb3dSTom St Denis #define mmDIG4_HDMI_ACR_STATUS_1 0x483E 2882de2bdb3dSTom St Denis #define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x480E 2883de2bdb3dSTom St Denis #define mmDIG4_HDMI_CONTROL 0x480C 2884de2bdb3dSTom St Denis #define mmDIG4_HDMI_GC 0x4816 2885de2bdb3dSTom St Denis #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x4813 2886de2bdb3dSTom St Denis #define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x4830 2887de2bdb3dSTom St Denis #define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x4811 2888de2bdb3dSTom St Denis #define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x4812 2889de2bdb3dSTom St Denis #define mmDIG4_HDMI_STATUS 0x480D 2890de2bdb3dSTom St Denis #define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x4810 2891de2bdb3dSTom St Denis #define mmDIG4_LVDS_DATA_CNTL 0x488C 2892de2bdb3dSTom St Denis #define mmDIG4_TMDS_CNTL 0x487C 2893de2bdb3dSTom St Denis #define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x487E 2894de2bdb3dSTom St Denis #define mmDIG4_TMDS_CONTROL_CHAR 0x487D 2895de2bdb3dSTom St Denis #define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x4886 2896de2bdb3dSTom St Denis #define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x4887 2897de2bdb3dSTom St Denis #define mmDIG4_TMDS_CTL_BITS 0x4883 2898de2bdb3dSTom St Denis #define mmDIG4_TMDS_DCBALANCER_CONTROL 0x4884 2899de2bdb3dSTom St Denis #define mmDIG4_TMDS_DEBUG 0x4882 2900de2bdb3dSTom St Denis #define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x487F 2901de2bdb3dSTom St Denis #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x4880 2902de2bdb3dSTom St Denis #define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x4881 2903de2bdb3dSTom St Denis #define mmDIG5_AFMT_60958_0 0x4B41 2904de2bdb3dSTom St Denis #define mmDIG5_AFMT_60958_1 0x4B42 2905de2bdb3dSTom St Denis #define mmDIG5_AFMT_60958_2 0x4B48 2906de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x4B43 2907de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x4B49 2908de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_DBG_DTO_CNTL 0x4B52 2909de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_INFO0 0x4B3F 2910de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_INFO1 0x4B40 2911de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x4B4B 2912de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x4B17 2913de2bdb3dSTom St Denis #define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x4B4F 2914de2bdb3dSTom St Denis #define mmDIG5_AFMT_AVI_INFO0 0x4B21 2915de2bdb3dSTom St Denis #define mmDIG5_AFMT_AVI_INFO1 0x4B22 2916de2bdb3dSTom St Denis #define mmDIG5_AFMT_AVI_INFO2 0x4B23 2917de2bdb3dSTom St Denis #define mmDIG5_AFMT_AVI_INFO3 0x4B24 2918de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_0 0x4B28 2919de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_1 0x4B29 2920de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_2 0x4B2A 2921de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_3 0x4B2B 2922de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_4 0x4B2C 2923de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_5 0x4B2D 2924de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_6 0x4B2E 2925de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_7 0x4B2F 2926de2bdb3dSTom St Denis #define mmDIG5_AFMT_GENERIC_HDR 0x4B27 2927de2bdb3dSTom St Denis #define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x4B4D 2928de2bdb3dSTom St Denis #define mmDIG5_AFMT_INTERRUPT_STATUS 0x4B14 2929de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC1_0 0x4B18 2930de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC1_1 0x4B19 2931de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC1_2 0x4B1A 2932de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC1_3 0x4B1B 2933de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC1_4 0x4B1C 2934de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC2_0 0x4B1D 2935de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC2_1 0x4B1E 2936de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC2_2 0x4B1F 2937de2bdb3dSTom St Denis #define mmDIG5_AFMT_ISRC2_3 0x4B20 2938de2bdb3dSTom St Denis #define mmDIG5_AFMT_MPEG_INFO0 0x4B25 2939de2bdb3dSTom St Denis #define mmDIG5_AFMT_MPEG_INFO1 0x4B26 2940de2bdb3dSTom St Denis #define mmDIG5_AFMT_RAMP_CONTROL0 0x4B44 2941de2bdb3dSTom St Denis #define mmDIG5_AFMT_RAMP_CONTROL1 0x4B45 2942de2bdb3dSTom St Denis #define mmDIG5_AFMT_RAMP_CONTROL2 0x4B46 2943de2bdb3dSTom St Denis #define mmDIG5_AFMT_RAMP_CONTROL3 0x4B47 2944de2bdb3dSTom St Denis #define mmDIG5_AFMT_STATUS 0x4B4A 2945de2bdb3dSTom St Denis #define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x4B4C 2946de2bdb3dSTom St Denis #define mmDIG5_DIG_BE_CNTL 0x4B50 2947de2bdb3dSTom St Denis #define mmDIG5_DIG_BE_EN_CNTL 0x4B51 2948de2bdb3dSTom St Denis #define mmDIG5_DIG_CLOCK_PATTERN 0x4B03 2949de2bdb3dSTom St Denis #define mmDIG5_DIG_DISPCLK_SWITCH_CNTL 0x4B08 2950de2bdb3dSTom St Denis #define mmDIG5_DIG_DISPCLK_SWITCH_STATUS 0x4B09 2951de2bdb3dSTom St Denis #define mmDIG5_DIG_FE_CNTL 0x4B00 2952de2bdb3dSTom St Denis #define mmDIG5_DIG_FIFO_STATUS 0x4B0A 2953de2bdb3dSTom St Denis #define mmDIG5_DIG_LANE_ENABLE 0x4B8D 2954de2bdb3dSTom St Denis #define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x4B01 2955de2bdb3dSTom St Denis #define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x4B02 2956de2bdb3dSTom St Denis #define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x4B05 2957de2bdb3dSTom St Denis #define mmDIG5_DIG_TEST_PATTERN 0x4B04 2958de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_32_0 0x4B37 2959de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_32_1 0x4B38 2960de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_44_0 0x4B39 2961de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_44_1 0x4B3A 2962de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_48_0 0x4B3B 2963de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_48_1 0x4B3C 2964de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x4B0F 2965de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_STATUS_0 0x4B3D 2966de2bdb3dSTom St Denis #define mmDIG5_HDMI_ACR_STATUS_1 0x4B3E 2967de2bdb3dSTom St Denis #define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x4B0E 2968de2bdb3dSTom St Denis #define mmDIG5_HDMI_CONTROL 0x4B0C 2969de2bdb3dSTom St Denis #define mmDIG5_HDMI_GC 0x4B16 2970de2bdb3dSTom St Denis #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x4B13 2971de2bdb3dSTom St Denis #define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x4B30 2972de2bdb3dSTom St Denis #define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x4B11 2973de2bdb3dSTom St Denis #define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x4B12 2974de2bdb3dSTom St Denis #define mmDIG5_HDMI_STATUS 0x4B0D 2975de2bdb3dSTom St Denis #define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x4B10 2976de2bdb3dSTom St Denis #define mmDIG5_LVDS_DATA_CNTL 0x4B8C 2977de2bdb3dSTom St Denis #define mmDIG5_TMDS_CNTL 0x4B7C 2978de2bdb3dSTom St Denis #define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x4B7E 2979de2bdb3dSTom St Denis #define mmDIG5_TMDS_CONTROL_CHAR 0x4B7D 2980de2bdb3dSTom St Denis #define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x4B86 2981de2bdb3dSTom St Denis #define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x4B87 2982de2bdb3dSTom St Denis #define mmDIG5_TMDS_CTL_BITS 0x4B83 2983de2bdb3dSTom St Denis #define mmDIG5_TMDS_DCBALANCER_CONTROL 0x4B84 2984de2bdb3dSTom St Denis #define mmDIG5_TMDS_DEBUG 0x4B82 2985de2bdb3dSTom St Denis #define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x4B7F 2986de2bdb3dSTom St Denis #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x4B80 2987de2bdb3dSTom St Denis #define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x4B81 2988de2bdb3dSTom St Denis #define mmDIG_BE_CNTL 0x1C50 2989de2bdb3dSTom St Denis #define mmDIG_BE_EN_CNTL 0x1C51 2990de2bdb3dSTom St Denis #define mmDIG_CLOCK_PATTERN 0x1C03 2991de2bdb3dSTom St Denis #define mmDIG_DISPCLK_SWITCH_CNTL 0x1C08 2992de2bdb3dSTom St Denis #define mmDIG_DISPCLK_SWITCH_STATUS 0x1C09 2993de2bdb3dSTom St Denis #define mmDIG_FE_CNTL 0x1C00 2994de2bdb3dSTom St Denis #define mmDIG_FIFO_STATUS 0x1C0A 2995de2bdb3dSTom St Denis #define mmDIG_LANE_ENABLE 0x1C8D 2996de2bdb3dSTom St Denis #define mmDIG_OUTPUT_CRC_CNTL 0x1C01 2997de2bdb3dSTom St Denis #define mmDIG_OUTPUT_CRC_RESULT 0x1C02 2998de2bdb3dSTom St Denis #define mmDIG_RANDOM_PATTERN_SEED 0x1C05 2999de2bdb3dSTom St Denis #define mmDIG_SOFT_RESET 0x013D 3000de2bdb3dSTom St Denis #define mmDIG_TEST_PATTERN 0x1C04 3001de2bdb3dSTom St Denis #define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0135 3002de2bdb3dSTom St Denis #define mmDISPCLK_FREQ_CHANGE_CNTL 0x0131 3003de2bdb3dSTom St Denis #define mmDISP_INTERRUPT_STATUS 0x183D 3004de2bdb3dSTom St Denis #define mmDISP_INTERRUPT_STATUS_CONTINUE 0x183E 3005de2bdb3dSTom St Denis #define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x183F 3006de2bdb3dSTom St Denis #define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x1840 3007de2bdb3dSTom St Denis #define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x1853 3008de2bdb3dSTom St Denis #define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x1854 3009de2bdb3dSTom St Denis #define mmDISPOUT_STEREOSYNC_SEL 0x18BF 3010de2bdb3dSTom St Denis #define mmDISPPLL_BG_CNTL 0x013C 3011de2bdb3dSTom St Denis #define mmDISP_TIMER_CONTROL 0x1842 3012de2bdb3dSTom St Denis #define mmDMCU_CTRL 0x1600 3013de2bdb3dSTom St Denis #define mmDMCU_ERAM_RD_CTRL 0x160B 3014de2bdb3dSTom St Denis #define mmDMCU_ERAM_RD_DATA 0x160C 3015de2bdb3dSTom St Denis #define mmDMCU_ERAM_WR_CTRL 0x1609 3016de2bdb3dSTom St Denis #define mmDMCU_ERAM_WR_DATA 0x160A 3017de2bdb3dSTom St Denis #define mmDMCU_EVENT_TRIGGER 0x1611 3018de2bdb3dSTom St Denis #define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x161A 3019de2bdb3dSTom St Denis #define mmDMCU_FW_CS_HI 0x1606 3020de2bdb3dSTom St Denis #define mmDMCU_FW_CS_LO 0x1607 3021de2bdb3dSTom St Denis #define mmDMCU_FW_END_ADDR 0x1604 3022de2bdb3dSTom St Denis #define mmDMCU_FW_ISR_START_ADDR 0x1605 3023de2bdb3dSTom St Denis #define mmDMCU_FW_START_ADDR 0x1603 3024de2bdb3dSTom St Denis #define mmDMCU_INT_CNT 0x1619 3025de2bdb3dSTom St Denis #define mmDMCU_INTERRUPT_STATUS 0x1614 3026de2bdb3dSTom St Denis #define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x1615 3027de2bdb3dSTom St Denis #define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x1616 3028de2bdb3dSTom St Denis #define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x1617 3029de2bdb3dSTom St Denis #define mmDMCU_IRAM_RD_CTRL 0x160F 3030de2bdb3dSTom St Denis #define mmDMCU_IRAM_RD_DATA 0x1610 3031de2bdb3dSTom St Denis #define mmDMCU_IRAM_WR_CTRL 0x160D 3032de2bdb3dSTom St Denis #define mmDMCU_IRAM_WR_DATA 0x160E 3033de2bdb3dSTom St Denis #define mmDMCU_PC_START_ADDR 0x1602 3034de2bdb3dSTom St Denis #define mmDMCU_RAM_ACCESS_CTRL 0x1608 3035de2bdb3dSTom St Denis #define mmDMCU_STATUS 0x1601 3036de2bdb3dSTom St Denis #define mmDMCU_TEST_DEBUG_DATA 0x1627 3037de2bdb3dSTom St Denis #define mmDMCU_TEST_DEBUG_INDEX 0x1626 3038de2bdb3dSTom St Denis #define mmDMCU_UC_CLK_GATING_CNTL 0x161B 3039de2bdb3dSTom St Denis #define mmDMCU_UC_INTERNAL_INT_STATUS 0x1612 3040de2bdb3dSTom St Denis #define mmDMIF_ADDR_CALC 0x0300 3041de2bdb3dSTom St Denis #define mmDMIF_ADDR_CONFIG 0x02F5 3042de2bdb3dSTom St Denis #define mmDMIF_ARBITRATION_CONTROL 0x02F9 3043de2bdb3dSTom St Denis #define mmDMIF_CONTROL 0x02F6 3044de2bdb3dSTom St Denis #define mmDMIF_HW_DEBUG 0x02F8 3045de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL1 0x1B30 3046de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL2 0x1B31 3047de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_PIPE_DPM_CONTROL 0x1B34 3048de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 3049de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL 0x1B35 3050de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 3051de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_PIPE_URGENCY_CONTROL 0x1B33 3052de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_TEST_DEBUG_DATA 0x1B39 3053de2bdb3dSTom St Denis #define mmDMIF_PG0_DPG_TEST_DEBUG_INDEX 0x1B38 3054de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL1 0x1E30 3055de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL2 0x1E31 3056de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_PIPE_DPM_CONTROL 0x1E34 3057de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1E36 3058de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL 0x1E35 3059de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1E37 3060de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_PIPE_URGENCY_CONTROL 0x1E33 3061de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_TEST_DEBUG_DATA 0x1E39 3062de2bdb3dSTom St Denis #define mmDMIF_PG1_DPG_TEST_DEBUG_INDEX 0x1E38 3063de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL1 0x4130 3064de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL2 0x4131 3065de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_PIPE_DPM_CONTROL 0x4134 3066de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4136 3067de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL 0x4135 3068de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4137 3069de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_PIPE_URGENCY_CONTROL 0x4133 3070de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_TEST_DEBUG_DATA 0x4139 3071de2bdb3dSTom St Denis #define mmDMIF_PG2_DPG_TEST_DEBUG_INDEX 0x4138 3072de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL1 0x4430 3073de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL2 0x4431 3074de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_PIPE_DPM_CONTROL 0x4434 3075de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4436 3076de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL 0x4435 3077de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4437 3078de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_PIPE_URGENCY_CONTROL 0x4433 3079de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_TEST_DEBUG_DATA 0x4439 3080de2bdb3dSTom St Denis #define mmDMIF_PG3_DPG_TEST_DEBUG_INDEX 0x4438 3081de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL1 0x4730 3082de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL2 0x4731 3083de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_PIPE_DPM_CONTROL 0x4734 3084de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4736 3085de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL 0x4735 3086de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4737 3087de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_PIPE_URGENCY_CONTROL 0x4733 3088de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_TEST_DEBUG_DATA 0x4739 3089de2bdb3dSTom St Denis #define mmDMIF_PG4_DPG_TEST_DEBUG_INDEX 0x4738 3090de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL1 0x4A30 3091de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL2 0x4A31 3092de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_PIPE_DPM_CONTROL 0x4A34 3093de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x4A36 3094de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL 0x4A35 3095de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x4A37 3096de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_PIPE_URGENCY_CONTROL 0x4A33 3097de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_TEST_DEBUG_DATA 0x4A39 3098de2bdb3dSTom St Denis #define mmDMIF_PG5_DPG_TEST_DEBUG_INDEX 0x4A38 3099de2bdb3dSTom St Denis #define mmDMIF_STATUS 0x02F7 3100de2bdb3dSTom St Denis #define mmDMIF_STATUS2 0x0301 3101de2bdb3dSTom St Denis #define mmDMIF_TEST_DEBUG_DATA 0x0313 3102de2bdb3dSTom St Denis #define mmDMIF_TEST_DEBUG_INDEX 0x0312 3103de2bdb3dSTom St Denis #define mmDOUT_DCE_VCE_CONTROL 0x18FF 3104de2bdb3dSTom St Denis #define mmDOUT_POWER_MANAGEMENT_CNTL 0x1841 3105de2bdb3dSTom St Denis #define mmDOUT_SCRATCH0 0x1844 3106de2bdb3dSTom St Denis #define mmDOUT_SCRATCH1 0x1845 3107de2bdb3dSTom St Denis #define mmDOUT_SCRATCH2 0x1846 3108de2bdb3dSTom St Denis #define mmDOUT_SCRATCH3 0x1847 3109de2bdb3dSTom St Denis #define mmDOUT_SCRATCH4 0x1848 3110de2bdb3dSTom St Denis #define mmDOUT_SCRATCH5 0x1849 3111de2bdb3dSTom St Denis #define mmDOUT_SCRATCH6 0x184A 3112de2bdb3dSTom St Denis #define mmDOUT_SCRATCH7 0x184B 3113de2bdb3dSTom St Denis #define mmDOUT_TEST_DEBUG_DATA 0x184E 3114de2bdb3dSTom St Denis #define mmDOUT_TEST_DEBUG_INDEX 0x184D 3115de2bdb3dSTom St Denis #define mmDP0_DP_CONFIG 0x1CC2 3116de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_8B10B_CNTL 0x1CD3 3117de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_CNTL 0x1CD0 3118de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_CRC_CNTL 0x1CD7 3119de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_CRC_EN 0x1CD6 3120de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_CRC_MST_CNTL 0x1CC6 3121de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_CRC_MST_STATUS 0x1CC7 3122de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_CRC_RESULT 0x1CD8 3123de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE 3124de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x1CE9 3125de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_PRBS_CNTL 0x1CD4 3126de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_SYM0 0x1CD2 3127de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_SYM1 0x1CE0 3128de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_SYM2 0x1CDF 3129de2bdb3dSTom St Denis #define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 3130de2bdb3dSTom St Denis #define mmDP0_DP_HBR2_EYE_PATTERN 0x1CC8 3131de2bdb3dSTom St Denis #define mmDP0_DP_LINK_CNTL 0x1CC0 3132de2bdb3dSTom St Denis #define mmDP0_DP_LINK_FRAMING_CNTL 0x1CCC 3133de2bdb3dSTom St Denis #define mmDP0_DP_MSA_COLORIMETRY 0x1CDA 3134de2bdb3dSTom St Denis #define mmDP0_DP_MSA_MISC 0x1CC5 3135de2bdb3dSTom St Denis #define mmDP0_DP_MSA_V_TIMING_OVERRIDE1 0x1CEA 3136de2bdb3dSTom St Denis #define mmDP0_DP_MSA_V_TIMING_OVERRIDE2 0x1CEB 3137de2bdb3dSTom St Denis #define mmDP0_DP_MSE_LINK_TIMING 0x1CE8 3138de2bdb3dSTom St Denis #define mmDP0_DP_MSE_MISC_CNTL 0x1CDB 3139de2bdb3dSTom St Denis #define mmDP0_DP_MSE_RATE_CNTL 0x1CE1 3140de2bdb3dSTom St Denis #define mmDP0_DP_MSE_RATE_UPDATE 0x1CE3 3141de2bdb3dSTom St Denis #define mmDP0_DP_MSE_SAT0 0x1CE4 3142de2bdb3dSTom St Denis #define mmDP0_DP_MSE_SAT1 0x1CE5 3143de2bdb3dSTom St Denis #define mmDP0_DP_MSE_SAT2 0x1CE6 3144de2bdb3dSTom St Denis #define mmDP0_DP_MSE_SAT_UPDATE 0x1CE7 3145de2bdb3dSTom St Denis #define mmDP0_DP_PIXEL_FORMAT 0x1CC1 3146de2bdb3dSTom St Denis #define mmDP0_DP_SEC_AUD_M 0x1CA7 3147de2bdb3dSTom St Denis #define mmDP0_DP_SEC_AUD_M_READBACK 0x1CA8 3148de2bdb3dSTom St Denis #define mmDP0_DP_SEC_AUD_N 0x1CA5 3149de2bdb3dSTom St Denis #define mmDP0_DP_SEC_AUD_N_READBACK 0x1CA6 3150de2bdb3dSTom St Denis #define mmDP0_DP_SEC_CNTL 0x1CA0 3151de2bdb3dSTom St Denis #define mmDP0_DP_SEC_CNTL1 0x1CAB 3152de2bdb3dSTom St Denis #define mmDP0_DP_SEC_FRAMING1 0x1CA1 3153de2bdb3dSTom St Denis #define mmDP0_DP_SEC_FRAMING2 0x1CA2 3154de2bdb3dSTom St Denis #define mmDP0_DP_SEC_FRAMING3 0x1CA3 3155de2bdb3dSTom St Denis #define mmDP0_DP_SEC_FRAMING4 0x1CA4 3156de2bdb3dSTom St Denis #define mmDP0_DP_SEC_PACKET_CNTL 0x1CAA 3157de2bdb3dSTom St Denis #define mmDP0_DP_SEC_TIMESTAMP 0x1CA9 3158de2bdb3dSTom St Denis #define mmDP0_DP_STEER_FIFO 0x1CC4 3159de2bdb3dSTom St Denis #define mmDP0_DP_TEST_DEBUG_DATA 0x1CFD 3160de2bdb3dSTom St Denis #define mmDP0_DP_TEST_DEBUG_INDEX 0x1CFC 3161de2bdb3dSTom St Denis #define mmDP0_DP_VID_INTERRUPT_CNTL 0x1CCF 3162de2bdb3dSTom St Denis #define mmDP0_DP_VID_M 0x1CCB 3163de2bdb3dSTom St Denis #define mmDP0_DP_VID_MSA_VBID 0x1CCD 3164de2bdb3dSTom St Denis #define mmDP0_DP_VID_N 0x1CCA 3165de2bdb3dSTom St Denis #define mmDP0_DP_VID_STREAM_CNTL 0x1CC3 3166de2bdb3dSTom St Denis #define mmDP0_DP_VID_TIMING 0x1CC9 3167de2bdb3dSTom St Denis #define mmDP1_DP_CONFIG 0x1FC2 3168de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_8B10B_CNTL 0x1FD3 3169de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_CNTL 0x1FD0 3170de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_CRC_CNTL 0x1FD7 3171de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_CRC_EN 0x1FD6 3172de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_CRC_MST_CNTL 0x1FC6 3173de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_CRC_MST_STATUS 0x1FC7 3174de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_CRC_RESULT 0x1FD8 3175de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE 3176de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x1FE9 3177de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_PRBS_CNTL 0x1FD4 3178de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_SYM0 0x1FD2 3179de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_SYM1 0x1FE0 3180de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_SYM2 0x1FDF 3181de2bdb3dSTom St Denis #define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x1FD1 3182de2bdb3dSTom St Denis #define mmDP1_DP_HBR2_EYE_PATTERN 0x1FC8 3183de2bdb3dSTom St Denis #define mmDP1_DP_LINK_CNTL 0x1FC0 3184de2bdb3dSTom St Denis #define mmDP1_DP_LINK_FRAMING_CNTL 0x1FCC 3185de2bdb3dSTom St Denis #define mmDP1_DP_MSA_COLORIMETRY 0x1FDA 3186de2bdb3dSTom St Denis #define mmDP1_DP_MSA_MISC 0x1FC5 3187de2bdb3dSTom St Denis #define mmDP1_DP_MSA_V_TIMING_OVERRIDE1 0x1FEA 3188de2bdb3dSTom St Denis #define mmDP1_DP_MSA_V_TIMING_OVERRIDE2 0x1FEB 3189de2bdb3dSTom St Denis #define mmDP1_DP_MSE_LINK_TIMING 0x1FE8 3190de2bdb3dSTom St Denis #define mmDP1_DP_MSE_MISC_CNTL 0x1FDB 3191de2bdb3dSTom St Denis #define mmDP1_DP_MSE_RATE_CNTL 0x1FE1 3192de2bdb3dSTom St Denis #define mmDP1_DP_MSE_RATE_UPDATE 0x1FE3 3193de2bdb3dSTom St Denis #define mmDP1_DP_MSE_SAT0 0x1FE4 3194de2bdb3dSTom St Denis #define mmDP1_DP_MSE_SAT1 0x1FE5 3195de2bdb3dSTom St Denis #define mmDP1_DP_MSE_SAT2 0x1FE6 3196de2bdb3dSTom St Denis #define mmDP1_DP_MSE_SAT_UPDATE 0x1FE7 3197de2bdb3dSTom St Denis #define mmDP1_DP_PIXEL_FORMAT 0x1FC1 3198de2bdb3dSTom St Denis #define mmDP1_DP_SEC_AUD_M 0x1FA7 3199de2bdb3dSTom St Denis #define mmDP1_DP_SEC_AUD_M_READBACK 0x1FA8 3200de2bdb3dSTom St Denis #define mmDP1_DP_SEC_AUD_N 0x1FA5 3201de2bdb3dSTom St Denis #define mmDP1_DP_SEC_AUD_N_READBACK 0x1FA6 3202de2bdb3dSTom St Denis #define mmDP1_DP_SEC_CNTL 0x1FA0 3203de2bdb3dSTom St Denis #define mmDP1_DP_SEC_CNTL1 0x1FAB 3204de2bdb3dSTom St Denis #define mmDP1_DP_SEC_FRAMING1 0x1FA1 3205de2bdb3dSTom St Denis #define mmDP1_DP_SEC_FRAMING2 0x1FA2 3206de2bdb3dSTom St Denis #define mmDP1_DP_SEC_FRAMING3 0x1FA3 3207de2bdb3dSTom St Denis #define mmDP1_DP_SEC_FRAMING4 0x1FA4 3208de2bdb3dSTom St Denis #define mmDP1_DP_SEC_PACKET_CNTL 0x1FAA 3209de2bdb3dSTom St Denis #define mmDP1_DP_SEC_TIMESTAMP 0x1FA9 3210de2bdb3dSTom St Denis #define mmDP1_DP_STEER_FIFO 0x1FC4 3211de2bdb3dSTom St Denis #define mmDP1_DP_TEST_DEBUG_DATA 0x1FFD 3212de2bdb3dSTom St Denis #define mmDP1_DP_TEST_DEBUG_INDEX 0x1FFC 3213de2bdb3dSTom St Denis #define mmDP1_DP_VID_INTERRUPT_CNTL 0x1FCF 3214de2bdb3dSTom St Denis #define mmDP1_DP_VID_M 0x1FCB 3215de2bdb3dSTom St Denis #define mmDP1_DP_VID_MSA_VBID 0x1FCD 3216de2bdb3dSTom St Denis #define mmDP1_DP_VID_N 0x1FCA 3217de2bdb3dSTom St Denis #define mmDP1_DP_VID_STREAM_CNTL 0x1FC3 3218de2bdb3dSTom St Denis #define mmDP1_DP_VID_TIMING 0x1FC9 3219de2bdb3dSTom St Denis #define mmDP2_DP_CONFIG 0x42C2 3220de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_8B10B_CNTL 0x42D3 3221de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_CNTL 0x42D0 3222de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_CRC_CNTL 0x42D7 3223de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_CRC_EN 0x42D6 3224de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_CRC_MST_CNTL 0x42C6 3225de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_CRC_MST_STATUS 0x42C7 3226de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_CRC_RESULT 0x42D8 3227de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE 3228de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x42E9 3229de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_PRBS_CNTL 0x42D4 3230de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_SYM0 0x42D2 3231de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_SYM1 0x42E0 3232de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_SYM2 0x42DF 3233de2bdb3dSTom St Denis #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1 3234de2bdb3dSTom St Denis #define mmDP2_DP_HBR2_EYE_PATTERN 0x42C8 3235de2bdb3dSTom St Denis #define mmDP2_DP_LINK_CNTL 0x42C0 3236de2bdb3dSTom St Denis #define mmDP2_DP_LINK_FRAMING_CNTL 0x42CC 3237de2bdb3dSTom St Denis #define mmDP2_DP_MSA_COLORIMETRY 0x42DA 3238de2bdb3dSTom St Denis #define mmDP2_DP_MSA_MISC 0x42C5 3239de2bdb3dSTom St Denis #define mmDP2_DP_MSA_V_TIMING_OVERRIDE1 0x42EA 3240de2bdb3dSTom St Denis #define mmDP2_DP_MSA_V_TIMING_OVERRIDE2 0x42EB 3241de2bdb3dSTom St Denis #define mmDP2_DP_MSE_LINK_TIMING 0x42E8 3242de2bdb3dSTom St Denis #define mmDP2_DP_MSE_MISC_CNTL 0x42DB 3243de2bdb3dSTom St Denis #define mmDP2_DP_MSE_RATE_CNTL 0x42E1 3244de2bdb3dSTom St Denis #define mmDP2_DP_MSE_RATE_UPDATE 0x42E3 3245de2bdb3dSTom St Denis #define mmDP2_DP_MSE_SAT0 0x42E4 3246de2bdb3dSTom St Denis #define mmDP2_DP_MSE_SAT1 0x42E5 3247de2bdb3dSTom St Denis #define mmDP2_DP_MSE_SAT2 0x42E6 3248de2bdb3dSTom St Denis #define mmDP2_DP_MSE_SAT_UPDATE 0x42E7 3249de2bdb3dSTom St Denis #define mmDP2_DP_PIXEL_FORMAT 0x42C1 3250de2bdb3dSTom St Denis #define mmDP2_DP_SEC_AUD_M 0x42A7 3251de2bdb3dSTom St Denis #define mmDP2_DP_SEC_AUD_M_READBACK 0x42A8 3252de2bdb3dSTom St Denis #define mmDP2_DP_SEC_AUD_N 0x42A5 3253de2bdb3dSTom St Denis #define mmDP2_DP_SEC_AUD_N_READBACK 0x42A6 3254de2bdb3dSTom St Denis #define mmDP2_DP_SEC_CNTL 0x42A0 3255de2bdb3dSTom St Denis #define mmDP2_DP_SEC_CNTL1 0x42AB 3256de2bdb3dSTom St Denis #define mmDP2_DP_SEC_FRAMING1 0x42A1 3257de2bdb3dSTom St Denis #define mmDP2_DP_SEC_FRAMING2 0x42A2 3258de2bdb3dSTom St Denis #define mmDP2_DP_SEC_FRAMING3 0x42A3 3259de2bdb3dSTom St Denis #define mmDP2_DP_SEC_FRAMING4 0x42A4 3260de2bdb3dSTom St Denis #define mmDP2_DP_SEC_PACKET_CNTL 0x42AA 3261de2bdb3dSTom St Denis #define mmDP2_DP_SEC_TIMESTAMP 0x42A9 3262de2bdb3dSTom St Denis #define mmDP2_DP_STEER_FIFO 0x42C4 3263de2bdb3dSTom St Denis #define mmDP2_DP_TEST_DEBUG_DATA 0x42FD 3264de2bdb3dSTom St Denis #define mmDP2_DP_TEST_DEBUG_INDEX 0x42FC 3265de2bdb3dSTom St Denis #define mmDP2_DP_VID_INTERRUPT_CNTL 0x42CF 3266de2bdb3dSTom St Denis #define mmDP2_DP_VID_M 0x42CB 3267de2bdb3dSTom St Denis #define mmDP2_DP_VID_MSA_VBID 0x42CD 3268de2bdb3dSTom St Denis #define mmDP2_DP_VID_N 0x42CA 3269de2bdb3dSTom St Denis #define mmDP2_DP_VID_STREAM_CNTL 0x42C3 3270de2bdb3dSTom St Denis #define mmDP2_DP_VID_TIMING 0x42C9 3271de2bdb3dSTom St Denis #define mmDP3_DP_CONFIG 0x45C2 3272de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3 3273de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_CNTL 0x45D0 3274de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_CRC_CNTL 0x45D7 3275de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_CRC_EN 0x45D6 3276de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_CRC_MST_CNTL 0x45C6 3277de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_CRC_MST_STATUS 0x45C7 3278de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_CRC_RESULT 0x45D8 3279de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE 3280de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x45E9 3281de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_PRBS_CNTL 0x45D4 3282de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_SYM0 0x45D2 3283de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_SYM1 0x45E0 3284de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_SYM2 0x45DF 3285de2bdb3dSTom St Denis #define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x45D1 3286de2bdb3dSTom St Denis #define mmDP3_DP_HBR2_EYE_PATTERN 0x45C8 3287de2bdb3dSTom St Denis #define mmDP3_DP_LINK_CNTL 0x45C0 3288de2bdb3dSTom St Denis #define mmDP3_DP_LINK_FRAMING_CNTL 0x45CC 3289de2bdb3dSTom St Denis #define mmDP3_DP_MSA_COLORIMETRY 0x45DA 3290de2bdb3dSTom St Denis #define mmDP3_DP_MSA_MISC 0x45C5 3291de2bdb3dSTom St Denis #define mmDP3_DP_MSA_V_TIMING_OVERRIDE1 0x45EA 3292de2bdb3dSTom St Denis #define mmDP3_DP_MSA_V_TIMING_OVERRIDE2 0x45EB 3293de2bdb3dSTom St Denis #define mmDP3_DP_MSE_LINK_TIMING 0x45E8 3294de2bdb3dSTom St Denis #define mmDP3_DP_MSE_MISC_CNTL 0x45DB 3295de2bdb3dSTom St Denis #define mmDP3_DP_MSE_RATE_CNTL 0x45E1 3296de2bdb3dSTom St Denis #define mmDP3_DP_MSE_RATE_UPDATE 0x45E3 3297de2bdb3dSTom St Denis #define mmDP3_DP_MSE_SAT0 0x45E4 3298de2bdb3dSTom St Denis #define mmDP3_DP_MSE_SAT1 0x45E5 3299de2bdb3dSTom St Denis #define mmDP3_DP_MSE_SAT2 0x45E6 3300de2bdb3dSTom St Denis #define mmDP3_DP_MSE_SAT_UPDATE 0x45E7 3301de2bdb3dSTom St Denis #define mmDP3_DP_PIXEL_FORMAT 0x45C1 3302de2bdb3dSTom St Denis #define mmDP3_DP_SEC_AUD_M 0x45A7 3303de2bdb3dSTom St Denis #define mmDP3_DP_SEC_AUD_M_READBACK 0x45A8 3304de2bdb3dSTom St Denis #define mmDP3_DP_SEC_AUD_N 0x45A5 3305de2bdb3dSTom St Denis #define mmDP3_DP_SEC_AUD_N_READBACK 0x45A6 3306de2bdb3dSTom St Denis #define mmDP3_DP_SEC_CNTL 0x45A0 3307de2bdb3dSTom St Denis #define mmDP3_DP_SEC_CNTL1 0x45AB 3308de2bdb3dSTom St Denis #define mmDP3_DP_SEC_FRAMING1 0x45A1 3309de2bdb3dSTom St Denis #define mmDP3_DP_SEC_FRAMING2 0x45A2 3310de2bdb3dSTom St Denis #define mmDP3_DP_SEC_FRAMING3 0x45A3 3311de2bdb3dSTom St Denis #define mmDP3_DP_SEC_FRAMING4 0x45A4 3312de2bdb3dSTom St Denis #define mmDP3_DP_SEC_PACKET_CNTL 0x45AA 3313de2bdb3dSTom St Denis #define mmDP3_DP_SEC_TIMESTAMP 0x45A9 3314de2bdb3dSTom St Denis #define mmDP3_DP_STEER_FIFO 0x45C4 3315de2bdb3dSTom St Denis #define mmDP3_DP_TEST_DEBUG_DATA 0x45FD 3316de2bdb3dSTom St Denis #define mmDP3_DP_TEST_DEBUG_INDEX 0x45FC 3317de2bdb3dSTom St Denis #define mmDP3_DP_VID_INTERRUPT_CNTL 0x45CF 3318de2bdb3dSTom St Denis #define mmDP3_DP_VID_M 0x45CB 3319de2bdb3dSTom St Denis #define mmDP3_DP_VID_MSA_VBID 0x45CD 3320de2bdb3dSTom St Denis #define mmDP3_DP_VID_N 0x45CA 3321de2bdb3dSTom St Denis #define mmDP3_DP_VID_STREAM_CNTL 0x45C3 3322de2bdb3dSTom St Denis #define mmDP3_DP_VID_TIMING 0x45C9 3323de2bdb3dSTom St Denis #define mmDP4_DP_CONFIG 0x48C2 3324de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_8B10B_CNTL 0x48D3 3325de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_CNTL 0x48D0 3326de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_CRC_CNTL 0x48D7 3327de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_CRC_EN 0x48D6 3328de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_CRC_MST_CNTL 0x48C6 3329de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_CRC_MST_STATUS 0x48C7 3330de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_CRC_RESULT 0x48D8 3331de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE 3332de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x48E9 3333de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_PRBS_CNTL 0x48D4 3334de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_SYM0 0x48D2 3335de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_SYM1 0x48E0 3336de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_SYM2 0x48DF 3337de2bdb3dSTom St Denis #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1 3338de2bdb3dSTom St Denis #define mmDP4_DP_HBR2_EYE_PATTERN 0x48C8 3339de2bdb3dSTom St Denis #define mmDP4_DP_LINK_CNTL 0x48C0 3340de2bdb3dSTom St Denis #define mmDP4_DP_LINK_FRAMING_CNTL 0x48CC 3341de2bdb3dSTom St Denis #define mmDP4_DP_MSA_COLORIMETRY 0x48DA 3342de2bdb3dSTom St Denis #define mmDP4_DP_MSA_MISC 0x48C5 3343de2bdb3dSTom St Denis #define mmDP4_DP_MSA_V_TIMING_OVERRIDE1 0x48EA 3344de2bdb3dSTom St Denis #define mmDP4_DP_MSA_V_TIMING_OVERRIDE2 0x48EB 3345de2bdb3dSTom St Denis #define mmDP4_DP_MSE_LINK_TIMING 0x48E8 3346de2bdb3dSTom St Denis #define mmDP4_DP_MSE_MISC_CNTL 0x48DB 3347de2bdb3dSTom St Denis #define mmDP4_DP_MSE_RATE_CNTL 0x48E1 3348de2bdb3dSTom St Denis #define mmDP4_DP_MSE_RATE_UPDATE 0x48E3 3349de2bdb3dSTom St Denis #define mmDP4_DP_MSE_SAT0 0x48E4 3350de2bdb3dSTom St Denis #define mmDP4_DP_MSE_SAT1 0x48E5 3351de2bdb3dSTom St Denis #define mmDP4_DP_MSE_SAT2 0x48E6 3352de2bdb3dSTom St Denis #define mmDP4_DP_MSE_SAT_UPDATE 0x48E7 3353de2bdb3dSTom St Denis #define mmDP4_DP_PIXEL_FORMAT 0x48C1 3354de2bdb3dSTom St Denis #define mmDP4_DP_SEC_AUD_M 0x48A7 3355de2bdb3dSTom St Denis #define mmDP4_DP_SEC_AUD_M_READBACK 0x48A8 3356de2bdb3dSTom St Denis #define mmDP4_DP_SEC_AUD_N 0x48A5 3357de2bdb3dSTom St Denis #define mmDP4_DP_SEC_AUD_N_READBACK 0x48A6 3358de2bdb3dSTom St Denis #define mmDP4_DP_SEC_CNTL 0x48A0 3359de2bdb3dSTom St Denis #define mmDP4_DP_SEC_CNTL1 0x48AB 3360de2bdb3dSTom St Denis #define mmDP4_DP_SEC_FRAMING1 0x48A1 3361de2bdb3dSTom St Denis #define mmDP4_DP_SEC_FRAMING2 0x48A2 3362de2bdb3dSTom St Denis #define mmDP4_DP_SEC_FRAMING3 0x48A3 3363de2bdb3dSTom St Denis #define mmDP4_DP_SEC_FRAMING4 0x48A4 3364de2bdb3dSTom St Denis #define mmDP4_DP_SEC_PACKET_CNTL 0x48AA 3365de2bdb3dSTom St Denis #define mmDP4_DP_SEC_TIMESTAMP 0x48A9 3366de2bdb3dSTom St Denis #define mmDP4_DP_STEER_FIFO 0x48C4 3367de2bdb3dSTom St Denis #define mmDP4_DP_TEST_DEBUG_DATA 0x48FD 3368de2bdb3dSTom St Denis #define mmDP4_DP_TEST_DEBUG_INDEX 0x48FC 3369de2bdb3dSTom St Denis #define mmDP4_DP_VID_INTERRUPT_CNTL 0x48CF 3370de2bdb3dSTom St Denis #define mmDP4_DP_VID_M 0x48CB 3371de2bdb3dSTom St Denis #define mmDP4_DP_VID_MSA_VBID 0x48CD 3372de2bdb3dSTom St Denis #define mmDP4_DP_VID_N 0x48CA 3373de2bdb3dSTom St Denis #define mmDP4_DP_VID_STREAM_CNTL 0x48C3 3374de2bdb3dSTom St Denis #define mmDP4_DP_VID_TIMING 0x48C9 3375de2bdb3dSTom St Denis #define mmDP5_DP_CONFIG 0x4BC2 3376de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_8B10B_CNTL 0x4BD3 3377de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_CNTL 0x4BD0 3378de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_CRC_CNTL 0x4BD7 3379de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_CRC_EN 0x4BD6 3380de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_CRC_MST_CNTL 0x4BC6 3381de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_CRC_MST_STATUS 0x4BC7 3382de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_CRC_RESULT 0x4BD8 3383de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE 3384de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x4BE9 3385de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_PRBS_CNTL 0x4BD4 3386de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_SYM0 0x4BD2 3387de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_SYM1 0x4BE0 3388de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_SYM2 0x4BDF 3389de2bdb3dSTom St Denis #define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x4BD1 3390de2bdb3dSTom St Denis #define mmDP5_DP_HBR2_EYE_PATTERN 0x4BC8 3391de2bdb3dSTom St Denis #define mmDP5_DP_LINK_CNTL 0x4BC0 3392de2bdb3dSTom St Denis #define mmDP5_DP_LINK_FRAMING_CNTL 0x4BCC 3393de2bdb3dSTom St Denis #define mmDP5_DP_MSA_COLORIMETRY 0x4BDA 3394de2bdb3dSTom St Denis #define mmDP5_DP_MSA_MISC 0x4BC5 3395de2bdb3dSTom St Denis #define mmDP5_DP_MSA_V_TIMING_OVERRIDE1 0x4BEA 3396de2bdb3dSTom St Denis #define mmDP5_DP_MSA_V_TIMING_OVERRIDE2 0x4BEB 3397de2bdb3dSTom St Denis #define mmDP5_DP_MSE_LINK_TIMING 0x4BE8 3398de2bdb3dSTom St Denis #define mmDP5_DP_MSE_MISC_CNTL 0x4BDB 3399de2bdb3dSTom St Denis #define mmDP5_DP_MSE_RATE_CNTL 0x4BE1 3400de2bdb3dSTom St Denis #define mmDP5_DP_MSE_RATE_UPDATE 0x4BE3 3401de2bdb3dSTom St Denis #define mmDP5_DP_MSE_SAT0 0x4BE4 3402de2bdb3dSTom St Denis #define mmDP5_DP_MSE_SAT1 0x4BE5 3403de2bdb3dSTom St Denis #define mmDP5_DP_MSE_SAT2 0x4BE6 3404de2bdb3dSTom St Denis #define mmDP5_DP_MSE_SAT_UPDATE 0x4BE7 3405de2bdb3dSTom St Denis #define mmDP5_DP_PIXEL_FORMAT 0x4BC1 3406de2bdb3dSTom St Denis #define mmDP5_DP_SEC_AUD_M 0x4BA7 3407de2bdb3dSTom St Denis #define mmDP5_DP_SEC_AUD_M_READBACK 0x4BA8 3408de2bdb3dSTom St Denis #define mmDP5_DP_SEC_AUD_N 0x4BA5 3409de2bdb3dSTom St Denis #define mmDP5_DP_SEC_AUD_N_READBACK 0x4BA6 3410de2bdb3dSTom St Denis #define mmDP5_DP_SEC_CNTL 0x4BA0 3411de2bdb3dSTom St Denis #define mmDP5_DP_SEC_CNTL1 0x4BAB 3412de2bdb3dSTom St Denis #define mmDP5_DP_SEC_FRAMING1 0x4BA1 3413de2bdb3dSTom St Denis #define mmDP5_DP_SEC_FRAMING2 0x4BA2 3414de2bdb3dSTom St Denis #define mmDP5_DP_SEC_FRAMING3 0x4BA3 3415de2bdb3dSTom St Denis #define mmDP5_DP_SEC_FRAMING4 0x4BA4 3416de2bdb3dSTom St Denis #define mmDP5_DP_SEC_PACKET_CNTL 0x4BAA 3417de2bdb3dSTom St Denis #define mmDP5_DP_SEC_TIMESTAMP 0x4BA9 3418de2bdb3dSTom St Denis #define mmDP5_DP_STEER_FIFO 0x4BC4 3419de2bdb3dSTom St Denis #define mmDP5_DP_TEST_DEBUG_DATA 0x4BFD 3420de2bdb3dSTom St Denis #define mmDP5_DP_TEST_DEBUG_INDEX 0x4BFC 3421de2bdb3dSTom St Denis #define mmDP5_DP_VID_INTERRUPT_CNTL 0x4BCF 3422de2bdb3dSTom St Denis #define mmDP5_DP_VID_M 0x4BCB 3423de2bdb3dSTom St Denis #define mmDP5_DP_VID_MSA_VBID 0x4BCD 3424de2bdb3dSTom St Denis #define mmDP5_DP_VID_N 0x4BCA 3425de2bdb3dSTom St Denis #define mmDP5_DP_VID_STREAM_CNTL 0x4BC3 3426de2bdb3dSTom St Denis #define mmDP5_DP_VID_TIMING 0x4BC9 3427de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_ARB_CONTROL 0x1882 3428de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_CONTROL 0x1880 3429de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x188A 3430de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x188B 3431de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x188D 3432de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1889 3433de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1888 3434de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x188C 3435de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_GTC_SYNC_CONTROL 0x188E 3436de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_GTC_SYNC_DATA 0x1890 3437de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1883 3438de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_LS_DATA 0x1887 3439de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_LS_STATUS 0x1885 3440de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_SW_CONTROL 0x1881 3441de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_SW_DATA 0x1886 3442de2bdb3dSTom St Denis #define mmDP_AUX0_AUX_SW_STATUS 0x1884 3443de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_ARB_CONTROL 0x1896 3444de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_CONTROL 0x1894 3445de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x189E 3446de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x189F 3447de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x18A1 3448de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x189D 3449de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x189C 3450de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x18A0 3451de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_GTC_SYNC_CONTROL 0x18A2 3452de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_GTC_SYNC_DATA 0x18A4 3453de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1897 3454de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_LS_DATA 0x189B 3455de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_LS_STATUS 0x1899 3456de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_SW_CONTROL 0x1895 3457de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_SW_DATA 0x189A 3458de2bdb3dSTom St Denis #define mmDP_AUX1_AUX_SW_STATUS 0x1898 3459de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_ARB_CONTROL 0x18AA 3460de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_CONTROL 0x18A8 3461de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x18B2 3462de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x18B3 3463de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x18B5 3464de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x18B1 3465de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x18B0 3466de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x18B4 3467de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_GTC_SYNC_CONTROL 0x18B6 3468de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_GTC_SYNC_DATA 0x18B8 3469de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x18AB 3470de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_LS_DATA 0x18AF 3471de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_LS_STATUS 0x18AD 3472de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_SW_CONTROL 0x18A9 3473de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_SW_DATA 0x18AE 3474de2bdb3dSTom St Denis #define mmDP_AUX2_AUX_SW_STATUS 0x18AC 3475de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_ARB_CONTROL 0x18C2 3476de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_CONTROL 0x18C0 3477de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x18CA 3478de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x18CB 3479de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x18CD 3480de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x18C9 3481de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x18C8 3482de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x18CC 3483de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_GTC_SYNC_CONTROL 0x18CE 3484de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_GTC_SYNC_DATA 0x18D0 3485de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x18C3 3486de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_LS_DATA 0x18C7 3487de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_LS_STATUS 0x18C5 3488de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_SW_CONTROL 0x18C1 3489de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_SW_DATA 0x18C6 3490de2bdb3dSTom St Denis #define mmDP_AUX3_AUX_SW_STATUS 0x18C4 3491de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_ARB_CONTROL 0x18D6 3492de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_CONTROL 0x18D4 3493de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x18DE 3494de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x18DF 3495de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x18E1 3496de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x18DD 3497de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x18DC 3498de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x18E0 3499de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_GTC_SYNC_CONTROL 0x18E2 3500de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_GTC_SYNC_DATA 0x18E4 3501de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x18D7 3502de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_LS_DATA 0x18DB 3503de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_LS_STATUS 0x18D9 3504de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_SW_CONTROL 0x18D5 3505de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_SW_DATA 0x18DA 3506de2bdb3dSTom St Denis #define mmDP_AUX4_AUX_SW_STATUS 0x18D8 3507de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_ARB_CONTROL 0x18EA 3508de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_CONTROL 0x18E8 3509de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x18F2 3510de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x18F3 3511de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x18F5 3512de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x18F1 3513de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x18F0 3514de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x18F4 3515de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_GTC_SYNC_CONTROL 0x18F6 3516de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_GTC_SYNC_DATA 0x18F8 3517de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x18EB 3518de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_LS_DATA 0x18EF 3519de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_LS_STATUS 0x18ED 3520de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_SW_CONTROL 0x18E9 3521de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_SW_DATA 0x18EE 3522de2bdb3dSTom St Denis #define mmDP_AUX5_AUX_SW_STATUS 0x18EC 3523de2bdb3dSTom St Denis #define mmDP_CONFIG 0x1CC2 3524de2bdb3dSTom St Denis #define mmDP_DPHY_8B10B_CNTL 0x1CD3 3525de2bdb3dSTom St Denis #define mmDP_DPHY_CNTL 0x1CD0 3526de2bdb3dSTom St Denis #define mmDP_DPHY_CRC_CNTL 0x1CD7 3527de2bdb3dSTom St Denis #define mmDP_DPHY_CRC_EN 0x1CD6 3528de2bdb3dSTom St Denis #define mmDP_DPHY_CRC_MST_CNTL 0x1CC6 3529de2bdb3dSTom St Denis #define mmDP_DPHY_CRC_MST_STATUS 0x1CC7 3530de2bdb3dSTom St Denis #define mmDP_DPHY_CRC_RESULT 0x1CD8 3531de2bdb3dSTom St Denis #define mmDP_DPHY_FAST_TRAINING 0x1CCE 3532de2bdb3dSTom St Denis #define mmDP_DPHY_FAST_TRAINING_STATUS 0x1CE9 3533de2bdb3dSTom St Denis #define mmDP_DPHY_PRBS_CNTL 0x1CD4 3534de2bdb3dSTom St Denis #define mmDP_DPHY_SYM0 0x1CD2 3535de2bdb3dSTom St Denis #define mmDP_DPHY_SYM1 0x1CE0 3536de2bdb3dSTom St Denis #define mmDP_DPHY_SYM2 0x1CDF 3537de2bdb3dSTom St Denis #define mmDP_DPHY_TRAINING_PATTERN_SEL 0x1CD1 3538de2bdb3dSTom St Denis #define mmDP_DTO0_MODULO 0x0142 3539de2bdb3dSTom St Denis #define mmDP_DTO0_PHASE 0x0141 3540de2bdb3dSTom St Denis #define mmDP_DTO1_MODULO 0x0146 3541de2bdb3dSTom St Denis #define mmDP_DTO1_PHASE 0x0145 3542de2bdb3dSTom St Denis #define mmDP_DTO2_MODULO 0x014A 3543de2bdb3dSTom St Denis #define mmDP_DTO2_PHASE 0x0149 3544de2bdb3dSTom St Denis #define mmDP_DTO3_MODULO 0x014E 3545de2bdb3dSTom St Denis #define mmDP_DTO3_PHASE 0x014D 3546de2bdb3dSTom St Denis #define mmDP_DTO4_MODULO 0x0152 3547de2bdb3dSTom St Denis #define mmDP_DTO4_PHASE 0x0151 3548de2bdb3dSTom St Denis #define mmDP_DTO5_MODULO 0x0156 3549de2bdb3dSTom St Denis #define mmDP_DTO5_PHASE 0x0155 3550de2bdb3dSTom St Denis #define mmDPG_PIPE_ARBITRATION_CONTROL1 0x1B30 3551de2bdb3dSTom St Denis #define mmDPG_PIPE_ARBITRATION_CONTROL2 0x1B31 3552de2bdb3dSTom St Denis #define mmDPG_PIPE_DPM_CONTROL 0x1B34 3553de2bdb3dSTom St Denis #define mmDPG_PIPE_NB_PSTATE_CHANGE_CONTROL 0x1B36 3554de2bdb3dSTom St Denis #define mmDPG_PIPE_STUTTER_CONTROL 0x1B35 3555de2bdb3dSTom St Denis #define mmDPG_PIPE_STUTTER_CONTROL_NONLPTCH 0x1B37 3556de2bdb3dSTom St Denis #define mmDPG_PIPE_URGENCY_CONTROL 0x1B33 3557de2bdb3dSTom St Denis #define mmDPG_TEST_DEBUG_DATA 0x1B39 3558de2bdb3dSTom St Denis #define mmDPG_TEST_DEBUG_INDEX 0x1B38 3559de2bdb3dSTom St Denis #define mmDP_HBR2_EYE_PATTERN 0x1CC8 3560de2bdb3dSTom St Denis #define mmDP_LINK_CNTL 0x1CC0 3561de2bdb3dSTom St Denis #define mmDP_LINK_FRAMING_CNTL 0x1CCC 3562de2bdb3dSTom St Denis #define mmDP_MSA_COLORIMETRY 0x1CDA 3563de2bdb3dSTom St Denis #define mmDP_MSA_MISC 0x1CC5 3564de2bdb3dSTom St Denis #define mmDP_MSA_V_TIMING_OVERRIDE1 0x1CEA 3565de2bdb3dSTom St Denis #define mmDP_MSA_V_TIMING_OVERRIDE2 0x1CEB 3566de2bdb3dSTom St Denis #define mmDP_MSE_LINK_TIMING 0x1CE8 3567de2bdb3dSTom St Denis #define mmDP_MSE_MISC_CNTL 0x1CDB 3568de2bdb3dSTom St Denis #define mmDP_MSE_RATE_CNTL 0x1CE1 3569de2bdb3dSTom St Denis #define mmDP_MSE_RATE_UPDATE 0x1CE3 3570de2bdb3dSTom St Denis #define mmDP_MSE_SAT0 0x1CE4 3571de2bdb3dSTom St Denis #define mmDP_MSE_SAT1 0x1CE5 3572de2bdb3dSTom St Denis #define mmDP_MSE_SAT2 0x1CE6 3573de2bdb3dSTom St Denis #define mmDP_MSE_SAT_UPDATE 0x1CE7 3574de2bdb3dSTom St Denis #define mmDP_PIXEL_FORMAT 0x1CC1 3575de2bdb3dSTom St Denis #define mmDP_SEC_AUD_M 0x1CA7 3576de2bdb3dSTom St Denis #define mmDP_SEC_AUD_M_READBACK 0x1CA8 3577de2bdb3dSTom St Denis #define mmDP_SEC_AUD_N 0x1CA5 3578de2bdb3dSTom St Denis #define mmDP_SEC_AUD_N_READBACK 0x1CA6 3579de2bdb3dSTom St Denis #define mmDP_SEC_CNTL 0x1CA0 3580de2bdb3dSTom St Denis #define mmDP_SEC_CNTL1 0x1CAB 3581de2bdb3dSTom St Denis #define mmDP_SEC_FRAMING1 0x1CA1 3582de2bdb3dSTom St Denis #define mmDP_SEC_FRAMING2 0x1CA2 3583de2bdb3dSTom St Denis #define mmDP_SEC_FRAMING3 0x1CA3 3584de2bdb3dSTom St Denis #define mmDP_SEC_FRAMING4 0x1CA4 3585de2bdb3dSTom St Denis #define mmDP_SEC_PACKET_CNTL 0x1CAA 3586de2bdb3dSTom St Denis #define mmDP_SEC_TIMESTAMP 0x1CA9 3587de2bdb3dSTom St Denis #define mmDP_STEER_FIFO 0x1CC4 3588de2bdb3dSTom St Denis #define mmDP_TEST_DEBUG_DATA 0x1CFD 3589de2bdb3dSTom St Denis #define mmDP_TEST_DEBUG_INDEX 0x1CFC 3590de2bdb3dSTom St Denis #define mmDP_VID_INTERRUPT_CNTL 0x1CCF 3591de2bdb3dSTom St Denis #define mmDP_VID_M 0x1CCB 3592de2bdb3dSTom St Denis #define mmDP_VID_MSA_VBID 0x1CCD 3593de2bdb3dSTom St Denis #define mmDP_VID_N 0x1CCA 3594de2bdb3dSTom St Denis #define mmDP_VID_STREAM_CNTL 0x1CC3 3595de2bdb3dSTom St Denis #define mmDP_VID_TIMING 0x1CC9 3596de2bdb3dSTom St Denis #define mmDVOACLKC_CNTL 0x016A 3597de2bdb3dSTom St Denis #define mmDVOACLKC_MVP_CNTL 0x0169 3598de2bdb3dSTom St Denis #define mmDVOACLKD_CNTL 0x0168 3599de2bdb3dSTom St Denis #define mmDVO_CLK_ENABLE 0x0129 3600de2bdb3dSTom St Denis #define mmDVO_CONTROL 0x185B 3601de2bdb3dSTom St Denis #define mmDVO_CRC2_SIG_MASK 0x185D 3602de2bdb3dSTom St Denis #define mmDVO_CRC2_SIG_RESULT 0x185E 3603de2bdb3dSTom St Denis #define mmDVO_CRC_EN 0x185C 3604de2bdb3dSTom St Denis #define mmDVO_ENABLE 0x1858 3605de2bdb3dSTom St Denis #define mmDVO_FIFO_ERROR_STATUS 0x185F 3606de2bdb3dSTom St Denis #define mmDVO_OUTPUT 0x185A 3607de2bdb3dSTom St Denis #define mmDVO_SKEW_ADJUST 0x197D 3608de2bdb3dSTom St Denis #define mmDVO_SOURCE_SELECT 0x1859 3609de2bdb3dSTom St Denis #define mmDVO_STRENGTH_CONTROL 0x197B 3610de2bdb3dSTom St Denis #define mmDVO_VREF_CONTROL 0x197C 3611de2bdb3dSTom St Denis #define mmEXT_OVERSCAN_LEFT_RIGHT 0x1B5E 3612de2bdb3dSTom St Denis #define mmEXT_OVERSCAN_TOP_BOTTOM 0x1B5F 3613de2bdb3dSTom St Denis #define mmFBC_CLIENT_REGION_MASK 0x16EB 3614de2bdb3dSTom St Denis #define mmFBC_CNTL 0x16D0 3615de2bdb3dSTom St Denis #define mmFBC_COMP_CNTL 0x16D4 3616de2bdb3dSTom St Denis #define mmFBC_COMP_MODE 0x16D5 3617de2bdb3dSTom St Denis #define mmFBC_CSM_REGION_OFFSET_01 0x16E9 3618de2bdb3dSTom St Denis #define mmFBC_CSM_REGION_OFFSET_23 0x16EA 3619de2bdb3dSTom St Denis #define mmFBC_DEBUG0 0x16D6 3620de2bdb3dSTom St Denis #define mmFBC_DEBUG1 0x16D7 3621de2bdb3dSTom St Denis #define mmFBC_DEBUG2 0x16D8 3622de2bdb3dSTom St Denis #define mmFBC_DEBUG_COMP 0x16EC 3623de2bdb3dSTom St Denis #define mmFBC_DEBUG_CSR 0x16ED 3624de2bdb3dSTom St Denis #define mmFBC_DEBUG_CSR_RDATA 0x16EE 3625de2bdb3dSTom St Denis #define mmFBC_DEBUG_CSR_RDATA_HI 0x16F6 3626de2bdb3dSTom St Denis #define mmFBC_DEBUG_CSR_WDATA 0x16EF 3627de2bdb3dSTom St Denis #define mmFBC_DEBUG_CSR_WDATA_HI 0x16F7 3628de2bdb3dSTom St Denis #define mmFBC_IDLE_FORCE_CLEAR_MASK 0x16D2 3629de2bdb3dSTom St Denis #define mmFBC_IDLE_MASK 0x16D1 3630de2bdb3dSTom St Denis #define mmFBC_IND_LUT0 0x16D9 3631de2bdb3dSTom St Denis #define mmFBC_IND_LUT10 0x16E3 3632de2bdb3dSTom St Denis #define mmFBC_IND_LUT1 0x16DA 3633de2bdb3dSTom St Denis #define mmFBC_IND_LUT11 0x16E4 3634de2bdb3dSTom St Denis #define mmFBC_IND_LUT12 0x16E5 3635de2bdb3dSTom St Denis #define mmFBC_IND_LUT13 0x16E6 3636de2bdb3dSTom St Denis #define mmFBC_IND_LUT14 0x16E7 3637de2bdb3dSTom St Denis #define mmFBC_IND_LUT15 0x16E8 3638de2bdb3dSTom St Denis #define mmFBC_IND_LUT2 0x16DB 3639de2bdb3dSTom St Denis #define mmFBC_IND_LUT3 0x16DC 3640de2bdb3dSTom St Denis #define mmFBC_IND_LUT4 0x16DD 3641de2bdb3dSTom St Denis #define mmFBC_IND_LUT5 0x16DE 3642de2bdb3dSTom St Denis #define mmFBC_IND_LUT6 0x16DF 3643de2bdb3dSTom St Denis #define mmFBC_IND_LUT7 0x16E0 3644de2bdb3dSTom St Denis #define mmFBC_IND_LUT8 0x16E1 3645de2bdb3dSTom St Denis #define mmFBC_IND_LUT9 0x16E2 3646de2bdb3dSTom St Denis #define mmFBC_MISC 0x16F0 3647de2bdb3dSTom St Denis #define mmFBC_START_STOP_DELAY 0x16D3 3648de2bdb3dSTom St Denis #define mmFBC_STATUS 0x16F1 3649de2bdb3dSTom St Denis #define mmFBC_TEST_DEBUG_DATA 0x16F5 3650de2bdb3dSTom St Denis #define mmFBC_TEST_DEBUG_INDEX 0x16F4 3651de2bdb3dSTom St Denis #define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1BF2 3652de2bdb3dSTom St Denis #define mmFMT0_FMT_CLAMP_CNTL 0x1BF9 3653de2bdb3dSTom St Denis #define mmFMT0_FMT_CONTROL 0x1BEE 3654de2bdb3dSTom St Denis #define mmFMT0_FMT_CRC_CNTL 0x1BFA 3655de2bdb3dSTom St Denis #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL 0x1BFE 3656de2bdb3dSTom St Denis #define mmFMT0_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC 3657de2bdb3dSTom St Denis #define mmFMT0_FMT_CRC_SIG_RED_GREEN 0x1BFD 3658de2bdb3dSTom St Denis #define mmFMT0_FMT_CRC_SIG_RED_GREEN_MASK 0x1BFB 3659de2bdb3dSTom St Denis #define mmFMT0_FMT_DEBUG_CNTL 0x1BFF 3660de2bdb3dSTom St Denis #define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1BF5 3661de2bdb3dSTom St Denis #define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1BF4 3662de2bdb3dSTom St Denis #define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1BF3 3663de2bdb3dSTom St Denis #define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x1BED 3664de2bdb3dSTom St Denis #define mmFMT0_FMT_FORCE_DATA_0_1 0x1BF0 3665de2bdb3dSTom St Denis #define mmFMT0_FMT_FORCE_DATA_2_3 0x1BF1 3666de2bdb3dSTom St Denis #define mmFMT0_FMT_FORCE_OUTPUT_CNTL 0x1BEF 3667de2bdb3dSTom St Denis #define mmFMT0_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 3668de2bdb3dSTom St Denis #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 3669de2bdb3dSTom St Denis #define mmFMT0_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 3670de2bdb3dSTom St Denis #define mmFMT0_FMT_TEST_DEBUG_DATA 0x1BEC 3671de2bdb3dSTom St Denis #define mmFMT0_FMT_TEST_DEBUG_INDEX 0x1BEB 3672de2bdb3dSTom St Denis #define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x1EF2 3673de2bdb3dSTom St Denis #define mmFMT1_FMT_CLAMP_CNTL 0x1EF9 3674de2bdb3dSTom St Denis #define mmFMT1_FMT_CONTROL 0x1EEE 3675de2bdb3dSTom St Denis #define mmFMT1_FMT_CRC_CNTL 0x1EFA 3676de2bdb3dSTom St Denis #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL 0x1EFE 3677de2bdb3dSTom St Denis #define mmFMT1_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x1EFC 3678de2bdb3dSTom St Denis #define mmFMT1_FMT_CRC_SIG_RED_GREEN 0x1EFD 3679de2bdb3dSTom St Denis #define mmFMT1_FMT_CRC_SIG_RED_GREEN_MASK 0x1EFB 3680de2bdb3dSTom St Denis #define mmFMT1_FMT_DEBUG_CNTL 0x1EFF 3681de2bdb3dSTom St Denis #define mmFMT1_FMT_DITHER_RAND_B_SEED 0x1EF5 3682de2bdb3dSTom St Denis #define mmFMT1_FMT_DITHER_RAND_G_SEED 0x1EF4 3683de2bdb3dSTom St Denis #define mmFMT1_FMT_DITHER_RAND_R_SEED 0x1EF3 3684de2bdb3dSTom St Denis #define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1EED 3685de2bdb3dSTom St Denis #define mmFMT1_FMT_FORCE_DATA_0_1 0x1EF0 3686de2bdb3dSTom St Denis #define mmFMT1_FMT_FORCE_DATA_2_3 0x1EF1 3687de2bdb3dSTom St Denis #define mmFMT1_FMT_FORCE_OUTPUT_CNTL 0x1EEF 3688de2bdb3dSTom St Denis #define mmFMT1_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1EF6 3689de2bdb3dSTom St Denis #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1EF7 3690de2bdb3dSTom St Denis #define mmFMT1_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1EF8 3691de2bdb3dSTom St Denis #define mmFMT1_FMT_TEST_DEBUG_DATA 0x1EEC 3692de2bdb3dSTom St Denis #define mmFMT1_FMT_TEST_DEBUG_INDEX 0x1EEB 3693de2bdb3dSTom St Denis #define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x41F2 3694de2bdb3dSTom St Denis #define mmFMT2_FMT_CLAMP_CNTL 0x41F9 3695de2bdb3dSTom St Denis #define mmFMT2_FMT_CONTROL 0x41EE 3696de2bdb3dSTom St Denis #define mmFMT2_FMT_CRC_CNTL 0x41FA 3697de2bdb3dSTom St Denis #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL 0x41FE 3698de2bdb3dSTom St Denis #define mmFMT2_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x41FC 3699de2bdb3dSTom St Denis #define mmFMT2_FMT_CRC_SIG_RED_GREEN 0x41FD 3700de2bdb3dSTom St Denis #define mmFMT2_FMT_CRC_SIG_RED_GREEN_MASK 0x41FB 3701de2bdb3dSTom St Denis #define mmFMT2_FMT_DEBUG_CNTL 0x41FF 3702de2bdb3dSTom St Denis #define mmFMT2_FMT_DITHER_RAND_B_SEED 0x41F5 3703de2bdb3dSTom St Denis #define mmFMT2_FMT_DITHER_RAND_G_SEED 0x41F4 3704de2bdb3dSTom St Denis #define mmFMT2_FMT_DITHER_RAND_R_SEED 0x41F3 3705de2bdb3dSTom St Denis #define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x41ED 3706de2bdb3dSTom St Denis #define mmFMT2_FMT_FORCE_DATA_0_1 0x41F0 3707de2bdb3dSTom St Denis #define mmFMT2_FMT_FORCE_DATA_2_3 0x41F1 3708de2bdb3dSTom St Denis #define mmFMT2_FMT_FORCE_OUTPUT_CNTL 0x41EF 3709de2bdb3dSTom St Denis #define mmFMT2_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x41F6 3710de2bdb3dSTom St Denis #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x41F7 3711de2bdb3dSTom St Denis #define mmFMT2_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x41F8 3712de2bdb3dSTom St Denis #define mmFMT2_FMT_TEST_DEBUG_DATA 0x41EC 3713de2bdb3dSTom St Denis #define mmFMT2_FMT_TEST_DEBUG_INDEX 0x41EB 3714de2bdb3dSTom St Denis #define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x44F2 3715de2bdb3dSTom St Denis #define mmFMT3_FMT_CLAMP_CNTL 0x44F9 3716de2bdb3dSTom St Denis #define mmFMT3_FMT_CONTROL 0x44EE 3717de2bdb3dSTom St Denis #define mmFMT3_FMT_CRC_CNTL 0x44FA 3718de2bdb3dSTom St Denis #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL 0x44FE 3719de2bdb3dSTom St Denis #define mmFMT3_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x44FC 3720de2bdb3dSTom St Denis #define mmFMT3_FMT_CRC_SIG_RED_GREEN 0x44FD 3721de2bdb3dSTom St Denis #define mmFMT3_FMT_CRC_SIG_RED_GREEN_MASK 0x44FB 3722de2bdb3dSTom St Denis #define mmFMT3_FMT_DEBUG_CNTL 0x44FF 3723de2bdb3dSTom St Denis #define mmFMT3_FMT_DITHER_RAND_B_SEED 0x44F5 3724de2bdb3dSTom St Denis #define mmFMT3_FMT_DITHER_RAND_G_SEED 0x44F4 3725de2bdb3dSTom St Denis #define mmFMT3_FMT_DITHER_RAND_R_SEED 0x44F3 3726de2bdb3dSTom St Denis #define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x44ED 3727de2bdb3dSTom St Denis #define mmFMT3_FMT_FORCE_DATA_0_1 0x44F0 3728de2bdb3dSTom St Denis #define mmFMT3_FMT_FORCE_DATA_2_3 0x44F1 3729de2bdb3dSTom St Denis #define mmFMT3_FMT_FORCE_OUTPUT_CNTL 0x44EF 3730de2bdb3dSTom St Denis #define mmFMT3_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x44F6 3731de2bdb3dSTom St Denis #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x44F7 3732de2bdb3dSTom St Denis #define mmFMT3_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x44F8 3733de2bdb3dSTom St Denis #define mmFMT3_FMT_TEST_DEBUG_DATA 0x44EC 3734de2bdb3dSTom St Denis #define mmFMT3_FMT_TEST_DEBUG_INDEX 0x44EB 3735de2bdb3dSTom St Denis #define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x47F2 3736de2bdb3dSTom St Denis #define mmFMT4_FMT_CLAMP_CNTL 0x47F9 3737de2bdb3dSTom St Denis #define mmFMT4_FMT_CONTROL 0x47EE 3738de2bdb3dSTom St Denis #define mmFMT4_FMT_CRC_CNTL 0x47FA 3739de2bdb3dSTom St Denis #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL 0x47FE 3740de2bdb3dSTom St Denis #define mmFMT4_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x47FC 3741de2bdb3dSTom St Denis #define mmFMT4_FMT_CRC_SIG_RED_GREEN 0x47FD 3742de2bdb3dSTom St Denis #define mmFMT4_FMT_CRC_SIG_RED_GREEN_MASK 0x47FB 3743de2bdb3dSTom St Denis #define mmFMT4_FMT_DEBUG_CNTL 0x47FF 3744de2bdb3dSTom St Denis #define mmFMT4_FMT_DITHER_RAND_B_SEED 0x47F5 3745de2bdb3dSTom St Denis #define mmFMT4_FMT_DITHER_RAND_G_SEED 0x47F4 3746de2bdb3dSTom St Denis #define mmFMT4_FMT_DITHER_RAND_R_SEED 0x47F3 3747de2bdb3dSTom St Denis #define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x47ED 3748de2bdb3dSTom St Denis #define mmFMT4_FMT_FORCE_DATA_0_1 0x47F0 3749de2bdb3dSTom St Denis #define mmFMT4_FMT_FORCE_DATA_2_3 0x47F1 3750de2bdb3dSTom St Denis #define mmFMT4_FMT_FORCE_OUTPUT_CNTL 0x47EF 3751de2bdb3dSTom St Denis #define mmFMT4_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x47F6 3752de2bdb3dSTom St Denis #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x47F7 3753de2bdb3dSTom St Denis #define mmFMT4_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x47F8 3754de2bdb3dSTom St Denis #define mmFMT4_FMT_TEST_DEBUG_DATA 0x47EC 3755de2bdb3dSTom St Denis #define mmFMT4_FMT_TEST_DEBUG_INDEX 0x47EB 3756de2bdb3dSTom St Denis #define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x4AF2 3757de2bdb3dSTom St Denis #define mmFMT5_FMT_CLAMP_CNTL 0x4AF9 3758de2bdb3dSTom St Denis #define mmFMT5_FMT_CONTROL 0x4AEE 3759de2bdb3dSTom St Denis #define mmFMT5_FMT_CRC_CNTL 0x4AFA 3760de2bdb3dSTom St Denis #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL 0x4AFE 3761de2bdb3dSTom St Denis #define mmFMT5_FMT_CRC_SIG_BLUE_CONTROL_MASK 0x4AFC 3762de2bdb3dSTom St Denis #define mmFMT5_FMT_CRC_SIG_RED_GREEN 0x4AFD 3763de2bdb3dSTom St Denis #define mmFMT5_FMT_CRC_SIG_RED_GREEN_MASK 0x4AFB 3764de2bdb3dSTom St Denis #define mmFMT5_FMT_DEBUG_CNTL 0x4AFF 3765de2bdb3dSTom St Denis #define mmFMT5_FMT_DITHER_RAND_B_SEED 0x4AF5 3766de2bdb3dSTom St Denis #define mmFMT5_FMT_DITHER_RAND_G_SEED 0x4AF4 3767de2bdb3dSTom St Denis #define mmFMT5_FMT_DITHER_RAND_R_SEED 0x4AF3 3768de2bdb3dSTom St Denis #define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x4AED 3769de2bdb3dSTom St Denis #define mmFMT5_FMT_FORCE_DATA_0_1 0x4AF0 3770de2bdb3dSTom St Denis #define mmFMT5_FMT_FORCE_DATA_2_3 0x4AF1 3771de2bdb3dSTom St Denis #define mmFMT5_FMT_FORCE_OUTPUT_CNTL 0x4AEF 3772de2bdb3dSTom St Denis #define mmFMT5_FMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x4AF6 3773de2bdb3dSTom St Denis #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x4AF7 3774de2bdb3dSTom St Denis #define mmFMT5_FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x4AF8 3775de2bdb3dSTom St Denis #define mmFMT5_FMT_TEST_DEBUG_DATA 0x4AEC 3776de2bdb3dSTom St Denis #define mmFMT5_FMT_TEST_DEBUG_INDEX 0x4AEB 3777de2bdb3dSTom St Denis #define mmFMT_BIT_DEPTH_CONTROL 0x1BF2 3778de2bdb3dSTom St Denis #define mmFMT_CLAMP_CNTL 0x1BF9 3779de2bdb3dSTom St Denis #define mmFMT_CONTROL 0x1BEE 3780de2bdb3dSTom St Denis #define mmFMT_CRC_CNTL 0x1BFA 3781de2bdb3dSTom St Denis #define mmFMT_CRC_SIG_BLUE_CONTROL 0x1BFE 3782de2bdb3dSTom St Denis #define mmFMT_CRC_SIG_BLUE_CONTROL_MASK 0x1BFC 3783de2bdb3dSTom St Denis #define mmFMT_CRC_SIG_RED_GREEN 0x1BFD 3784de2bdb3dSTom St Denis #define mmFMT_CRC_SIG_RED_GREEN_MASK 0x1BFB 3785de2bdb3dSTom St Denis #define mmFMT_DEBUG_CNTL 0x1BFF 3786de2bdb3dSTom St Denis #define mmFMT_DITHER_RAND_B_SEED 0x1BF5 3787de2bdb3dSTom St Denis #define mmFMT_DITHER_RAND_G_SEED 0x1BF4 3788de2bdb3dSTom St Denis #define mmFMT_DITHER_RAND_R_SEED 0x1BF3 3789de2bdb3dSTom St Denis #define mmFMT_DYNAMIC_EXP_CNTL 0x1BED 3790de2bdb3dSTom St Denis #define mmFMT_FORCE_DATA_0_1 0x1BF0 3791de2bdb3dSTom St Denis #define mmFMT_FORCE_DATA_2_3 0x1BF1 3792de2bdb3dSTom St Denis #define mmFMT_FORCE_OUTPUT_CNTL 0x1BEF 3793de2bdb3dSTom St Denis #define mmFMT_TEMPORAL_DITHER_PATTERN_CONTROL 0x1BF6 3794de2bdb3dSTom St Denis #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX 0x1BF7 3795de2bdb3dSTom St Denis #define mmFMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX 0x1BF8 3796de2bdb3dSTom St Denis #define mmFMT_TEST_DEBUG_DATA 0x1BEC 3797de2bdb3dSTom St Denis #define mmFMT_TEST_DEBUG_INDEX 0x1BEB 3798de2bdb3dSTom St Denis #define mmGAMUT_REMAP_C11_C12 0x1A5A 3799de2bdb3dSTom St Denis #define mmGAMUT_REMAP_C13_C14 0x1A5B 3800de2bdb3dSTom St Denis #define mmGAMUT_REMAP_C21_C22 0x1A5C 3801de2bdb3dSTom St Denis #define mmGAMUT_REMAP_C23_C24 0x1A5D 3802de2bdb3dSTom St Denis #define mmGAMUT_REMAP_C31_C32 0x1A5E 3803de2bdb3dSTom St Denis #define mmGAMUT_REMAP_C33_C34 0x1A5F 3804de2bdb3dSTom St Denis #define mmGAMUT_REMAP_CONTROL 0x1A59 3805de2bdb3dSTom St Denis #define mmGENENB 0x00F0 3806de2bdb3dSTom St Denis #define mmGENERIC_I2C_CONTROL 0x1834 3807de2bdb3dSTom St Denis #define mmGENERIC_I2C_DATA 0x183A 3808de2bdb3dSTom St Denis #define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1835 3809de2bdb3dSTom St Denis #define mmGENERIC_I2C_PIN_DEBUG 0x183C 3810de2bdb3dSTom St Denis #define mmGENERIC_I2C_PIN_SELECTION 0x183B 3811de2bdb3dSTom St Denis #define mmGENERIC_I2C_SETUP 0x1838 3812de2bdb3dSTom St Denis #define mmGENERIC_I2C_SPEED 0x1837 3813de2bdb3dSTom St Denis #define mmGENERIC_I2C_STATUS 0x1836 3814de2bdb3dSTom St Denis #define mmGENERIC_I2C_TRANSACTION 0x1839 3815de2bdb3dSTom St Denis #define mmGENFC_RD 0x00F2 3816de2bdb3dSTom St Denis #define mmGENFC_WT 0x00EE 3817de2bdb3dSTom St Denis #define mmGENMO_RD 0x00F3 3818de2bdb3dSTom St Denis #define mmGENMO_WT 0x00F0 3819de2bdb3dSTom St Denis #define mmGENS0 0x00F0 3820de2bdb3dSTom St Denis #define mmGENS1 0x00EE 3821de2bdb3dSTom St Denis #define mmGRPH8_DATA 0x00F3 3822de2bdb3dSTom St Denis #define mmGRPH8_IDX 0x00F3 3823de2bdb3dSTom St Denis #define mmGRPH_COMPRESS_PITCH 0x1A1A 3824de2bdb3dSTom St Denis #define mmGRPH_COMPRESS_SURFACE_ADDRESS 0x1A19 3825de2bdb3dSTom St Denis #define mmGRPH_COMPRESS_SURFACE_ADDRESS_HIGH 0x1A1B 3826de2bdb3dSTom St Denis #define mmGRPH_CONTROL 0x1A01 3827de2bdb3dSTom St Denis #define mmGRPH_DFQ_CONTROL 0x1A14 3828de2bdb3dSTom St Denis #define mmGRPH_DFQ_STATUS 0x1A15 3829de2bdb3dSTom St Denis #define mmGRPH_ENABLE 0x1A00 3830de2bdb3dSTom St Denis #define mmGRPH_FLIP_CONTROL 0x1A12 3831de2bdb3dSTom St Denis #define mmGRPH_INTERRUPT_CONTROL 0x1A17 3832de2bdb3dSTom St Denis #define mmGRPH_INTERRUPT_STATUS 0x1A16 3833de2bdb3dSTom St Denis #define mmGRPH_LUT_10BIT_BYPASS 0x1A02 3834de2bdb3dSTom St Denis #define mmGRPH_PITCH 0x1A06 3835de2bdb3dSTom St Denis #define mmGRPH_PRIMARY_SURFACE_ADDRESS 0x1A04 3836de2bdb3dSTom St Denis #define mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x1A07 3837de2bdb3dSTom St Denis #define mmGRPH_SECONDARY_SURFACE_ADDRESS 0x1A05 3838de2bdb3dSTom St Denis #define mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A08 3839de2bdb3dSTom St Denis #define mmGRPH_STEREOSYNC_FLIP 0x1A97 3840de2bdb3dSTom St Denis #define mmGRPH_SURFACE_ADDRESS_HIGH_INUSE 0x1A18 3841de2bdb3dSTom St Denis #define mmGRPH_SURFACE_ADDRESS_INUSE 0x1A13 3842de2bdb3dSTom St Denis #define mmGRPH_SURFACE_OFFSET_X 0x1A09 3843de2bdb3dSTom St Denis #define mmGRPH_SURFACE_OFFSET_Y 0x1A0A 3844de2bdb3dSTom St Denis #define mmGRPH_SWAP_CNTL 0x1A03 3845de2bdb3dSTom St Denis #define mmGRPH_UPDATE 0x1A11 3846de2bdb3dSTom St Denis #define mmGRPH_X_END 0x1A0D 3847de2bdb3dSTom St Denis #define mmGRPH_X_START 0x1A0B 3848de2bdb3dSTom St Denis #define mmGRPH_Y_END 0x1A0E 3849de2bdb3dSTom St Denis #define mmGRPH_Y_START 0x1A0C 3850de2bdb3dSTom St Denis #define mmHDMI_ACR_32_0 0x1C37 3851de2bdb3dSTom St Denis #define mmHDMI_ACR_32_1 0x1C38 3852de2bdb3dSTom St Denis #define mmHDMI_ACR_44_0 0x1C39 3853de2bdb3dSTom St Denis #define mmHDMI_ACR_44_1 0x1C3A 3854de2bdb3dSTom St Denis #define mmHDMI_ACR_48_0 0x1C3B 3855de2bdb3dSTom St Denis #define mmHDMI_ACR_48_1 0x1C3C 3856de2bdb3dSTom St Denis #define mmHDMI_ACR_PACKET_CONTROL 0x1C0F 3857de2bdb3dSTom St Denis #define mmHDMI_ACR_STATUS_0 0x1C3D 3858de2bdb3dSTom St Denis #define mmHDMI_ACR_STATUS_1 0x1C3E 3859de2bdb3dSTom St Denis #define mmHDMI_AUDIO_PACKET_CONTROL 0x1C0E 3860de2bdb3dSTom St Denis #define mmHDMI_CONTROL 0x1C0C 3861de2bdb3dSTom St Denis #define mmHDMI_GC 0x1C16 3862de2bdb3dSTom St Denis #define mmHDMI_GENERIC_PACKET_CONTROL0 0x1C13 3863de2bdb3dSTom St Denis #define mmHDMI_GENERIC_PACKET_CONTROL1 0x1C30 3864de2bdb3dSTom St Denis #define mmHDMI_INFOFRAME_CONTROL0 0x1C11 3865de2bdb3dSTom St Denis #define mmHDMI_INFOFRAME_CONTROL1 0x1C12 3866de2bdb3dSTom St Denis #define mmHDMI_STATUS 0x1C0D 3867de2bdb3dSTom St Denis #define mmHDMI_VBI_PACKET_CONTROL 0x1C10 3868de2bdb3dSTom St Denis #define mmINPUT_CSC_C11_C12 0x1A36 3869de2bdb3dSTom St Denis #define mmINPUT_CSC_C13_C14 0x1A37 3870de2bdb3dSTom St Denis #define mmINPUT_CSC_C21_C22 0x1A38 3871de2bdb3dSTom St Denis #define mmINPUT_CSC_C23_C24 0x1A39 3872de2bdb3dSTom St Denis #define mmINPUT_CSC_C31_C32 0x1A3A 3873de2bdb3dSTom St Denis #define mmINPUT_CSC_C33_C34 0x1A3B 3874de2bdb3dSTom St Denis #define mmINPUT_CSC_CONTROL 0x1A35 3875de2bdb3dSTom St Denis #define mmINPUT_GAMMA_CONTROL 0x1A10 3876de2bdb3dSTom St Denis #define mmKEY_CONTROL 0x1A53 3877de2bdb3dSTom St Denis #define mmKEY_RANGE_ALPHA 0x1A54 3878de2bdb3dSTom St Denis #define mmKEY_RANGE_BLUE 0x1A57 3879de2bdb3dSTom St Denis #define mmKEY_RANGE_GREEN 0x1A56 3880de2bdb3dSTom St Denis #define mmKEY_RANGE_RED 0x1A55 3881de2bdb3dSTom St Denis #define mmLB0_DC_MVP_LB_CONTROL 0x1ADB 3882de2bdb3dSTom St Denis #define mmLB0_LB_DEBUG 0x1AFC 3883de2bdb3dSTom St Denis #define mmLB0_LB_DEBUG2 0x1AC9 3884de2bdb3dSTom St Denis #define mmLB0_LB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 3885de2bdb3dSTom St Denis #define mmLB0_LB_SYNC_RESET_SEL 0x1ACA 3886de2bdb3dSTom St Denis #define mmLB0_LB_TEST_DEBUG_DATA 0x1AFF 3887de2bdb3dSTom St Denis #define mmLB0_LB_TEST_DEBUG_INDEX 0x1AFE 3888de2bdb3dSTom St Denis #define mmLB0_MVP_AFR_FLIP_FIFO_CNTL 0x1AD9 3889de2bdb3dSTom St Denis #define mmLB0_MVP_AFR_FLIP_MODE 0x1AD8 3890de2bdb3dSTom St Denis #define mmLB0_MVP_FLIP_LINE_NUM_INSERT 0x1ADA 3891de2bdb3dSTom St Denis #define mmLB1_DC_MVP_LB_CONTROL 0x1DDB 3892de2bdb3dSTom St Denis #define mmLB1_LB_DEBUG 0x1DFC 3893de2bdb3dSTom St Denis #define mmLB1_LB_DEBUG2 0x1DC9 3894de2bdb3dSTom St Denis #define mmLB1_LB_NO_OUTSTANDING_REQ_STATUS 0x1DC8 3895de2bdb3dSTom St Denis #define mmLB1_LB_SYNC_RESET_SEL 0x1DCA 3896de2bdb3dSTom St Denis #define mmLB1_LB_TEST_DEBUG_DATA 0x1DFF 3897de2bdb3dSTom St Denis #define mmLB1_LB_TEST_DEBUG_INDEX 0x1DFE 3898de2bdb3dSTom St Denis #define mmLB1_MVP_AFR_FLIP_FIFO_CNTL 0x1DD9 3899de2bdb3dSTom St Denis #define mmLB1_MVP_AFR_FLIP_MODE 0x1DD8 3900de2bdb3dSTom St Denis #define mmLB1_MVP_FLIP_LINE_NUM_INSERT 0x1DDA 3901de2bdb3dSTom St Denis #define mmLB2_DC_MVP_LB_CONTROL 0x40DB 3902de2bdb3dSTom St Denis #define mmLB2_LB_DEBUG 0x40FC 3903de2bdb3dSTom St Denis #define mmLB2_LB_DEBUG2 0x40C9 3904de2bdb3dSTom St Denis #define mmLB2_LB_NO_OUTSTANDING_REQ_STATUS 0x40C8 3905de2bdb3dSTom St Denis #define mmLB2_LB_SYNC_RESET_SEL 0x40CA 3906de2bdb3dSTom St Denis #define mmLB2_LB_TEST_DEBUG_DATA 0x40FF 3907de2bdb3dSTom St Denis #define mmLB2_LB_TEST_DEBUG_INDEX 0x40FE 3908de2bdb3dSTom St Denis #define mmLB2_MVP_AFR_FLIP_FIFO_CNTL 0x40D9 3909de2bdb3dSTom St Denis #define mmLB2_MVP_AFR_FLIP_MODE 0x40D8 3910de2bdb3dSTom St Denis #define mmLB2_MVP_FLIP_LINE_NUM_INSERT 0x40DA 3911de2bdb3dSTom St Denis #define mmLB3_DC_MVP_LB_CONTROL 0x43DB 3912de2bdb3dSTom St Denis #define mmLB3_LB_DEBUG 0x43FC 3913de2bdb3dSTom St Denis #define mmLB3_LB_DEBUG2 0x43C9 3914de2bdb3dSTom St Denis #define mmLB3_LB_NO_OUTSTANDING_REQ_STATUS 0x43C8 3915de2bdb3dSTom St Denis #define mmLB3_LB_SYNC_RESET_SEL 0x43CA 3916de2bdb3dSTom St Denis #define mmLB3_LB_TEST_DEBUG_DATA 0x43FF 3917de2bdb3dSTom St Denis #define mmLB3_LB_TEST_DEBUG_INDEX 0x43FE 3918de2bdb3dSTom St Denis #define mmLB3_MVP_AFR_FLIP_FIFO_CNTL 0x43D9 3919de2bdb3dSTom St Denis #define mmLB3_MVP_AFR_FLIP_MODE 0x43D8 3920de2bdb3dSTom St Denis #define mmLB3_MVP_FLIP_LINE_NUM_INSERT 0x43DA 3921de2bdb3dSTom St Denis #define mmLB4_DC_MVP_LB_CONTROL 0x46DB 3922de2bdb3dSTom St Denis #define mmLB4_LB_DEBUG 0x46FC 3923de2bdb3dSTom St Denis #define mmLB4_LB_DEBUG2 0x46C9 3924de2bdb3dSTom St Denis #define mmLB4_LB_NO_OUTSTANDING_REQ_STATUS 0x46C8 3925de2bdb3dSTom St Denis #define mmLB4_LB_SYNC_RESET_SEL 0x46CA 3926de2bdb3dSTom St Denis #define mmLB4_LB_TEST_DEBUG_DATA 0x46FF 3927de2bdb3dSTom St Denis #define mmLB4_LB_TEST_DEBUG_INDEX 0x46FE 3928de2bdb3dSTom St Denis #define mmLB4_MVP_AFR_FLIP_FIFO_CNTL 0x46D9 3929de2bdb3dSTom St Denis #define mmLB4_MVP_AFR_FLIP_MODE 0x46D8 3930de2bdb3dSTom St Denis #define mmLB4_MVP_FLIP_LINE_NUM_INSERT 0x46DA 3931de2bdb3dSTom St Denis #define mmLB5_DC_MVP_LB_CONTROL 0x49DB 3932de2bdb3dSTom St Denis #define mmLB5_LB_DEBUG 0x49FC 3933de2bdb3dSTom St Denis #define mmLB5_LB_DEBUG2 0x49C9 3934de2bdb3dSTom St Denis #define mmLB5_LB_NO_OUTSTANDING_REQ_STATUS 0x49C8 3935de2bdb3dSTom St Denis #define mmLB5_LB_SYNC_RESET_SEL 0x49CA 3936de2bdb3dSTom St Denis #define mmLB5_LB_TEST_DEBUG_DATA 0x49FF 3937de2bdb3dSTom St Denis #define mmLB5_LB_TEST_DEBUG_INDEX 0x49FE 3938de2bdb3dSTom St Denis #define mmLB5_MVP_AFR_FLIP_FIFO_CNTL 0x49D9 3939de2bdb3dSTom St Denis #define mmLB5_MVP_AFR_FLIP_MODE 0x49D8 3940de2bdb3dSTom St Denis #define mmLB5_MVP_FLIP_LINE_NUM_INSERT 0x49DA 3941de2bdb3dSTom St Denis #define mmLB_DEBUG 0x1AFC 3942de2bdb3dSTom St Denis #define mmLB_DEBUG2 0x1AC9 3943de2bdb3dSTom St Denis #define mmLB_NO_OUTSTANDING_REQ_STATUS 0x1AC8 3944de2bdb3dSTom St Denis #define mmLB_SYNC_RESET_SEL 0x1ACA 3945de2bdb3dSTom St Denis #define mmLB_TEST_DEBUG_DATA 0x1AFF 3946de2bdb3dSTom St Denis #define mmLB_TEST_DEBUG_INDEX 0x1AFE 3947de2bdb3dSTom St Denis #define mmLIGHT_SLEEP_CNTL 0x0132 3948de2bdb3dSTom St Denis #define mmLOW_POWER_TILING_CONTROL 0x0325 3949de2bdb3dSTom St Denis #define mmLVDS_DATA_CNTL 0x1C8C 3950de2bdb3dSTom St Denis #define mmLVTMA_PWRSEQ_CNTL 0x1919 3951de2bdb3dSTom St Denis #define mmLVTMA_PWRSEQ_DELAY1 0x191C 3952de2bdb3dSTom St Denis #define mmLVTMA_PWRSEQ_DELAY2 0x191D 3953de2bdb3dSTom St Denis #define mmLVTMA_PWRSEQ_REF_DIV 0x191B 3954de2bdb3dSTom St Denis #define mmLVTMA_PWRSEQ_STATE 0x191A 3955de2bdb3dSTom St Denis #define mmMASTER_COMM_CMD_REG 0x161F 3956de2bdb3dSTom St Denis #define mmMASTER_COMM_CNTL_REG 0x1620 3957de2bdb3dSTom St Denis #define mmMASTER_COMM_DATA_REG1 0x161C 3958de2bdb3dSTom St Denis #define mmMASTER_COMM_DATA_REG2 0x161D 3959de2bdb3dSTom St Denis #define mmMASTER_COMM_DATA_REG3 0x161E 3960de2bdb3dSTom St Denis #define mmMASTER_UPDATE_LOCK 0x1BBD 3961de2bdb3dSTom St Denis #define mmMASTER_UPDATE_MODE 0x1BBE 3962de2bdb3dSTom St Denis #define mmMC_DC_INTERFACE_NACK_STATUS 0x031C 3963de2bdb3dSTom St Denis #define mmMCIF_CONTROL 0x0314 3964de2bdb3dSTom St Denis #define mmMCIF_MEM_CONTROL 0x0319 3965de2bdb3dSTom St Denis #define mmMCIF_TEST_DEBUG_DATA 0x0317 3966de2bdb3dSTom St Denis #define mmMCIF_TEST_DEBUG_INDEX 0x0316 3967de2bdb3dSTom St Denis #define mmMCIF_VMID 0x0318 3968de2bdb3dSTom St Denis #define mmMCIF_WRITE_COMBINE_CONTROL 0x0315 3969de2bdb3dSTom St Denis #define mmMICROSECOND_TIME_BASE_DIV 0x013B 3970de2bdb3dSTom St Denis #define mmMILLISECOND_TIME_BASE_DIV 0x0130 3971de2bdb3dSTom St Denis #define mmMVP_AFR_FLIP_FIFO_CNTL 0x1AD9 3972de2bdb3dSTom St Denis #define mmMVP_AFR_FLIP_MODE 0x1AD8 3973de2bdb3dSTom St Denis #define mmMVP_BLACK_KEYER 0x1686 3974de2bdb3dSTom St Denis #define mmMVP_CONTROL1 0x1680 3975de2bdb3dSTom St Denis #define mmMVP_CONTROL2 0x1681 3976de2bdb3dSTom St Denis #define mmMVP_CONTROL3 0x168A 3977de2bdb3dSTom St Denis #define mmMVP_CRC_CNTL 0x1687 3978de2bdb3dSTom St Denis #define mmMVP_CRC_RESULT_BLUE_GREEN 0x1688 3979de2bdb3dSTom St Denis #define mmMVP_CRC_RESULT_RED 0x1689 3980de2bdb3dSTom St Denis #define mmMVP_DEBUG 0x168F 3981de2bdb3dSTom St Denis #define mmMVP_FIFO_CONTROL 0x1682 3982de2bdb3dSTom St Denis #define mmMVP_FIFO_STATUS 0x1683 3983de2bdb3dSTom St Denis #define mmMVP_FLIP_LINE_NUM_INSERT 0x1ADA 3984de2bdb3dSTom St Denis #define mmMVP_INBAND_CNTL_CAP 0x1685 3985de2bdb3dSTom St Denis #define mmMVP_RECEIVE_CNT_CNTL1 0x168B 3986de2bdb3dSTom St Denis #define mmMVP_RECEIVE_CNT_CNTL2 0x168C 3987de2bdb3dSTom St Denis #define mmMVP_SLAVE_STATUS 0x1684 3988de2bdb3dSTom St Denis #define mmMVP_TEST_DEBUG_DATA 0x168E 3989de2bdb3dSTom St Denis #define mmMVP_TEST_DEBUG_INDEX 0x168D 3990de2bdb3dSTom St Denis #define mmOUTPUT_CSC_C11_C12 0x1A3D 3991de2bdb3dSTom St Denis #define mmOUTPUT_CSC_C13_C14 0x1A3E 3992de2bdb3dSTom St Denis #define mmOUTPUT_CSC_C21_C22 0x1A3F 3993de2bdb3dSTom St Denis #define mmOUTPUT_CSC_C23_C24 0x1A40 3994de2bdb3dSTom St Denis #define mmOUTPUT_CSC_C31_C32 0x1A41 3995de2bdb3dSTom St Denis #define mmOUTPUT_CSC_C33_C34 0x1A42 3996de2bdb3dSTom St Denis #define mmOUTPUT_CSC_CONTROL 0x1A3C 3997de2bdb3dSTom St Denis #define mmOUT_ROUND_CONTROL 0x1A51 3998de2bdb3dSTom St Denis #define mmOVL_CONTROL1 0x1A1D 3999de2bdb3dSTom St Denis #define mmOVL_CONTROL2 0x1A1E 4000de2bdb3dSTom St Denis #define mmOVL_DFQ_CONTROL 0x1A29 4001de2bdb3dSTom St Denis #define mmOVL_DFQ_STATUS 0x1A2A 4002de2bdb3dSTom St Denis #define mmOVL_ENABLE 0x1A1C 4003de2bdb3dSTom St Denis #define mmOVL_END 0x1A26 4004de2bdb3dSTom St Denis #define mmOVL_PITCH 0x1A21 4005de2bdb3dSTom St Denis #define mmOVLSCL_EDGE_PIXEL_CNTL 0x1A2C 4006de2bdb3dSTom St Denis #define mmOVL_SECONDARY_SURFACE_ADDRESS 0x1A92 4007de2bdb3dSTom St Denis #define mmOVL_SECONDARY_SURFACE_ADDRESS_HIGH 0x1A94 4008de2bdb3dSTom St Denis #define mmOVL_START 0x1A25 4009de2bdb3dSTom St Denis #define mmOVL_STEREOSYNC_FLIP 0x1A93 4010de2bdb3dSTom St Denis #define mmOVL_SURFACE_ADDRESS 0x1A20 4011de2bdb3dSTom St Denis #define mmOVL_SURFACE_ADDRESS_HIGH 0x1A22 4012de2bdb3dSTom St Denis #define mmOVL_SURFACE_ADDRESS_HIGH_INUSE 0x1A2B 4013de2bdb3dSTom St Denis #define mmOVL_SURFACE_ADDRESS_INUSE 0x1A28 4014de2bdb3dSTom St Denis #define mmOVL_SURFACE_OFFSET_X 0x1A23 4015de2bdb3dSTom St Denis #define mmOVL_SURFACE_OFFSET_Y 0x1A24 4016de2bdb3dSTom St Denis #define mmOVL_SWAP_CNTL 0x1A1F 4017de2bdb3dSTom St Denis #define mmOVL_UPDATE 0x1A27 4018de2bdb3dSTom St Denis #define mmPHY_AUX_CNTL 0x197F 4019de2bdb3dSTom St Denis #define mmPIPE0_ARBITRATION_CONTROL3 0x02FA 4020de2bdb3dSTom St Denis #define mmPIPE0_DMIF_BUFFER_CONTROL 0x0328 4021de2bdb3dSTom St Denis #define mmPIPE0_MAX_REQUESTS 0x0302 4022de2bdb3dSTom St Denis #define mmPIPE0_PG_CONFIG 0x1760 4023de2bdb3dSTom St Denis #define mmPIPE0_PG_ENABLE 0x1761 4024de2bdb3dSTom St Denis #define mmPIPE0_PG_STATUS 0x1762 4025de2bdb3dSTom St Denis #define mmPIPE1_ARBITRATION_CONTROL3 0x02FB 4026de2bdb3dSTom St Denis #define mmPIPE1_DMIF_BUFFER_CONTROL 0x0330 4027de2bdb3dSTom St Denis #define mmPIPE1_MAX_REQUESTS 0x0303 4028de2bdb3dSTom St Denis #define mmPIPE1_PG_CONFIG 0x1764 4029de2bdb3dSTom St Denis #define mmPIPE1_PG_ENABLE 0x1765 4030de2bdb3dSTom St Denis #define mmPIPE1_PG_STATUS 0x1766 4031de2bdb3dSTom St Denis #define mmPIPE2_ARBITRATION_CONTROL3 0x02FC 4032de2bdb3dSTom St Denis #define mmPIPE2_DMIF_BUFFER_CONTROL 0x0338 4033de2bdb3dSTom St Denis #define mmPIPE2_MAX_REQUESTS 0x0304 4034de2bdb3dSTom St Denis #define mmPIPE2_PG_CONFIG 0x1768 4035de2bdb3dSTom St Denis #define mmPIPE2_PG_ENABLE 0x1769 4036de2bdb3dSTom St Denis #define mmPIPE2_PG_STATUS 0x176A 4037de2bdb3dSTom St Denis #define mmPIPE3_ARBITRATION_CONTROL3 0x02FD 4038de2bdb3dSTom St Denis #define mmPIPE3_DMIF_BUFFER_CONTROL 0x0340 4039de2bdb3dSTom St Denis #define mmPIPE3_MAX_REQUESTS 0x0305 4040de2bdb3dSTom St Denis #define mmPIPE3_PG_CONFIG 0x176C 4041de2bdb3dSTom St Denis #define mmPIPE3_PG_ENABLE 0x176D 4042de2bdb3dSTom St Denis #define mmPIPE3_PG_STATUS 0x176E 4043de2bdb3dSTom St Denis #define mmPIPE4_ARBITRATION_CONTROL3 0x02FE 4044de2bdb3dSTom St Denis #define mmPIPE4_DMIF_BUFFER_CONTROL 0x0348 4045de2bdb3dSTom St Denis #define mmPIPE4_MAX_REQUESTS 0x0306 4046de2bdb3dSTom St Denis #define mmPIPE4_PG_CONFIG 0x1770 4047de2bdb3dSTom St Denis #define mmPIPE4_PG_ENABLE 0x1771 4048de2bdb3dSTom St Denis #define mmPIPE4_PG_STATUS 0x1772 4049de2bdb3dSTom St Denis #define mmPIPE5_ARBITRATION_CONTROL3 0x02FF 4050de2bdb3dSTom St Denis #define mmPIPE5_DMIF_BUFFER_CONTROL 0x0350 4051de2bdb3dSTom St Denis #define mmPIPE5_MAX_REQUESTS 0x0307 4052de2bdb3dSTom St Denis #define mmPIPE5_PG_CONFIG 0x1774 4053de2bdb3dSTom St Denis #define mmPIPE5_PG_ENABLE 0x1775 4054de2bdb3dSTom St Denis #define mmPIPE5_PG_STATUS 0x1776 4055de2bdb3dSTom St Denis #define mmPIXCLK0_RESYNC_CNTL 0x013A 4056de2bdb3dSTom St Denis #define mmPIXCLK1_RESYNC_CNTL 0x0138 4057de2bdb3dSTom St Denis #define mmPIXCLK2_RESYNC_CNTL 0x0139 4058de2bdb3dSTom St Denis #define mmPLL_ANALOG 0x1708 4059de2bdb3dSTom St Denis #define mmPLL_CNTL 0x1707 4060de2bdb3dSTom St Denis #define mmPLL_DEBUG_CNTL 0x170B 4061de2bdb3dSTom St Denis #define mmPLL_DISPCLK_CURRENT_DTO_PHASE 0x170F 4062de2bdb3dSTom St Denis #define mmPLL_DISPCLK_DTO_CNTL 0x170E 4063de2bdb3dSTom St Denis #define mmPLL_DS_CNTL 0x1705 4064de2bdb3dSTom St Denis #define mmPLL_FB_DIV 0x1701 4065de2bdb3dSTom St Denis #define mmPLL_IDCLK_CNTL 0x1706 4066de2bdb3dSTom St Denis #define mmPLL_POST_DIV 0x1702 4067de2bdb3dSTom St Denis #define mmPLL_REF_DIV 0x1700 4068de2bdb3dSTom St Denis #define mmPLL_SS_AMOUNT_DSFRAC 0x1703 4069de2bdb3dSTom St Denis #define mmPLL_SS_CNTL 0x1704 4070de2bdb3dSTom St Denis #define mmPLL_UNLOCK_DETECT_CNTL 0x170A 4071de2bdb3dSTom St Denis #define mmPLL_UPDATE_CNTL 0x170D 4072de2bdb3dSTom St Denis #define mmPLL_UPDATE_LOCK 0x170C 4073de2bdb3dSTom St Denis #define mmPLL_VREG_CNTL 0x1709 4074de2bdb3dSTom St Denis #define mmPRESCALE_GRPH_CONTROL 0x1A2D 4075de2bdb3dSTom St Denis #define mmPRESCALE_OVL_CONTROL 0x1A31 4076de2bdb3dSTom St Denis #define mmPRESCALE_VALUES_GRPH_B 0x1A30 4077de2bdb3dSTom St Denis #define mmPRESCALE_VALUES_GRPH_G 0x1A2F 4078de2bdb3dSTom St Denis #define mmPRESCALE_VALUES_GRPH_R 0x1A2E 4079de2bdb3dSTom St Denis #define mmPRESCALE_VALUES_OVL_CB 0x1A32 4080de2bdb3dSTom St Denis #define mmPRESCALE_VALUES_OVL_CR 0x1A34 4081de2bdb3dSTom St Denis #define mmPRESCALE_VALUES_OVL_Y 0x1A33 4082de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_END_CNTL1 0x1AA6 4083de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_END_CNTL2 0x1AA7 4084de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_0_1 0x1AA8 4085de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_10_11 0x1AAD 4086de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_12_13 0x1AAE 4087de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_14_15 0x1AAF 4088de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_2_3 0x1AA9 4089de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_4_5 0x1AAA 4090de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_6_7 0x1AAB 4091de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_REGION_8_9 0x1AAC 4092de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_SLOPE_CNTL 0x1AA5 4093de2bdb3dSTom St Denis #define mmREGAMMA_CNTLA_START_CNTL 0x1AA4 4094de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_END_CNTL1 0x1AB2 4095de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_END_CNTL2 0x1AB3 4096de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_0_1 0x1AB4 4097de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_10_11 0x1AB9 4098de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_12_13 0x1ABA 4099de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_14_15 0x1ABB 4100de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_2_3 0x1AB5 4101de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_4_5 0x1AB6 4102de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_6_7 0x1AB7 4103de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_REGION_8_9 0x1AB8 4104de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_SLOPE_CNTL 0x1AB1 4105de2bdb3dSTom St Denis #define mmREGAMMA_CNTLB_START_CNTL 0x1AB0 4106de2bdb3dSTom St Denis #define mmREGAMMA_CONTROL 0x1AA0 4107de2bdb3dSTom St Denis #define mmREGAMMA_LUT_DATA 0x1AA2 4108de2bdb3dSTom St Denis #define mmREGAMMA_LUT_INDEX 0x1AA1 4109de2bdb3dSTom St Denis #define mmREGAMMA_LUT_WRITE_EN_MASK 0x1AA3 4110de2bdb3dSTom St Denis #define mmSCL0_EXT_OVERSCAN_LEFT_RIGHT 0x1B5E 4111de2bdb3dSTom St Denis #define mmSCL0_EXT_OVERSCAN_TOP_BOTTOM 0x1B5F 4112de2bdb3dSTom St Denis #define mmSCL0_SCL_ALU_CONTROL 0x1B54 4113de2bdb3dSTom St Denis #define mmSCL0_SCL_AUTOMATIC_MODE_CONTROL 0x1B47 4114de2bdb3dSTom St Denis #define mmSCL0_SCL_BYPASS_CONTROL 0x1B45 4115de2bdb3dSTom St Denis #define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55 4116de2bdb3dSTom St Denis #define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40 4117de2bdb3dSTom St Denis #define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41 4118de2bdb3dSTom St Denis #define mmSCL0_SCL_CONTROL 0x1B44 4119de2bdb3dSTom St Denis #define mmSCL0_SCL_DEBUG 0x1B6A 4120de2bdb3dSTom St Denis #define mmSCL0_SCL_DEBUG2 0x1B69 4121de2bdb3dSTom St Denis #define mmSCL0_SCL_F_SHARP_CONTROL 0x1B53 4122de2bdb3dSTom St Denis #define mmSCL0_SCL_HORZ_FILTER_CONTROL 0x1B4A 4123de2bdb3dSTom St Denis #define mmSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x1B4B 4124de2bdb3dSTom St Denis #define mmSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x1B46 4125de2bdb3dSTom St Denis #define mmSCL0_SCL_MODE_CHANGE_DET1 0x1B60 4126de2bdb3dSTom St Denis #define mmSCL0_SCL_MODE_CHANGE_DET2 0x1B61 4127de2bdb3dSTom St Denis #define mmSCL0_SCL_MODE_CHANGE_DET3 0x1B62 4128de2bdb3dSTom St Denis #define mmSCL0_SCL_MODE_CHANGE_MASK 0x1B63 4129de2bdb3dSTom St Denis #define mmSCL0_SCL_TAP_CONTROL 0x1B43 4130de2bdb3dSTom St Denis #define mmSCL0_SCL_TEST_DEBUG_DATA 0x1B6C 4131de2bdb3dSTom St Denis #define mmSCL0_SCL_TEST_DEBUG_INDEX 0x1B6B 4132de2bdb3dSTom St Denis #define mmSCL0_SCL_UPDATE 0x1B51 4133de2bdb3dSTom St Denis #define mmSCL0_SCL_VERT_FILTER_CONTROL 0x1B4E 4134de2bdb3dSTom St Denis #define mmSCL0_SCL_VERT_FILTER_INIT 0x1B50 4135de2bdb3dSTom St Denis #define mmSCL0_SCL_VERT_FILTER_INIT_BOT 0x1B57 4136de2bdb3dSTom St Denis #define mmSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x1B4F 4137de2bdb3dSTom St Denis #define mmSCL0_VIEWPORT_SIZE 0x1B5D 4138de2bdb3dSTom St Denis #define mmSCL0_VIEWPORT_START 0x1B5C 4139de2bdb3dSTom St Denis #define mmSCL1_EXT_OVERSCAN_LEFT_RIGHT 0x1E5E 4140de2bdb3dSTom St Denis #define mmSCL1_EXT_OVERSCAN_TOP_BOTTOM 0x1E5F 4141de2bdb3dSTom St Denis #define mmSCL1_SCL_ALU_CONTROL 0x1E54 4142de2bdb3dSTom St Denis #define mmSCL1_SCL_AUTOMATIC_MODE_CONTROL 0x1E47 4143de2bdb3dSTom St Denis #define mmSCL1_SCL_BYPASS_CONTROL 0x1E45 4144de2bdb3dSTom St Denis #define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55 4145de2bdb3dSTom St Denis #define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40 4146de2bdb3dSTom St Denis #define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41 4147de2bdb3dSTom St Denis #define mmSCL1_SCL_CONTROL 0x1E44 4148de2bdb3dSTom St Denis #define mmSCL1_SCL_DEBUG 0x1E6A 4149de2bdb3dSTom St Denis #define mmSCL1_SCL_DEBUG2 0x1E69 4150de2bdb3dSTom St Denis #define mmSCL1_SCL_F_SHARP_CONTROL 0x1E53 4151de2bdb3dSTom St Denis #define mmSCL1_SCL_HORZ_FILTER_CONTROL 0x1E4A 4152de2bdb3dSTom St Denis #define mmSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x1E4B 4153de2bdb3dSTom St Denis #define mmSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x1E46 4154de2bdb3dSTom St Denis #define mmSCL1_SCL_MODE_CHANGE_DET1 0x1E60 4155de2bdb3dSTom St Denis #define mmSCL1_SCL_MODE_CHANGE_DET2 0x1E61 4156de2bdb3dSTom St Denis #define mmSCL1_SCL_MODE_CHANGE_DET3 0x1E62 4157de2bdb3dSTom St Denis #define mmSCL1_SCL_MODE_CHANGE_MASK 0x1E63 4158de2bdb3dSTom St Denis #define mmSCL1_SCL_TAP_CONTROL 0x1E43 4159de2bdb3dSTom St Denis #define mmSCL1_SCL_TEST_DEBUG_DATA 0x1E6C 4160de2bdb3dSTom St Denis #define mmSCL1_SCL_TEST_DEBUG_INDEX 0x1E6B 4161de2bdb3dSTom St Denis #define mmSCL1_SCL_UPDATE 0x1E51 4162de2bdb3dSTom St Denis #define mmSCL1_SCL_VERT_FILTER_CONTROL 0x1E4E 4163de2bdb3dSTom St Denis #define mmSCL1_SCL_VERT_FILTER_INIT 0x1E50 4164de2bdb3dSTom St Denis #define mmSCL1_SCL_VERT_FILTER_INIT_BOT 0x1E57 4165de2bdb3dSTom St Denis #define mmSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x1E4F 4166de2bdb3dSTom St Denis #define mmSCL1_VIEWPORT_SIZE 0x1E5D 4167de2bdb3dSTom St Denis #define mmSCL1_VIEWPORT_START 0x1E5C 4168de2bdb3dSTom St Denis #define mmSCL2_EXT_OVERSCAN_LEFT_RIGHT 0x415E 4169de2bdb3dSTom St Denis #define mmSCL2_EXT_OVERSCAN_TOP_BOTTOM 0x415F 4170de2bdb3dSTom St Denis #define mmSCL2_SCL_ALU_CONTROL 0x4154 4171de2bdb3dSTom St Denis #define mmSCL2_SCL_AUTOMATIC_MODE_CONTROL 0x4147 4172de2bdb3dSTom St Denis #define mmSCL2_SCL_BYPASS_CONTROL 0x4145 4173de2bdb3dSTom St Denis #define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155 4174de2bdb3dSTom St Denis #define mmSCL2_SCL_COEF_RAM_SELECT 0x4140 4175de2bdb3dSTom St Denis #define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141 4176de2bdb3dSTom St Denis #define mmSCL2_SCL_CONTROL 0x4144 4177de2bdb3dSTom St Denis #define mmSCL2_SCL_DEBUG 0x416A 4178de2bdb3dSTom St Denis #define mmSCL2_SCL_DEBUG2 0x4169 4179de2bdb3dSTom St Denis #define mmSCL2_SCL_F_SHARP_CONTROL 0x4153 4180de2bdb3dSTom St Denis #define mmSCL2_SCL_HORZ_FILTER_CONTROL 0x414A 4181de2bdb3dSTom St Denis #define mmSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x414B 4182de2bdb3dSTom St Denis #define mmSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x4146 4183de2bdb3dSTom St Denis #define mmSCL2_SCL_MODE_CHANGE_DET1 0x4160 4184de2bdb3dSTom St Denis #define mmSCL2_SCL_MODE_CHANGE_DET2 0x4161 4185de2bdb3dSTom St Denis #define mmSCL2_SCL_MODE_CHANGE_DET3 0x4162 4186de2bdb3dSTom St Denis #define mmSCL2_SCL_MODE_CHANGE_MASK 0x4163 4187de2bdb3dSTom St Denis #define mmSCL2_SCL_TAP_CONTROL 0x4143 4188de2bdb3dSTom St Denis #define mmSCL2_SCL_TEST_DEBUG_DATA 0x416C 4189de2bdb3dSTom St Denis #define mmSCL2_SCL_TEST_DEBUG_INDEX 0x416B 4190de2bdb3dSTom St Denis #define mmSCL2_SCL_UPDATE 0x4151 4191de2bdb3dSTom St Denis #define mmSCL2_SCL_VERT_FILTER_CONTROL 0x414E 4192de2bdb3dSTom St Denis #define mmSCL2_SCL_VERT_FILTER_INIT 0x4150 4193de2bdb3dSTom St Denis #define mmSCL2_SCL_VERT_FILTER_INIT_BOT 0x4157 4194de2bdb3dSTom St Denis #define mmSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x414F 4195de2bdb3dSTom St Denis #define mmSCL2_VIEWPORT_SIZE 0x415D 4196de2bdb3dSTom St Denis #define mmSCL2_VIEWPORT_START 0x415C 4197de2bdb3dSTom St Denis #define mmSCL3_EXT_OVERSCAN_LEFT_RIGHT 0x445E 4198de2bdb3dSTom St Denis #define mmSCL3_EXT_OVERSCAN_TOP_BOTTOM 0x445F 4199de2bdb3dSTom St Denis #define mmSCL3_SCL_ALU_CONTROL 0x4454 4200de2bdb3dSTom St Denis #define mmSCL3_SCL_AUTOMATIC_MODE_CONTROL 0x4447 4201de2bdb3dSTom St Denis #define mmSCL3_SCL_BYPASS_CONTROL 0x4445 4202de2bdb3dSTom St Denis #define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455 4203de2bdb3dSTom St Denis #define mmSCL3_SCL_COEF_RAM_SELECT 0x4440 4204de2bdb3dSTom St Denis #define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441 4205de2bdb3dSTom St Denis #define mmSCL3_SCL_CONTROL 0x4444 4206de2bdb3dSTom St Denis #define mmSCL3_SCL_DEBUG 0x446A 4207de2bdb3dSTom St Denis #define mmSCL3_SCL_DEBUG2 0x4469 4208de2bdb3dSTom St Denis #define mmSCL3_SCL_F_SHARP_CONTROL 0x4453 4209de2bdb3dSTom St Denis #define mmSCL3_SCL_HORZ_FILTER_CONTROL 0x444A 4210de2bdb3dSTom St Denis #define mmSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x444B 4211de2bdb3dSTom St Denis #define mmSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x4446 4212de2bdb3dSTom St Denis #define mmSCL3_SCL_MODE_CHANGE_DET1 0x4460 4213de2bdb3dSTom St Denis #define mmSCL3_SCL_MODE_CHANGE_DET2 0x4461 4214de2bdb3dSTom St Denis #define mmSCL3_SCL_MODE_CHANGE_DET3 0x4462 4215de2bdb3dSTom St Denis #define mmSCL3_SCL_MODE_CHANGE_MASK 0x4463 4216de2bdb3dSTom St Denis #define mmSCL3_SCL_TAP_CONTROL 0x4443 4217de2bdb3dSTom St Denis #define mmSCL3_SCL_TEST_DEBUG_DATA 0x446C 4218de2bdb3dSTom St Denis #define mmSCL3_SCL_TEST_DEBUG_INDEX 0x446B 4219de2bdb3dSTom St Denis #define mmSCL3_SCL_UPDATE 0x4451 4220de2bdb3dSTom St Denis #define mmSCL3_SCL_VERT_FILTER_CONTROL 0x444E 4221de2bdb3dSTom St Denis #define mmSCL3_SCL_VERT_FILTER_INIT 0x4450 4222de2bdb3dSTom St Denis #define mmSCL3_SCL_VERT_FILTER_INIT_BOT 0x4457 4223de2bdb3dSTom St Denis #define mmSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x444F 4224de2bdb3dSTom St Denis #define mmSCL3_VIEWPORT_SIZE 0x445D 4225de2bdb3dSTom St Denis #define mmSCL3_VIEWPORT_START 0x445C 4226de2bdb3dSTom St Denis #define mmSCL4_EXT_OVERSCAN_LEFT_RIGHT 0x475E 4227de2bdb3dSTom St Denis #define mmSCL4_EXT_OVERSCAN_TOP_BOTTOM 0x475F 4228de2bdb3dSTom St Denis #define mmSCL4_SCL_ALU_CONTROL 0x4754 4229de2bdb3dSTom St Denis #define mmSCL4_SCL_AUTOMATIC_MODE_CONTROL 0x4747 4230de2bdb3dSTom St Denis #define mmSCL4_SCL_BYPASS_CONTROL 0x4745 4231de2bdb3dSTom St Denis #define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755 4232de2bdb3dSTom St Denis #define mmSCL4_SCL_COEF_RAM_SELECT 0x4740 4233de2bdb3dSTom St Denis #define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741 4234de2bdb3dSTom St Denis #define mmSCL4_SCL_CONTROL 0x4744 4235de2bdb3dSTom St Denis #define mmSCL4_SCL_DEBUG 0x476A 4236de2bdb3dSTom St Denis #define mmSCL4_SCL_DEBUG2 0x4769 4237de2bdb3dSTom St Denis #define mmSCL4_SCL_F_SHARP_CONTROL 0x4753 4238de2bdb3dSTom St Denis #define mmSCL4_SCL_HORZ_FILTER_CONTROL 0x474A 4239de2bdb3dSTom St Denis #define mmSCL4_SCL_HORZ_FILTER_SCALE_RATIO 0x474B 4240de2bdb3dSTom St Denis #define mmSCL4_SCL_MANUAL_REPLICATE_CONTROL 0x4746 4241de2bdb3dSTom St Denis #define mmSCL4_SCL_MODE_CHANGE_DET1 0x4760 4242de2bdb3dSTom St Denis #define mmSCL4_SCL_MODE_CHANGE_DET2 0x4761 4243de2bdb3dSTom St Denis #define mmSCL4_SCL_MODE_CHANGE_DET3 0x4762 4244de2bdb3dSTom St Denis #define mmSCL4_SCL_MODE_CHANGE_MASK 0x4763 4245de2bdb3dSTom St Denis #define mmSCL4_SCL_TAP_CONTROL 0x4743 4246de2bdb3dSTom St Denis #define mmSCL4_SCL_TEST_DEBUG_DATA 0x476C 4247de2bdb3dSTom St Denis #define mmSCL4_SCL_TEST_DEBUG_INDEX 0x476B 4248de2bdb3dSTom St Denis #define mmSCL4_SCL_UPDATE 0x4751 4249de2bdb3dSTom St Denis #define mmSCL4_SCL_VERT_FILTER_CONTROL 0x474E 4250de2bdb3dSTom St Denis #define mmSCL4_SCL_VERT_FILTER_INIT 0x4750 4251de2bdb3dSTom St Denis #define mmSCL4_SCL_VERT_FILTER_INIT_BOT 0x4757 4252de2bdb3dSTom St Denis #define mmSCL4_SCL_VERT_FILTER_SCALE_RATIO 0x474F 4253de2bdb3dSTom St Denis #define mmSCL4_VIEWPORT_SIZE 0x475D 4254de2bdb3dSTom St Denis #define mmSCL4_VIEWPORT_START 0x475C 4255de2bdb3dSTom St Denis #define mmSCL5_EXT_OVERSCAN_LEFT_RIGHT 0x4A5E 4256de2bdb3dSTom St Denis #define mmSCL5_EXT_OVERSCAN_TOP_BOTTOM 0x4A5F 4257de2bdb3dSTom St Denis #define mmSCL5_SCL_ALU_CONTROL 0x4A54 4258de2bdb3dSTom St Denis #define mmSCL5_SCL_AUTOMATIC_MODE_CONTROL 0x4A47 4259de2bdb3dSTom St Denis #define mmSCL5_SCL_BYPASS_CONTROL 0x4A45 4260de2bdb3dSTom St Denis #define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55 4261de2bdb3dSTom St Denis #define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40 4262de2bdb3dSTom St Denis #define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41 4263de2bdb3dSTom St Denis #define mmSCL5_SCL_CONTROL 0x4A44 4264de2bdb3dSTom St Denis #define mmSCL5_SCL_DEBUG 0x4A6A 4265de2bdb3dSTom St Denis #define mmSCL5_SCL_DEBUG2 0x4A69 4266de2bdb3dSTom St Denis #define mmSCL5_SCL_F_SHARP_CONTROL 0x4A53 4267de2bdb3dSTom St Denis #define mmSCL5_SCL_HORZ_FILTER_CONTROL 0x4A4A 4268de2bdb3dSTom St Denis #define mmSCL5_SCL_HORZ_FILTER_SCALE_RATIO 0x4A4B 4269de2bdb3dSTom St Denis #define mmSCL5_SCL_MANUAL_REPLICATE_CONTROL 0x4A46 4270de2bdb3dSTom St Denis #define mmSCL5_SCL_MODE_CHANGE_DET1 0x4A60 4271de2bdb3dSTom St Denis #define mmSCL5_SCL_MODE_CHANGE_DET2 0x4A61 4272de2bdb3dSTom St Denis #define mmSCL5_SCL_MODE_CHANGE_DET3 0x4A62 4273de2bdb3dSTom St Denis #define mmSCL5_SCL_MODE_CHANGE_MASK 0x4A63 4274de2bdb3dSTom St Denis #define mmSCL5_SCL_TAP_CONTROL 0x4A43 4275de2bdb3dSTom St Denis #define mmSCL5_SCL_TEST_DEBUG_DATA 0x4A6C 4276de2bdb3dSTom St Denis #define mmSCL5_SCL_TEST_DEBUG_INDEX 0x4A6B 4277de2bdb3dSTom St Denis #define mmSCL5_SCL_UPDATE 0x4A51 4278de2bdb3dSTom St Denis #define mmSCL5_SCL_VERT_FILTER_CONTROL 0x4A4E 4279de2bdb3dSTom St Denis #define mmSCL5_SCL_VERT_FILTER_INIT 0x4A50 4280de2bdb3dSTom St Denis #define mmSCL5_SCL_VERT_FILTER_INIT_BOT 0x4A57 4281de2bdb3dSTom St Denis #define mmSCL5_SCL_VERT_FILTER_SCALE_RATIO 0x4A4F 4282de2bdb3dSTom St Denis #define mmSCL5_VIEWPORT_SIZE 0x4A5D 4283de2bdb3dSTom St Denis #define mmSCL5_VIEWPORT_START 0x4A5C 4284de2bdb3dSTom St Denis #define mmSCL_ALU_CONTROL 0x1B54 4285de2bdb3dSTom St Denis #define mmSCL_AUTOMATIC_MODE_CONTROL 0x1B47 4286de2bdb3dSTom St Denis #define mmSCL_BYPASS_CONTROL 0x1B45 4287de2bdb3dSTom St Denis #define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55 4288de2bdb3dSTom St Denis #define mmSCL_COEF_RAM_SELECT 0x1B40 4289de2bdb3dSTom St Denis #define mmSCL_COEF_RAM_TAP_DATA 0x1B41 4290de2bdb3dSTom St Denis #define mmSCL_CONTROL 0x1B44 4291de2bdb3dSTom St Denis #define mmSCL_DEBUG 0x1B6A 4292de2bdb3dSTom St Denis #define mmSCL_DEBUG2 0x1B69 4293de2bdb3dSTom St Denis #define mmSCL_F_SHARP_CONTROL 0x1B53 4294de2bdb3dSTom St Denis #define mmSCL_HORZ_FILTER_CONTROL 0x1B4A 4295de2bdb3dSTom St Denis #define mmSCL_HORZ_FILTER_SCALE_RATIO 0x1B4B 4296de2bdb3dSTom St Denis #define mmSCLK_CGTT_BLK_CTRL_REG 0x0136 4297de2bdb3dSTom St Denis #define mmSCL_MANUAL_REPLICATE_CONTROL 0x1B46 4298de2bdb3dSTom St Denis #define mmSCL_MODE_CHANGE_DET1 0x1B60 4299de2bdb3dSTom St Denis #define mmSCL_MODE_CHANGE_DET2 0x1B61 4300de2bdb3dSTom St Denis #define mmSCL_MODE_CHANGE_DET3 0x1B62 4301de2bdb3dSTom St Denis #define mmSCL_MODE_CHANGE_MASK 0x1B63 4302de2bdb3dSTom St Denis #define mmSCL_TAP_CONTROL 0x1B43 4303de2bdb3dSTom St Denis #define mmSCL_TEST_DEBUG_DATA 0x1B6C 4304de2bdb3dSTom St Denis #define mmSCL_TEST_DEBUG_INDEX 0x1B6B 4305de2bdb3dSTom St Denis #define mmSCL_UPDATE 0x1B51 4306de2bdb3dSTom St Denis #define mmSCL_VERT_FILTER_CONTROL 0x1B4E 4307de2bdb3dSTom St Denis #define mmSCL_VERT_FILTER_INIT 0x1B50 4308de2bdb3dSTom St Denis #define mmSCL_VERT_FILTER_INIT_BOT 0x1B57 4309de2bdb3dSTom St Denis #define mmSCL_VERT_FILTER_SCALE_RATIO 0x1B4F 4310de2bdb3dSTom St Denis #define mmSEQ8_DATA 0x00F1 4311de2bdb3dSTom St Denis #define mmSEQ8_IDX 0x00F1 4312de2bdb3dSTom St Denis #define mmSLAVE_COMM_CMD_REG 0x1624 4313de2bdb3dSTom St Denis #define mmSLAVE_COMM_CNTL_REG 0x1625 4314de2bdb3dSTom St Denis #define mmSLAVE_COMM_DATA_REG1 0x1621 4315de2bdb3dSTom St Denis #define mmSLAVE_COMM_DATA_REG2 0x1622 4316de2bdb3dSTom St Denis #define mmSLAVE_COMM_DATA_REG3 0x1623 4317de2bdb3dSTom St Denis #define mmSYMCLKA_CLOCK_ENABLE 0x0160 4318de2bdb3dSTom St Denis #define mmSYMCLKB_CLOCK_ENABLE 0x0161 4319de2bdb3dSTom St Denis #define mmSYMCLKC_CLOCK_ENABLE 0x0162 4320de2bdb3dSTom St Denis #define mmSYMCLKD_CLOCK_ENABLE 0x0163 4321de2bdb3dSTom St Denis #define mmSYMCLKE_CLOCK_ENABLE 0x0164 4322de2bdb3dSTom St Denis #define mmSYMCLKF_CLOCK_ENABLE 0x0165 4323de2bdb3dSTom St Denis #define mmTMDS_CNTL 0x1C7C 4324de2bdb3dSTom St Denis #define mmTMDS_CONTROL0_FEEDBACK 0x1C7E 4325de2bdb3dSTom St Denis #define mmTMDS_CONTROL_CHAR 0x1C7D 4326de2bdb3dSTom St Denis #define mmTMDS_CTL0_1_GEN_CNTL 0x1C86 4327de2bdb3dSTom St Denis #define mmTMDS_CTL2_3_GEN_CNTL 0x1C87 4328de2bdb3dSTom St Denis #define mmTMDS_CTL_BITS 0x1C83 4329de2bdb3dSTom St Denis #define mmTMDS_DCBALANCER_CONTROL 0x1C84 4330de2bdb3dSTom St Denis #define mmTMDS_DEBUG 0x1C82 4331de2bdb3dSTom St Denis #define mmTMDS_STEREOSYNC_CTL_SEL 0x1C7F 4332de2bdb3dSTom St Denis #define mmTMDS_SYNC_CHAR_PATTERN_0_1 0x1C80 4333de2bdb3dSTom St Denis #define mmTMDS_SYNC_CHAR_PATTERN_2_3 0x1C81 4334de2bdb3dSTom St Denis #define mmUNIPHYAB_TPG_CONTROL 0x1931 4335de2bdb3dSTom St Denis #define mmUNIPHYAB_TPG_SEED 0x1932 4336de2bdb3dSTom St Denis #define mmUNIPHY_ANG_BIST_CNTL 0x198C 4337de2bdb3dSTom St Denis #define mmUNIPHYCD_TPG_CONTROL 0x1933 4338de2bdb3dSTom St Denis #define mmUNIPHYCD_TPG_SEED 0x1934 4339de2bdb3dSTom St Denis #define mmUNIPHY_CHANNEL_XBAR_CNTL 0x198E 4340de2bdb3dSTom St Denis #define mmUNIPHY_DATA_SYNCHRONIZATION 0x198A 4341de2bdb3dSTom St Denis #define mmUNIPHYEF_TPG_CONTROL 0x1935 4342de2bdb3dSTom St Denis #define mmUNIPHYEF_TPG_SEED 0x1936 4343de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_LINKA 0x1908 4344de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_LINKB 0x1909 4345de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_LINKC 0x190F 4346de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_LINKD 0x1910 4347de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_LINKE 0x1913 4348de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_LINKF 0x1914 4349de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_PERIOD 0x190A 4350de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_PSW_AB 0x190E 4351de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_PSW_CD 0x1912 4352de2bdb3dSTom St Denis #define mmUNIPHY_IMPCAL_PSW_EF 0x1916 4353de2bdb3dSTom St Denis #define mmUNIPHY_LINK_CNTL 0x198D 4354de2bdb3dSTom St Denis #define mmUNIPHY_PLL_CONTROL1 0x1986 4355de2bdb3dSTom St Denis #define mmUNIPHY_PLL_CONTROL2 0x1987 4356de2bdb3dSTom St Denis #define mmUNIPHY_PLL_FBDIV 0x1985 4357de2bdb3dSTom St Denis #define mmUNIPHY_PLL_SS_CNTL 0x1989 4358de2bdb3dSTom St Denis #define mmUNIPHY_PLL_SS_STEP_SIZE 0x1988 4359de2bdb3dSTom St Denis #define mmUNIPHY_POWER_CONTROL 0x1984 4360de2bdb3dSTom St Denis #define mmUNIPHY_REG_TEST_OUTPUT 0x198B 4361de2bdb3dSTom St Denis #define mmUNIPHY_SOFT_RESET 0x0166 4362de2bdb3dSTom St Denis #define mmUNIPHY_TX_CONTROL1 0x1980 4363de2bdb3dSTom St Denis #define mmUNIPHY_TX_CONTROL2 0x1981 4364de2bdb3dSTom St Denis #define mmUNIPHY_TX_CONTROL3 0x1982 4365de2bdb3dSTom St Denis #define mmUNIPHY_TX_CONTROL4 0x1983 4366de2bdb3dSTom St Denis #define mmVGA25_PPLL_ANALOG 0x00E4 4367de2bdb3dSTom St Denis #define mmVGA25_PPLL_FB_DIV 0x00DC 4368de2bdb3dSTom St Denis #define mmVGA25_PPLL_POST_DIV 0x00E0 4369de2bdb3dSTom St Denis #define mmVGA25_PPLL_REF_DIV 0x00D8 4370de2bdb3dSTom St Denis #define mmVGA28_PPLL_ANALOG 0x00E5 4371de2bdb3dSTom St Denis #define mmVGA28_PPLL_FB_DIV 0x00DD 4372de2bdb3dSTom St Denis #define mmVGA28_PPLL_POST_DIV 0x00E1 4373de2bdb3dSTom St Denis #define mmVGA28_PPLL_REF_DIV 0x00D9 4374de2bdb3dSTom St Denis #define mmVGA41_PPLL_ANALOG 0x00E6 4375de2bdb3dSTom St Denis #define mmVGA41_PPLL_FB_DIV 0x00DE 4376de2bdb3dSTom St Denis #define mmVGA41_PPLL_POST_DIV 0x00E2 4377de2bdb3dSTom St Denis #define mmVGA41_PPLL_REF_DIV 0x00DA 4378de2bdb3dSTom St Denis #define mmVGA_CACHE_CONTROL 0x00CB 4379de2bdb3dSTom St Denis #define mmVGA_DEBUG_READBACK_DATA 0x00D7 4380de2bdb3dSTom St Denis #define mmVGA_DEBUG_READBACK_INDEX 0x00D6 4381de2bdb3dSTom St Denis #define mmVGA_DISPBUF1_SURFACE_ADDR 0x00C6 4382de2bdb3dSTom St Denis #define mmVGA_DISPBUF2_SURFACE_ADDR 0x00C8 4383de2bdb3dSTom St Denis #define mmVGA_HDP_CONTROL 0x00CA 4384de2bdb3dSTom St Denis #define mmVGA_HW_DEBUG 0x00CF 4385de2bdb3dSTom St Denis #define mmVGA_INTERRUPT_CONTROL 0x00D1 4386de2bdb3dSTom St Denis #define mmVGA_INTERRUPT_STATUS 0x00D3 4387de2bdb3dSTom St Denis #define mmVGA_MAIN_CONTROL 0x00D4 4388de2bdb3dSTom St Denis #define mmVGA_MEMORY_BASE_ADDRESS 0x00C4 4389de2bdb3dSTom St Denis #define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x00C9 4390de2bdb3dSTom St Denis #define mmVGA_MEM_READ_PAGE_ADDR 0x0013 4391de2bdb3dSTom St Denis #define mmVGA_MEM_WRITE_PAGE_ADDR 0x0012 4392de2bdb3dSTom St Denis #define mmVGA_MODE_CONTROL 0x00C2 4393de2bdb3dSTom St Denis #define mmVGA_RENDER_CONTROL 0x00C0 4394de2bdb3dSTom St Denis #define mmVGA_SEQUENCER_RESET_CONTROL 0x00C1 4395de2bdb3dSTom St Denis #define mmVGA_SOURCE_SELECT 0x00FC 4396de2bdb3dSTom St Denis #define mmVGA_STATUS 0x00D0 4397de2bdb3dSTom St Denis #define mmVGA_STATUS_CLEAR 0x00D2 4398de2bdb3dSTom St Denis #define mmVGA_SURFACE_PITCH_SELECT 0x00C3 4399de2bdb3dSTom St Denis #define mmVGA_TEST_CONTROL 0x00D5 4400de2bdb3dSTom St Denis #define mmVGA_TEST_DEBUG_DATA 0x00C7 4401de2bdb3dSTom St Denis #define mmVGA_TEST_DEBUG_INDEX 0x00C5 4402de2bdb3dSTom St Denis #define mmVIEWPORT_SIZE 0x1B5D 4403de2bdb3dSTom St Denis #define mmVIEWPORT_START 0x1B5C 4404de2bdb3dSTom St Denis #define mmXDMA_CLOCK_GATING_CNTL 0x0409 4405de2bdb3dSTom St Denis #define mmXDMA_IF_BIF_STATUS 0x0418 4406de2bdb3dSTom St Denis #define mmXDMA_INTERRUPT 0x0406 4407de2bdb3dSTom St Denis #define mmXDMA_LOCAL_SURFACE_TILING1 0x03F4 4408de2bdb3dSTom St Denis #define mmXDMA_LOCAL_SURFACE_TILING2 0x03F5 4409de2bdb3dSTom St Denis #define mmXDMA_MC_PCIE_CLIENT_CONFIG 0x03E9 4410de2bdb3dSTom St Denis #define mmXDMA_MEM_POWER_CNTL 0x040B 4411de2bdb3dSTom St Denis #define mmXDMA_MSTR_CMD_URGENT_CNTL 0x03F6 4412de2bdb3dSTom St Denis #define mmXDMA_MSTR_CNTL 0x03E0 4413de2bdb3dSTom St Denis #define mmXDMA_MSTR_HEIGHT 0x03E3 4414de2bdb3dSTom St Denis #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR 0x03F1 4415de2bdb3dSTom St Denis #define mmXDMA_MSTR_LOCAL_SURFACE_BASE_ADDR_HIGH 0x03F2 4416de2bdb3dSTom St Denis #define mmXDMA_MSTR_LOCAL_SURFACE_PITCH 0x03F3 4417de2bdb3dSTom St Denis #define mmXDMA_MSTR_MEM_CLIENT_CONFIG 0x03EA 4418de2bdb3dSTom St Denis #define mmXDMA_MSTR_MEM_NACK_STATUS 0x040D 4419de2bdb3dSTom St Denis #define mmXDMA_MSTR_MEM_URGENT_CNTL 0x03F7 4420de2bdb3dSTom St Denis #define mmXDMA_MSTR_PCIE_NACK_STATUS 0x040C 4421de2bdb3dSTom St Denis #define mmXDMA_MSTR_READ_COMMAND 0x03E1 4422de2bdb3dSTom St Denis #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS 0x03E6 4423de2bdb3dSTom St Denis #define mmXDMA_MSTR_REMOTE_GPU_ADDRESS_HIGH 0x03E7 4424de2bdb3dSTom St Denis #define mmXDMA_MSTR_REMOTE_SURFACE_BASE 0x03E4 4425de2bdb3dSTom St Denis #define mmXDMA_MSTR_REMOTE_SURFACE_BASE_HIGH 0x03E5 4426de2bdb3dSTom St Denis #define mmXDMA_MSTR_STATUS 0x03E8 4427de2bdb3dSTom St Denis #define mmXDMA_RBBMIF_RDWR_CNTL 0x040A 4428de2bdb3dSTom St Denis #define mmXDMA_SLV_CNTL 0x03FB 4429de2bdb3dSTom St Denis #define mmXDMA_SLV_FLIP_PENDING 0x0407 4430de2bdb3dSTom St Denis #define mmXDMA_SLV_MEM_CLIENT_CONFIG 0x03FD 4431de2bdb3dSTom St Denis #define mmXDMA_SLV_MEM_NACK_STATUS 0x040F 4432de2bdb3dSTom St Denis #define mmXDMA_SLV_PCIE_NACK_STATUS 0x040E 4433de2bdb3dSTom St Denis #define mmXDMA_SLV_READ_LATENCY_AVE 0x0405 4434de2bdb3dSTom St Denis #define mmXDMA_SLV_READ_LATENCY_MINMAX 0x0404 4435de2bdb3dSTom St Denis #define mmXDMA_SLV_READ_LATENCY_TIMER 0x0412 4436de2bdb3dSTom St Denis #define mmXDMA_SLV_READ_URGENT_CNTL 0x03FF 4437de2bdb3dSTom St Denis #define mmXDMA_SLV_REMOTE_GPU_ADDRESS 0x0402 4438de2bdb3dSTom St Denis #define mmXDMA_SLV_REMOTE_GPU_ADDRESS_HIGH 0x0403 4439de2bdb3dSTom St Denis #define mmXDMA_SLV_SLS_PITCH 0x03FE 4440de2bdb3dSTom St Denis #define mmXDMA_SLV_WB_RATE_CNTL 0x0401 4441de2bdb3dSTom St Denis #define mmXDMA_SLV_WRITE_URGENT_CNTL 0x0400 4442de2bdb3dSTom St Denis #define mmXDMA_TEST_DEBUG_DATA 0x041D 4443de2bdb3dSTom St Denis #define mmXDMA_TEST_DEBUG_INDEX 0x041C 4444de2bdb3dSTom St Denis 4445b00861b9STom St Denis /* Registers that spilled out of sid.h */ 4446b00861b9STom St Denis #define mmDATA_FORMAT 0x1AC0 44476863660dSAlex Deucher #define mmLB0_DATA_FORMAT 0x1AC0 44486863660dSAlex Deucher #define mmLB1_DATA_FORMAT 0x1DC0 44496863660dSAlex Deucher #define mmLB2_DATA_FORMAT 0x40C0 44506863660dSAlex Deucher #define mmLB3_DATA_FORMAT 0x43C0 44516863660dSAlex Deucher #define mmLB4_DATA_FORMAT 0x46C0 44526863660dSAlex Deucher #define mmLB5_DATA_FORMAT 0x49C0 4453b00861b9STom St Denis #define mmDESKTOP_HEIGHT 0x1AC1 44546863660dSAlex Deucher #define mmLB0_DESKTOP_HEIGHT 0x1AC1 44556863660dSAlex Deucher #define mmLB1_DESKTOP_HEIGHT 0x1DC1 44566863660dSAlex Deucher #define mmLB2_DESKTOP_HEIGHT 0x40C1 44576863660dSAlex Deucher #define mmLB3_DESKTOP_HEIGHT 0x43C1 44586863660dSAlex Deucher #define mmLB4_DESKTOP_HEIGHT 0x46C1 44596863660dSAlex Deucher #define mmLB5_DESKTOP_HEIGHT 0x49C1 4460b00861b9STom St Denis #define mmDC_LB_MEMORY_SPLIT 0x1AC3 44616863660dSAlex Deucher #define mmLB0_DC_LB_MEMORY_SPLIT 0x1AC3 44626863660dSAlex Deucher #define mmLB1_DC_LB_MEMORY_SPLIT 0x1DC3 44636863660dSAlex Deucher #define mmLB2_DC_LB_MEMORY_SPLIT 0x40C3 44646863660dSAlex Deucher #define mmLB3_DC_LB_MEMORY_SPLIT 0x43C3 44656863660dSAlex Deucher #define mmLB4_DC_LB_MEMORY_SPLIT 0x46C3 44666863660dSAlex Deucher #define mmLB5_DC_LB_MEMORY_SPLIT 0x49C3 44676863660dSAlex Deucher #define mmDC_LB_MEM_SIZE 0x1AC4 44686863660dSAlex Deucher #define mmLB0_DC_LB_MEM_SIZE 0x1AC4 44696863660dSAlex Deucher #define mmLB1_DC_LB_MEM_SIZE 0x1DC4 44706863660dSAlex Deucher #define mmLB2_DC_LB_MEM_SIZE 0x40C4 44716863660dSAlex Deucher #define mmLB3_DC_LB_MEM_SIZE 0x43C4 44726863660dSAlex Deucher #define mmLB4_DC_LB_MEM_SIZE 0x46C4 44736863660dSAlex Deucher #define mmLB5_DC_LB_MEM_SIZE 0x49C4 4474b00861b9STom St Denis #define mmPRIORITY_A_CNT 0x1AC6 44756863660dSAlex Deucher #define mmLB0_PRIORITY_A_CNT 0x1AC6 44766863660dSAlex Deucher #define mmLB1_PRIORITY_A_CNT 0x1DC6 44776863660dSAlex Deucher #define mmLB2_PRIORITY_A_CNT 0x40C6 44786863660dSAlex Deucher #define mmLB3_PRIORITY_A_CNT 0x43C6 44796863660dSAlex Deucher #define mmLB4_PRIORITY_A_CNT 0x46C6 44806863660dSAlex Deucher #define mmLB5_PRIORITY_A_CNT 0x49C6 4481b00861b9STom St Denis #define mmPRIORITY_B_CNT 0x1AC7 44826863660dSAlex Deucher #define mmLB0_PRIORITY_B_CNT 0x1AC7 44836863660dSAlex Deucher #define mmLB1_PRIORITY_B_CNT 0x1DC7 44846863660dSAlex Deucher #define mmLB2_PRIORITY_B_CNT 0x40C7 44856863660dSAlex Deucher #define mmLB3_PRIORITY_B_CNT 0x43C7 44866863660dSAlex Deucher #define mmLB4_PRIORITY_B_CNT 0x46C7 44876863660dSAlex Deucher #define mmLB5_PRIORITY_B_CNT 0x49C7 4488b00861b9STom St Denis #define mmDPG_PIPE_ARBITRATION_CONTROL3 0x1B32 44896863660dSAlex Deucher #define mmDMIF_PG0_DPG_PIPE_ARBITRATION_CONTROL3 0x1B32 44906863660dSAlex Deucher #define mmDMIF_PG1_DPG_PIPE_ARBITRATION_CONTROL3 0x1E32 44916863660dSAlex Deucher #define mmDMIF_PG2_DPG_PIPE_ARBITRATION_CONTROL3 0x4132 44926863660dSAlex Deucher #define mmDMIF_PG3_DPG_PIPE_ARBITRATION_CONTROL3 0x4432 44936863660dSAlex Deucher #define mmDMIF_PG4_DPG_PIPE_ARBITRATION_CONTROL3 0x4732 44946863660dSAlex Deucher #define mmDMIF_PG5_DPG_PIPE_ARBITRATION_CONTROL3 0x4A32 4495b00861b9STom St Denis #define mmINT_MASK 0x1AD0 44966863660dSAlex Deucher #define mmLB0_INT_MASK 0x1AD0 44976863660dSAlex Deucher #define mmLB1_INT_MASK 0x1DD0 44986863660dSAlex Deucher #define mmLB2_INT_MASK 0x40D0 44996863660dSAlex Deucher #define mmLB3_INT_MASK 0x43D0 45006863660dSAlex Deucher #define mmLB4_INT_MASK 0x46D0 45016863660dSAlex Deucher #define mmLB5_INT_MASK 0x49D0 4502b00861b9STom St Denis #define mmVLINE_STATUS 0x1AEE 45036863660dSAlex Deucher #define mmLB0_VLINE_STATUS 0x1AEE 45046863660dSAlex Deucher #define mmLB1_VLINE_STATUS 0x1DEE 45056863660dSAlex Deucher #define mmLB2_VLINE_STATUS 0x40EE 45066863660dSAlex Deucher #define mmLB3_VLINE_STATUS 0x43EE 45076863660dSAlex Deucher #define mmLB4_VLINE_STATUS 0x46EE 45086863660dSAlex Deucher #define mmLB5_VLINE_STATUS 0x49EE 4509b00861b9STom St Denis #define mmVBLANK_STATUS 0x1AEF 45106863660dSAlex Deucher #define mmLB0_VBLANK_STATUS 0x1AEF 45116863660dSAlex Deucher #define mmLB1_VBLANK_STATUS 0x1DEF 45126863660dSAlex Deucher #define mmLB2_VBLANK_STATUS 0x40EF 45136863660dSAlex Deucher #define mmLB3_VBLANK_STATUS 0x43EF 45146863660dSAlex Deucher #define mmLB4_VBLANK_STATUS 0x46EF 45156863660dSAlex Deucher #define mmLB5_VBLANK_STATUS 0x49EF 4516b00861b9STom St Denis 45176863660dSAlex Deucher #define mmSCL_HORZ_FILTER_INIT_RGB_LUMA 0x1B4C 45186863660dSAlex Deucher #define mmSCL0_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x1B4C 45196863660dSAlex Deucher #define mmSCL1_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x1E4C 45206863660dSAlex Deucher #define mmSCL2_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x414C 45216863660dSAlex Deucher #define mmSCL3_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x444C 45226863660dSAlex Deucher #define mmSCL4_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x474C 45236863660dSAlex Deucher #define mmSCL5_SCL_HORZ_FILTER_INIT_RGB_LUMA 0x4A4C 45246863660dSAlex Deucher 45256863660dSAlex Deucher #define mmSCL_HORZ_FILTER_INIT_CHROMA 0x1B4D 45266863660dSAlex Deucher #define mmSCL0_SCL_HORZ_FILTER_INIT_CHROMA 0x1B4D 45276863660dSAlex Deucher #define mmSCL1_SCL_HORZ_FILTER_INIT_CHROMA 0x1E4D 45286863660dSAlex Deucher #define mmSCL2_SCL_HORZ_FILTER_INIT_CHROMA 0x414D 45296863660dSAlex Deucher #define mmSCL3_SCL_HORZ_FILTER_INIT_CHROMA 0x444D 45306863660dSAlex Deucher #define mmSCL4_SCL_HORZ_FILTER_INIT_CHROMA 0x474D 45316863660dSAlex Deucher #define mmSCL5_SCL_HORZ_FILTER_INIT_CHROMA 0x4A4D 4532b00861b9STom St Denis 4533de2bdb3dSTom St Denis #endif 4534