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/openbmc/linux/arch/x86/include/asm/
H A Dbios_ebda.h8 * Returns physical address of EBDA. Returns 0 if there is no EBDA.
14 * 4K EBDA area at 0x40E. in get_bios_ebda()
16 unsigned int address = *(unsigned short *)phys_to_virt(0x40E); in get_bios_ebda()
18 return address; /* 0 means none */ in get_bios_ebda()
/openbmc/linux/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sdm660-venus.yaml113 reg = <0x0cc00000 0xff000>;
119 interconnects = <&gnoc 0 &mnoc 13>,
123 iommus = <&mmss_smmu 0x400>,
124 <&mmss_smmu 0x401>,
125 <&mmss_smmu 0x40a>,
126 <&mmss_smmu 0x407>,
127 <&mmss_smmu 0x40e>,
128 <&mmss_smmu 0x40f>,
129 <&mmss_smmu 0x408>,
130 <&mmss_smmu 0x409>,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/
H A Doss_2_0_d.h27 #define mmIH_VMID_0_LUT 0xf50
28 #define mmIH_VMID_1_LUT 0xf51
29 #define mmIH_VMID_2_LUT 0xf52
30 #define mmIH_VMID_3_LUT 0xf53
31 #define mmIH_VMID_4_LUT 0xf54
32 #define mmIH_VMID_5_LUT 0xf55
33 #define mmIH_VMID_6_LUT 0xf56
34 #define mmIH_VMID_7_LUT 0xf57
35 #define mmIH_VMID_8_LUT 0xf58
36 #define mmIH_VMID_9_LUT 0xf59
[all …]
/openbmc/linux/arch/x86/boot/compressed/
H A Dpgtable_64.c9 #define BIOS_START_MIN 0x20000U /* 128K, less than this is insane */
10 #define BIOS_START_MAX 0x9f000U /* 640K, absolute maximum */
36 unsigned long bios_start = 0, ebda_start = 0; in find_trampoline_placement()
55 ebda_start = *(unsigned short *)0x40e << 4; in find_trampoline_placement()
56 bios_start = *(unsigned short *)0x413 << 10; in find_trampoline_placement()
68 for (i = boot_params->e820_entries - 1; i >= 0; i--) { in find_trampoline_placement()
126 native_cpuid_eax(0) >= 7 && in configure_5level_paging()
149 memset(trampoline_32bit, 0, TRAMPOLINE_32BIT_SIZE); in configure_5level_paging()
/openbmc/u-boot/drivers/net/
H A Dmtk_eth.h13 #define PDMA_BASE 0x0800
14 #define GDMA1_BASE 0x0500
15 #define GDMA2_BASE 0x1500
16 #define GMAC_BASE 0x10000
20 #define ETHSYS_SYSCFG0_REG 0x14
22 #define SYSCFG0_GE_MODE_M 0x3
24 #define ETHSYS_CLKCFG0_REG 0x2c
28 #define GE_MODE_RGMII 0
36 #define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
37 #define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
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/openbmc/linux/include/linux/mfd/mt6331/
H A Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
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/openbmc/linux/drivers/leds/
H A Dleds-mt6323.c24 #define RG_VWLED_1M_CK_PDN BIT(0)
41 #define ISINK_CON(r, i) (r + 0x8 * (i))
44 #define ISINK_DIM_DUTY_MASK (0x1f << 8)
48 #define ISINK_DIM_FSEL_MASK (0xffff)
53 #define ISINK_CH_STEP_MASK (0x7 << 12)
55 #define ISINK_SFSTR0_TC_MASK (0x3 << 1)
57 #define ISINK_SFSTR0_EN_MASK BIT(0)
58 #define ISINK_SFSTR0_EN BIT(0)
84 * @top_ckpdn: Offset to ISINK_CKPDN[0..x] registers
86 * @top_ckcon: Offset to ISINK_CKCON[0..x] registers
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-core.c17 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write()
18 u32 mask = 0xff; in cx18_av_write()
24 return 0; in cx18_av_write()
29 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write_expect()
33 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); in cx18_av_write_expect()
36 return 0; in cx18_av_write_expect()
41 cx18_write_reg(cx, value, 0xc40000 + addr); in cx18_av_write4()
42 return 0; in cx18_av_write4()
48 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); in cx18_av_write4_expect()
49 return 0; in cx18_av_write4_expect()
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/openbmc/linux/drivers/gpu/drm/tegra/
H A Ddc.h176 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
177 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
179 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
180 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
181 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
182 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
183 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
184 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
185 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
186 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
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/openbmc/linux/arch/x86/kernel/
H A Dmpparse.c41 int sum = 0; in mpf_checksum()
46 return sum & 0xFF; in mpf_checksum()
69 str[6] = 0; in mpc_oem_bus_info()
88 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) { in MP_bus_info()
92 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) { in MP_bus_info()
96 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) { in MP_bus_info()
144 mpc->signature[0], mpc->signature[1], in smp_check_mpc()
146 return 0; in smp_check_mpc()
150 return 0; in smp_check_mpc()
152 if (mpc->spec != 0x01 && mpc->spec != 0x04) { in smp_check_mpc()
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/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dstm32f746-pinfunc.h4 #define STM32F746_PA0_FUNC_GPIO 0x0
5 #define STM32F746_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32F746_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32F746_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32F746_PA0_FUNC_USART2_CTS 0x8
9 #define STM32F746_PA0_FUNC_UART4_TX 0x9
10 #define STM32F746_PA0_FUNC_SAI2_SD_B 0xb
11 #define STM32F746_PA0_FUNC_ETH_MII_CRS 0xc
12 #define STM32F746_PA0_FUNC_EVENTOUT 0x10
13 #define STM32F746_PA0_FUNC_ANALOG 0x11
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H A Dstm32h7-pinfunc.h4 #define STM32H7_PA0_FUNC_GPIO 0x0
5 #define STM32H7_PA0_FUNC_TIM2_CH1_TIM2_ETR 0x2
6 #define STM32H7_PA0_FUNC_TIM5_CH1 0x3
7 #define STM32H7_PA0_FUNC_TIM8_ETR 0x4
8 #define STM32H7_PA0_FUNC_TIM15_BKIN 0x5
9 #define STM32H7_PA0_FUNC_USART2_CTS_NSS 0x8
10 #define STM32H7_PA0_FUNC_UART4_TX 0x9
11 #define STM32H7_PA0_FUNC_SDMMC2_CMD 0xa
12 #define STM32H7_PA0_FUNC_SAI2_SD_B 0xb
13 #define STM32H7_PA0_FUNC_ETH_MII_CRS 0xc
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/openbmc/linux/drivers/net/dsa/
H A Dmt7530.h12 #define MT7530_ALL_MEMBERS 0xff
18 ID_MT7530 = 0,
26 #define TRGMII_BASE(x) (0x10000 + (x))
29 #define ETHSYS_CLKCFG0 0x2c
32 #define SYSC_REG_RSTCTRL 0x34
36 #define MT753X_AGC 0xc
40 #define MT7530_MFC 0x10
41 #define BC_FFP(x) (((x) & 0xff) << 24)
42 #define BC_FFP_MASK BC_FFP(~0)
43 #define UNM_FFP(x) (((x) & 0xff) << 16)
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/openbmc/linux/include/linux/mfd/mt6357/
H A Dregisters.h10 #define MT6357_TOP0_ID 0x0
11 #define MT6357_TOP0_REV0 0x2
12 #define MT6357_TOP0_DSN_DBI 0x4
13 #define MT6357_TOP0_DSN_DXI 0x6
14 #define MT6357_HWCID 0x8
15 #define MT6357_SWCID 0xa
16 #define MT6357_PONSTS 0xc
17 #define MT6357_POFFSTS 0xe
18 #define MT6357_PSTSCTL 0x10
19 #define MT6357_PG_DEB_STS0 0x12
[all …]
/openbmc/qemu/target/arm/
H A Dinternals.h35 #define BANK_USRSYS 0
78 FIELD(V7M_CONTROL, NPRIV, 0, 1)
84 FIELD(V7M_EXCRET, ES, 0, 1)
94 #define EXC_RETURN_MIN_MAGIC 0xff000000
98 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
101 FIELD(DBGWCR, E, 0, 1)
177 #define MDCR_HPMN (0x1fU)
184 #define TTBCR_N (7U << 0) /* TTBCR.EAE==0 */
185 #define TTBCR_T0SZ (7U << 0) /* TTBCR.EAE==1 */
200 FIELD(VTCR, T0SZ, 0, 6)
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm630.dtsi33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm2200.h14 #define WM2200_CLKSRC_MCLK1 0
19 #define WM2200_FLL_SRC_MCLK1 0
26 #define WM2200_SOFTWARE_RESET 0x00
27 #define WM2200_DEVICE_REVISION 0x01
28 #define WM2200_TONE_GENERATOR_1 0x0B
29 #define WM2200_CLOCKING_3 0x102
30 #define WM2200_CLOCKING_4 0x103
31 #define WM2200_FLL_CONTROL_1 0x111
32 #define WM2200_FLL_CONTROL_2 0x112
33 #define WM2200_FLL_CONTROL_3 0x113
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmDCFEV0_PG_CONFIG 0x2db
[all …]
H A Ddce_10_0_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
[all …]
H A Ddce_11_2_d.h27 #define mmPIPE0_PG_CONFIG 0x2c0
28 #define mmPIPE0_PG_ENABLE 0x2c1
29 #define mmPIPE0_PG_STATUS 0x2c2
30 #define mmPIPE1_PG_CONFIG 0x2c3
31 #define mmPIPE1_PG_ENABLE 0x2c4
32 #define mmPIPE1_PG_STATUS 0x2c5
33 #define mmPIPE2_PG_CONFIG 0x2c6
34 #define mmPIPE2_PG_ENABLE 0x2c7
35 #define mmPIPE2_PG_STATUS 0x2c8
36 #define mmPIPE3_PG_CONFIG 0x2c9
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/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-core.c45 #define CX25840_VID_INT_STAT_REG 0x410
46 #define CX25840_VID_INT_STAT_BITS 0x0000ffff
47 #define CX25840_VID_INT_MASK_BITS 0xffff0000
49 #define CX25840_VID_INT_MASK_REG 0x412
51 #define CX23885_AUD_MC_INT_MASK_REG 0x80c
52 #define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
53 #define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
56 #define CX25840_AUD_INT_CTRL_REG 0x812
57 #define CX25840_AUD_INT_STAT_REG 0x813
59 #define CX23885_PIN_CTRL_IRQ_REG 0x123
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dcore.h22 #define MASKBYTE0 0xff
23 #define MASKBYTE1 0xff00
24 #define MASKBYTE2 0xff0000
25 #define MASKBYTE3 0xff000000
26 #define MASKBYTE4 0xff00000000ULL
27 #define MASKHWORD 0xffff0000
28 #define MASKLWORD 0x0000ffff
29 #define MASKDWORD 0xffffffff
30 #define RFREG_MASK 0xfffff
31 #define INV_RF_DATA 0xffffffff
[all …]
H A Drtw8852a_rfk.c29 static const u32 rtw8852a_backup_bb_regs[] = {0x2344, 0x58f0, 0x78f0};
30 static const u32 rtw8852a_backup_rf_regs[] = {0xef, 0xde, 0x0, 0x1e, 0x2, 0x85, 0x90, 0x5};
38 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_backup_bb_reg()
53 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_backup_rf_reg()
68 for (i = 0; i < BACKUP_BB_REGS_NR; i++) { in _rfk_restore_bb_reg()
82 for (i = 0; i < BACKUP_RF_REGS_NR; i++) { in _rfk_restore_rf_reg()
98 for (path = 0; path < RF_PATH_MAX; path++) { in _wait_rx_mode()
103 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
118 "[DACK]S0 ADC_DCK ic = 0x%x, qc = 0x%x\n", in _dack_dump()
119 dack->addck_d[0][0], dack->addck_d[0][1]); in _dack_dump()
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dtranslate.c64 for (i = 0; i < 16; i++) { in arm_translate_init()
86 case 0: case 1: in asimd_imm_const()
105 imm = (imm << 8) | 0xff; in asimd_imm_const()
108 imm = (imm << 16) | 0xffff; in asimd_imm_const()
116 uint64_t imm64 = 0; in asimd_imm_const()
119 for (n = 0; n < 8; n++) { in asimd_imm_const()
121 imm64 |= (0xffULL << (n * 8)); in asimd_imm_const()
131 uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; in asimd_imm_const()
132 if (imm & 0x80) { in asimd_imm_const()
133 imm64 |= 0x8000000000000000ULL; in asimd_imm_const()
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