Lines Matching +full:0 +full:x40e
64 for (i = 0; i < 16; i++) { in arm_translate_init()
86 case 0: case 1: in asimd_imm_const()
105 imm = (imm << 8) | 0xff; in asimd_imm_const()
108 imm = (imm << 16) | 0xffff; in asimd_imm_const()
116 uint64_t imm64 = 0; in asimd_imm_const()
119 for (n = 0; n < 8; n++) { in asimd_imm_const()
121 imm64 |= (0xffULL << (n * 8)); in asimd_imm_const()
131 uint64_t imm64 = (uint64_t)(imm & 0x3f) << 48; in asimd_imm_const()
132 if (imm & 0x80) { in asimd_imm_const()
133 imm64 |= 0x8000000000000000ULL; in asimd_imm_const()
135 if (imm & 0x40) { in asimd_imm_const()
136 imm64 |= 0x3fc0000000000000ULL; in asimd_imm_const()
138 imm64 |= 0x4000000000000000ULL; in asimd_imm_const()
142 imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19) in asimd_imm_const()
143 | ((imm & 0x40) ? (0x1f << 25) : (1 << 30)); in asimd_imm_const()
165 ISSNone = 0,
166 ISSRegMask = 0x1f,
217 syn = syn_data_abort_with_iss(0, sas, sse, srt, 0, is_acqrel, in disas_set_da_iss()
218 0, 0, 0, is_write, 0, is_16bit); in disas_set_da_iss()
276 gen_pc_plus_diff(s, var, jmp_diff(s, 0)); in load_reg_var()
308 /* In Thumb mode, we must ignore bit 0. in store_reg()
309 * In ARM mode, for ARMv4 and ARMv5, it is UNPREDICTABLE if bits [1:0] in store_reg()
310 * are not 0b00, but for ARMv6 and above, we must ignore bits [1:0]. in store_reg()
311 * We choose to ignore [1:0] in ARM mode for all architecture versions. in store_reg()
317 /* For M-profile SP bits [1:0] are always zero */ in store_reg()
403 store_cpu_field_constant(0, condexec_bits); in clear_eci_state()
404 s->eci = 0; in clear_eci_state()
425 TCGv_i32 mask = tcg_constant_i32(0x00ff00ff); in gen_rev16()
440 tmp = (t0 ^ t1) & 0x8000;
441 t0 &= ~0x8000;
442 t1 &= ~0x8000;
450 tcg_gen_andi_i32(tmp, tmp, 0x8000); in gen_add16()
451 tcg_gen_andi_i32(t0, t0, ~0x8000); in gen_add16()
452 tcg_gen_andi_i32(t1, t1, ~0x8000); in gen_add16()
483 tcg_gen_movi_i32(tmp, 0); in gen_add_CC()
497 tcg_gen_movi_i32(tmp, 0); in gen_adc_CC()
544 TCGv_i32 zero = tcg_constant_i32(0); \
545 tcg_gen_andi_i32(tmp1, t1, 0x1f); \
547 tcg_gen_andi_i32(tmp1, t1, 0xe0); \
558 tcg_gen_andi_i32(tmp1, t1, 0xff); in GEN_SHIFT()
568 /* Shift by immediate. Includes special handling for shift == 0. */
573 case 0: /* LSL */ in gen_arm_shift_im()
574 if (shift != 0) { in gen_arm_shift_im()
581 if (shift == 0) { in gen_arm_shift_im()
585 tcg_gen_movi_i32(var, 0); in gen_arm_shift_im()
593 if (shift == 0) in gen_arm_shift_im()
602 if (shift != 0) { in gen_arm_shift_im()
610 shifter_out_im(var, 0); in gen_arm_shift_im()
622 case 0: gen_helper_shl_cc(var, tcg_env, var, shift); break; in gen_arm_shift_reg()
629 case 0: in gen_arm_shift_reg()
638 case 3: tcg_gen_andi_i32(shift, shift, 0x1f); in gen_arm_shift_reg()
654 case 0: /* eq: Z */ in arm_test_cc()
688 case 10: /* ge: N == V -> N ^ V == 0 */ in arm_test_cc()
689 case 11: /* lt: N != V -> N ^ V != 0 */ in arm_test_cc()
690 /* Since we're only interested in the sign bit, == 0 is >= 0. */ in arm_test_cc()
716 fprintf(stderr, "Bad condition code 0x%x\n", cc); in arm_test_cc()
731 tcg_gen_brcondi_i32(cmp->cond, cmp->value, 0, label); in arm_jump_cc()
822 tcg_gen_exit_tb(NULL, 0); in gen_bx_excret_final_code()
850 * so we know that condexec == 0 (already set at the top of the TB) in gen_bxns()
899 #define IS_USER_ONLY 0
905 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32 in pow2_align()
1022 gen_update_pc(s, 0); in gen_hvc()
1039 gen_update_pc(s, 0); in gen_smc()
1048 gen_update_pc(s, 0); in gen_exception_internal_insn()
1106 gen_update_pc(s, 0); in gen_exception_bkpt_insn()
1114 gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); in unallocated_encoding()
1130 * Secondly, "HLT 0x3C" is a T32 semihosting trap instruction, in gen_hlt()
1131 * and "HLT 0xF000" is an A32 semihosting syscall. These traps in gen_hlt()
1138 if (semihosting_enabled(s->current_el == 0) && in gen_hlt()
1139 (imm == (s->thumb ? 0x3c : 0xf000))) { in gen_hlt()
1157 * where 0 is the least significant end of the register.
1179 return neon_element_offset(reg, 0, MO_64); in vfp_reg_offset()
1434 rd = (insn >> 16) & 0xf; in gen_iwmmxt_address()
1437 offset = (insn & 0xff) << ((insn >> 7) & 2); in gen_iwmmxt_address()
1458 return 0; in gen_iwmmxt_address()
1463 int rd = (insn >> 0) & 0xf; in gen_iwmmxt_shift()
1479 return 0; in gen_iwmmxt_shift()
1491 if ((insn & 0x0e000e00) == 0x0c000000) { in disas_iwmmxt_insn()
1492 if ((insn & 0x0fe00ff0) == 0x0c400000) { in disas_iwmmxt_insn()
1493 wrd = insn & 0xf; in disas_iwmmxt_insn()
1494 rdlo = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1495 rdhi = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1505 return 0; in disas_iwmmxt_insn()
1508 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1514 if ((insn >> 28) == 0xf) { /* WLDRW wCx */ in disas_iwmmxt_insn()
1523 i = 0; in disas_iwmmxt_insn()
1542 if ((insn >> 28) == 0xf) { /* WSTRW wCx */ in disas_iwmmxt_insn()
1566 return 0; in disas_iwmmxt_insn()
1569 if ((insn & 0x0f000000) != 0x0e000000) in disas_iwmmxt_insn()
1572 switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { in disas_iwmmxt_insn()
1573 case 0x000: /* WOR */ in disas_iwmmxt_insn()
1574 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1575 rd0 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1576 rd1 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1584 case 0x011: /* TMCR */ in disas_iwmmxt_insn()
1585 if (insn & 0xf) in disas_iwmmxt_insn()
1587 rd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1588 wrd = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1614 case 0x100: /* WXOR */ in disas_iwmmxt_insn()
1615 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1616 rd0 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1617 rd1 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1625 case 0x111: /* TMRC */ in disas_iwmmxt_insn()
1626 if (insn & 0xf) in disas_iwmmxt_insn()
1628 rd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1629 wrd = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1633 case 0x300: /* WANDN */ in disas_iwmmxt_insn()
1634 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1635 rd0 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1636 rd1 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1645 case 0x200: /* WAND */ in disas_iwmmxt_insn()
1646 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1647 rd0 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1648 rd1 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1656 case 0x810: case 0xa10: /* WMADD */ in disas_iwmmxt_insn()
1657 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1658 rd0 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1659 rd1 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1668 case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ in disas_iwmmxt_insn()
1669 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1670 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1671 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1674 case 0: in disas_iwmmxt_insn()
1690 case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ in disas_iwmmxt_insn()
1691 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1692 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1693 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1696 case 0: in disas_iwmmxt_insn()
1712 case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ in disas_iwmmxt_insn()
1713 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1714 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1715 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1726 case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ in disas_iwmmxt_insn()
1727 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1728 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1729 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1745 case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ in disas_iwmmxt_insn()
1746 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1747 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1748 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1761 case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ in disas_iwmmxt_insn()
1762 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1763 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1764 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1767 case 0: in disas_iwmmxt_insn()
1783 case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ in disas_iwmmxt_insn()
1784 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1785 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1786 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1803 case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ in disas_iwmmxt_insn()
1804 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1805 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1806 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
1815 case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ in disas_iwmmxt_insn()
1818 rd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1819 wrd = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1823 case 0: in disas_iwmmxt_insn()
1824 tmp2 = tcg_constant_i32(0xff); in disas_iwmmxt_insn()
1828 tmp2 = tcg_constant_i32(0xffff); in disas_iwmmxt_insn()
1832 tmp2 = tcg_constant_i32(0xffffffff); in disas_iwmmxt_insn()
1842 case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ in disas_iwmmxt_insn()
1843 rd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1844 wrd = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1850 case 0: in disas_iwmmxt_insn()
1856 tcg_gen_andi_i32(tmp, tmp, 0xff); in disas_iwmmxt_insn()
1865 tcg_gen_andi_i32(tmp, tmp, 0xffff); in disas_iwmmxt_insn()
1875 case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ in disas_iwmmxt_insn()
1876 if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3) in disas_iwmmxt_insn()
1880 case 0: in disas_iwmmxt_insn()
1881 tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); in disas_iwmmxt_insn()
1893 case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ in disas_iwmmxt_insn()
1896 rd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1897 wrd = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1900 case 0: in disas_iwmmxt_insn()
1913 case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ in disas_iwmmxt_insn()
1914 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) in disas_iwmmxt_insn()
1920 case 0: in disas_iwmmxt_insn()
1921 for (i = 0; i < 7; i ++) { in disas_iwmmxt_insn()
1927 for (i = 0; i < 3; i ++) { in disas_iwmmxt_insn()
1939 case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ in disas_iwmmxt_insn()
1940 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1941 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1944 case 0: in disas_iwmmxt_insn()
1959 case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ in disas_iwmmxt_insn()
1960 if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) in disas_iwmmxt_insn()
1966 case 0: in disas_iwmmxt_insn()
1967 for (i = 0; i < 7; i ++) { in disas_iwmmxt_insn()
1973 for (i = 0; i < 3; i ++) { in disas_iwmmxt_insn()
1985 case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ in disas_iwmmxt_insn()
1986 rd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
1987 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
1988 if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3) in disas_iwmmxt_insn()
1993 case 0: in disas_iwmmxt_insn()
2005 case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ in disas_iwmmxt_insn()
2006 case 0x906: case 0xb06: case 0xd06: case 0xf06: in disas_iwmmxt_insn()
2007 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2008 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2009 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2012 case 0: in disas_iwmmxt_insn()
2037 case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ in disas_iwmmxt_insn()
2038 case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: in disas_iwmmxt_insn()
2039 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2040 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2043 case 0: in disas_iwmmxt_insn()
2068 case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ in disas_iwmmxt_insn()
2069 case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: in disas_iwmmxt_insn()
2070 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2071 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2074 case 0: in disas_iwmmxt_insn()
2099 case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ in disas_iwmmxt_insn()
2100 case 0x214: case 0x614: case 0xa14: case 0xe14: in disas_iwmmxt_insn()
2101 if (((insn >> 22) & 3) == 0) in disas_iwmmxt_insn()
2103 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2104 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2107 if (gen_iwmmxt_shift(insn, 0xff, tmp)) { in disas_iwmmxt_insn()
2125 case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ in disas_iwmmxt_insn()
2126 case 0x014: case 0x414: case 0x814: case 0xc14: in disas_iwmmxt_insn()
2127 if (((insn >> 22) & 3) == 0) in disas_iwmmxt_insn()
2129 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2130 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2133 if (gen_iwmmxt_shift(insn, 0xff, tmp)) { in disas_iwmmxt_insn()
2151 case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ in disas_iwmmxt_insn()
2152 case 0x114: case 0x514: case 0x914: case 0xd14: in disas_iwmmxt_insn()
2153 if (((insn >> 22) & 3) == 0) in disas_iwmmxt_insn()
2155 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2156 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2159 if (gen_iwmmxt_shift(insn, 0xff, tmp)) { in disas_iwmmxt_insn()
2177 case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ in disas_iwmmxt_insn()
2178 case 0x314: case 0x714: case 0xb14: case 0xf14: in disas_iwmmxt_insn()
2179 if (((insn >> 22) & 3) == 0) in disas_iwmmxt_insn()
2181 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2182 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2187 if (gen_iwmmxt_shift(insn, 0xf, tmp)) { in disas_iwmmxt_insn()
2193 if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { in disas_iwmmxt_insn()
2199 if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { in disas_iwmmxt_insn()
2209 case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ in disas_iwmmxt_insn()
2210 case 0x916: case 0xb16: case 0xd16: case 0xf16: in disas_iwmmxt_insn()
2211 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2212 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2213 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2216 case 0: in disas_iwmmxt_insn()
2240 case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ in disas_iwmmxt_insn()
2241 case 0x816: case 0xa16: case 0xc16: case 0xe16: in disas_iwmmxt_insn()
2242 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2243 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2244 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2247 case 0: in disas_iwmmxt_insn()
2271 case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ in disas_iwmmxt_insn()
2272 case 0x402: case 0x502: case 0x602: case 0x702: in disas_iwmmxt_insn()
2273 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2274 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2275 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2283 case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ in disas_iwmmxt_insn()
2284 case 0x41a: case 0x51a: case 0x61a: case 0x71a: in disas_iwmmxt_insn()
2285 case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: in disas_iwmmxt_insn()
2286 case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: in disas_iwmmxt_insn()
2287 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2288 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2289 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2291 switch ((insn >> 20) & 0xf) { in disas_iwmmxt_insn()
2292 case 0x0: in disas_iwmmxt_insn()
2295 case 0x1: in disas_iwmmxt_insn()
2298 case 0x3: in disas_iwmmxt_insn()
2301 case 0x4: in disas_iwmmxt_insn()
2304 case 0x5: in disas_iwmmxt_insn()
2307 case 0x7: in disas_iwmmxt_insn()
2310 case 0x8: in disas_iwmmxt_insn()
2313 case 0x9: in disas_iwmmxt_insn()
2316 case 0xb: in disas_iwmmxt_insn()
2326 case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ in disas_iwmmxt_insn()
2327 case 0x41e: case 0x51e: case 0x61e: case 0x71e: in disas_iwmmxt_insn()
2328 case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: in disas_iwmmxt_insn()
2329 case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: in disas_iwmmxt_insn()
2330 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2331 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2333 tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); in disas_iwmmxt_insn()
2339 case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ in disas_iwmmxt_insn()
2340 case 0x418: case 0x518: case 0x618: case 0x718: in disas_iwmmxt_insn()
2341 case 0x818: case 0x918: case 0xa18: case 0xb18: in disas_iwmmxt_insn()
2342 case 0xc18: case 0xd18: case 0xe18: case 0xf18: in disas_iwmmxt_insn()
2343 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2344 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2345 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2347 switch ((insn >> 20) & 0xf) { in disas_iwmmxt_insn()
2348 case 0x0: in disas_iwmmxt_insn()
2351 case 0x1: in disas_iwmmxt_insn()
2354 case 0x3: in disas_iwmmxt_insn()
2357 case 0x4: in disas_iwmmxt_insn()
2360 case 0x5: in disas_iwmmxt_insn()
2363 case 0x7: in disas_iwmmxt_insn()
2366 case 0x8: in disas_iwmmxt_insn()
2369 case 0x9: in disas_iwmmxt_insn()
2372 case 0xb: in disas_iwmmxt_insn()
2382 case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ in disas_iwmmxt_insn()
2383 case 0x408: case 0x508: case 0x608: case 0x708: in disas_iwmmxt_insn()
2384 case 0x808: case 0x908: case 0xa08: case 0xb08: in disas_iwmmxt_insn()
2385 case 0xc08: case 0xd08: case 0xe08: case 0xf08: in disas_iwmmxt_insn()
2386 if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0) in disas_iwmmxt_insn()
2388 wrd = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2389 rd0 = (insn >> 16) & 0xf; in disas_iwmmxt_insn()
2390 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2416 case 0x201: case 0x203: case 0x205: case 0x207: in disas_iwmmxt_insn()
2417 case 0x209: case 0x20b: case 0x20d: case 0x20f: in disas_iwmmxt_insn()
2418 case 0x211: case 0x213: case 0x215: case 0x217: in disas_iwmmxt_insn()
2419 case 0x219: case 0x21b: case 0x21d: case 0x21f: in disas_iwmmxt_insn()
2420 wrd = (insn >> 5) & 0xf; in disas_iwmmxt_insn()
2421 rd0 = (insn >> 12) & 0xf; in disas_iwmmxt_insn()
2422 rd1 = (insn >> 0) & 0xf; in disas_iwmmxt_insn()
2423 if (rd0 == 0xf || rd1 == 0xf) in disas_iwmmxt_insn()
2428 switch ((insn >> 16) & 0xf) { in disas_iwmmxt_insn()
2429 case 0x0: /* TMIA */ in disas_iwmmxt_insn()
2432 case 0x8: /* TMIAPH */ in disas_iwmmxt_insn()
2435 case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ in disas_iwmmxt_insn()
2452 return 0; in disas_iwmmxt_insn()
2462 if ((insn & 0x0ff00f10) == 0x0e200010) { in disas_dsp_insn()
2464 rd0 = (insn >> 12) & 0xf; in disas_dsp_insn()
2465 rd1 = insn & 0xf; in disas_dsp_insn()
2468 if (acc != 0) in disas_dsp_insn()
2473 switch ((insn >> 16) & 0xf) { in disas_dsp_insn()
2474 case 0x0: /* MIA */ in disas_dsp_insn()
2477 case 0x8: /* MIAPH */ in disas_dsp_insn()
2480 case 0xc: /* MIABB */ in disas_dsp_insn()
2481 case 0xd: /* MIABT */ in disas_dsp_insn()
2482 case 0xe: /* MIATB */ in disas_dsp_insn()
2483 case 0xf: /* MIATT */ in disas_dsp_insn()
2495 return 0; in disas_dsp_insn()
2498 if ((insn & 0x0fe00ff8) == 0x0c400000) { in disas_dsp_insn()
2500 rdhi = (insn >> 16) & 0xf; in disas_dsp_insn()
2501 rdlo = (insn >> 12) & 0xf; in disas_dsp_insn()
2504 if (acc != 0) in disas_dsp_insn()
2516 return 0; in disas_dsp_insn()
2603 gen_jmp_tb(s, diff, 0); in gen_jmp()
2622 uint32_t mask = 0; in msr_mask()
2624 if (flags & (1 << 0)) { in msr_mask()
2625 mask |= 0xff; in msr_mask()
2628 mask |= 0xff00; in msr_mask()
2631 mask |= 0xff0000; in msr_mask()
2634 mask |= 0xff000000; in msr_mask()
2670 return 0; in gen_set_psr()
2722 case 0xe: /* SPSR_fiq */ in msr_banked_access_decode()
2725 case 0x10: /* SPSR_irq */ in msr_banked_access_decode()
2728 case 0x12: /* SPSR_svc */ in msr_banked_access_decode()
2731 case 0x14: /* SPSR_abt */ in msr_banked_access_decode()
2734 case 0x16: /* SPSR_und */ in msr_banked_access_decode()
2737 case 0x1c: /* SPSR_mon */ in msr_banked_access_decode()
2740 case 0x1e: /* SPSR_hyp */ in msr_banked_access_decode()
2751 case 0x0 ... 0x6: /* 0b00xxx : r8_usr ... r14_usr */ in msr_banked_access_decode()
2755 case 0x8 ... 0xe: /* 0b01xxx : r8_fiq ... r14_fiq */ in msr_banked_access_decode()
2759 case 0x10 ... 0x11: /* 0b1000x : r14_irq, r13_irq */ in msr_banked_access_decode()
2763 case 0x12 ... 0x13: /* 0b1001x : r14_svc, r13_svc */ in msr_banked_access_decode()
2767 case 0x14 ... 0x15: /* 0b1010x : r14_abt, r13_abt */ in msr_banked_access_decode()
2771 case 0x16 ... 0x17: /* 0b1011x : r14_und, r13_und */ in msr_banked_access_decode()
2775 case 0x1c ... 0x1d: /* 0b1110x : r14_mon, r13_mon */ in msr_banked_access_decode()
2779 case 0x1e ... 0x1f: /* 0b1111x : elr_hyp, r13_hyp */ in msr_banked_access_decode()
2814 gen_exception_insn_el_v(s, 0, EXCP_UDEF, in msr_banked_access_decode()
2846 gen_exception_insn(s, 0, EXCP_UDEF, syn_uncategorized()); in msr_banked_access_decode()
2853 int tgtmode = 0, regno = 0; in gen_msr_banked()
2861 gen_update_pc(s, 0); in gen_msr_banked()
2872 int tgtmode = 0, regno = 0; in gen_mrs_banked()
2880 gen_update_pc(s, 0); in gen_mrs_banked()
2921 0b0000000111100111, /* crn == 9, crm == {c0-c2, c5-c8} */ in aa32_cpreg_encoding_in_impdef_space()
2922 0b0000000100010011, /* crn == 10, crm == {c0, c1, c4, c8} */ in aa32_cpreg_encoding_in_impdef_space()
2923 0b1000000111111111, /* crn == 11, crm == {c0-c8, c15} */ in aa32_cpreg_encoding_in_impdef_space()
2947 * the COND field in the instruction to 0xE in all cases. in do_coproc_insn()
2954 syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, in do_coproc_insn()
2957 syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
2963 syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, in do_coproc_insn()
2966 syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
3000 tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); in do_coproc_insn()
3002 gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); in do_coproc_insn()
3020 case 0: in do_coproc_insn()
3060 if ((s->hstr_active && s->current_el == 0) || ri->accessfn || in do_coproc_insn()
3070 gen_update_pc(s, 0); in do_coproc_insn()
3082 gen_update_pc(s, 0); in do_coproc_insn()
3087 case 0: in do_coproc_insn()
3205 /* Decode XScale DSP or iWMMXt insn (in the copro space, cp=0 or 1) */
3208 int cpnum = (insn >> 8) & 0xf; in disas_xscale_insn()
3210 if (extract32(s->c15_cpar, cpnum, 1) == 0) { in disas_xscale_insn()
3319 {Rd} = 0; in gen_store_exclusive()
3402 gen_exception_insn_el(s, 0, EXCP_UDEF, syn_uncategorized(), 3); in gen_srs()
3406 if (s->current_el == 0 || s->current_el == 2) { in gen_srs()
3445 gen_update_pc(s, 0); in gen_srs()
3448 case 0: /* DA */ in gen_srs()
3452 offset = 0; in gen_srs()
3471 case 0: in gen_srs()
3481 offset = 0; in gen_srs()
3507 return x & 0xc00 ? extract32(x, 7, 5) : 0; in t32_expandimm_rot()
3513 int imm = extract32(x, 0, 8); in t32_expandimm_imm()
3516 case 0: /* XY */ in t32_expandimm_imm()
3520 imm *= 0x00010001; in t32_expandimm_imm()
3523 imm *= 0x01000100; in t32_expandimm_imm()
3526 imm *= 0x01010101; in t32_expandimm_imm()
3530 imm |= 0x80; in t32_expandimm_imm()
3539 x ^= !(x < 0) * (3 << 21); in t32_branch24()
3546 return s->condexec_mask == 0; in t16_setflags()
3551 return (x & 0xff) | (x & 0x100) << (14 - 8); in t16_push_list()
3556 return (x & 0xff) | (x & 0x100) << (15 - 8); in t16_pop_list()
3581 * permits coprocessors 0..7. in valid_cp()
3586 if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) { in valid_cp()
3603 false, a->rt, 0); in trans_MCR()
3613 true, a->rt, 0); in trans_MRC()
3622 do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, in trans_MCRR()
3632 do_coproc_insn(s, a->cp, true, a->opc1, 0, a->crm, 0, in trans_MRRC()
3894 a->s = 0; in DO_CMP2()
3916 a->s = 0;
4000 if (a->shim == 0) { in do_mve_shl_ri()
4146 if (a->shim == 0) { in do_mve_sh_ri()
4319 zero = tcg_constant_i32(0); in trans_UMAAL()
4390 case 0: in DO_QADDSUB()
4420 DO_SMLAX(SMULBB, 0, 0, 0)
4421 DO_SMLAX(SMULBT, 0, 0, 1)
4422 DO_SMLAX(SMULTB, 0, 1, 0)
4423 DO_SMLAX(SMULTT, 0, 1, 1)
4425 DO_SMLAX(SMLABB, 1, 0, 0)
4426 DO_SMLAX(SMLABT, 1, 0, 1)
4427 DO_SMLAX(SMLATB, 1, 1, 0)
4430 DO_SMLAX(SMLALBB, 2, 0, 0)
4431 DO_SMLAX(SMLALBT, 2, 0, 1)
4432 DO_SMLAX(SMLALTB, 2, 1, 0)
4452 tcg_gen_andi_i32(t1, t1, 0xffff0000); in op_smlawx()
4471 DO_SMLAWX(SMULWB, 0, 0)
4472 DO_SMLAWX(SMULWT, 0, 1)
4473 DO_SMLAWX(SMLAWB, 1, 0)
4814 semihosting_enabled(s->current_el == 0) && in trans_BKPT()
4815 (a->imm == 0xab)) { in trans_BKPT()
4871 s->condexec_cond = 0; in trans_SG()
4872 s->condexec_mask = 0; in trans_SG()
4933 gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); in op_addr_rr_pre()
4948 gen_arm_shift_im(ofs, a->shtype, a->shimm, 0); in op_addr_rr_post()
4977 op_addr_rr_post(s, a, addr, 0); in op_load_rr()
5002 op_addr_rr_post(s, a, addr, 0); in op_store_rr()
5089 return add_reg_for_lit(s, a->rn, a->p ? ofs : 0); in op_addr_ri_pre()
5124 op_addr_ri_post(s, a, addr, 0); in op_load_ri()
5149 op_addr_ri_post(s, a, addr, 0); in op_store_ri()
5679 t_in = tcg_constant_i32(0); in trans_BFCI()
5820 if (shift == 0) { in DO_PAR_ADDSUB_GE()
5824 tcg_gen_deposit_i32(tn, tn, tm, 0, 16); in DO_PAR_ADDSUB_GE()
5828 tcg_gen_deposit_i32(tn, tm, tn, 0, 16); in DO_PAR_ADDSUB_GE()
6172 tcg_gen_sub2_i32(t2, t1, tcg_constant_i32(0), t3, t2, t1); in op_smmla()
6179 * Adding 0x80000000 to the 64-bit quantity means that we have in op_smmla()
6334 for (i = j = 0; i < 16; i++) { in op_stm()
6421 for (i = j = 0; i < 16; i++) { in do_ldm()
6515 zero = tcg_constant_i32(0); in trans_CLRM()
6516 for (i = 0; i < 15; i++) { in trans_CLRM()
6525 * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0) in trans_CLRM()
6527 gen_helper_v7m_msr(tcg_env, tcg_constant_i32(0xc00), zero); in trans_CLRM()
6546 if (a->cond >= 0xe) { in trans_B_cond_thumb()
6614 tcg_gen_andi_i32(tmp, tmp, 0xfffffffc); in trans_BLX_suffix()
6632 if (a->boff == 0) { in trans_BF()
6717 gen_exception_insn_el(s, 0, EXCP_NOCP, in trans_WLS()
6724 tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_R[a->rn], 0, nextlabel.label); in trans_WLS()
6739 * LTPSIZE updated, but MVE_NO_PRED will always be the same thing (0) in trans_WLS()
6819 gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); in trans_LE()
6935 gen_pc_plus_diff(s, addr, jmp_diff(s, 0)); in op_tbranch()
6957 tmp, 0, s->condlabel.label); in trans_CBZ()
6969 const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456; in trans_SVC()
6972 semihosting_enabled(s->current_el == 0) && in trans_SVC()
6978 gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); in trans_SVC()
6995 /* DA */ -4, /* IA */ 0, /* DB */ -8, /* IB */ 4 in trans_RFE()
6998 /* DA */ -8, /* IA */ 4, /* DB */ -4, /* IB */ 0 in trans_RFE()
7051 mask = val = 0; in trans_CPS()
7071 gen_set_psr_im(s, mask, 0, val); in trans_CPS()
7204 * Combinations of firstcond and mask which set up an 0b1111 in trans_IT()
7206 * UNPREDICTABLE choice to treat 0b1111 the same as 0b1110, in trans_IT()
7209 s->condexec_cond = (cond_mask >> 4) & 0xe; in trans_IT()
7210 s->condexec_mask = cond_mask & 0x1f; in trans_IT()
7234 /* In this insn input reg fields of 0b1111 mean "zero", not "PC" */ in trans_CSEL()
7238 tcg_gen_movi_i32(rn, 0); in trans_CSEL()
7243 tcg_gen_movi_i32(rm, 0); in trans_CSEL()
7249 case 0: /* CSEL */ in trans_CSEL()
7265 tcg_gen_movcond_i32(c.cond, rn, c.value, tcg_constant_i32(0), rn, rm); in trans_CSEL()
7283 gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); in disas_arm_insn()
7292 gen_exception_insn(s, 0, EXCP_UDEF, syn_illegalstate()); in disas_arm_insn()
7296 if (cond == 0xf) { in disas_arm_insn()
7317 if ((insn & 0x0e000f00) == 0x0c000100) { in disas_arm_insn()
7329 if (cond != 0xe) { in disas_arm_insn()
7343 if (((insn & 0x0c000e00) == 0x0c000000) in disas_arm_insn()
7344 && ((insn & 0x03000000) != 0x03000000)) { in disas_arm_insn()
7345 /* Coprocessor insn, coprocessor 0 or 1 */ in disas_arm_insn()
7361 if ((insn >> 11) < 0x1d) { in thumb_insn_is_16bit()
7366 /* Top five bits 0b11101 / 0b11110 / 0b11111 : this is the in thumb_insn_is_16bit()
7379 if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) { in thumb_insn_is_16bit()
7380 /* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix in thumb_insn_is_16bit()
7386 /* 0b1110_1xxx_xxxx_xxxx : BLX suffix (or UNDEF); in thumb_insn_is_16bit()
7387 * 0b1111_1xxx_xxxx_xxxx : BL suffix; in thumb_insn_is_16bit()
7388 * 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix on the end of a page in thumb_insn_is_16bit()
7406 static const uint32_t armv6m_insn[] = {0xf3808000 /* msr */, in disas_thumb2_insn()
7407 0xf3b08040 /* dsb */, in disas_thumb2_insn()
7408 0xf3b08050 /* dmb */, in disas_thumb2_insn()
7409 0xf3b08060 /* isb */, in disas_thumb2_insn()
7410 0xf3e08000 /* mrs */, in disas_thumb2_insn()
7411 0xf000d000 /* bl */}; in disas_thumb2_insn()
7412 static const uint32_t armv6m_mask[] = {0xffe0d000, in disas_thumb2_insn()
7413 0xfff0d0f0, in disas_thumb2_insn()
7414 0xfff0d0f0, in disas_thumb2_insn()
7415 0xfff0d0f0, in disas_thumb2_insn()
7416 0xffe0d000, in disas_thumb2_insn()
7417 0xf800d000}; in disas_thumb2_insn()
7419 for (i = 0; i < ARRAY_SIZE(armv6m_insn); i++) { in disas_thumb2_insn()
7428 } else if ((insn & 0xf800e800) != 0xf000e800) { in disas_thumb2_insn()
7448 if ((insn & 0xef000000) == 0xef000000) { in disas_thumb2_insn()
7450 * T32 encodings 0b111p_1111_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq in disas_thumb2_insn()
7452 * A32 encodings 0b1111_001p_qqqq_qqqq_qqqq_qqqq_qqqq_qqqq in disas_thumb2_insn()
7454 uint32_t a32_insn = (insn & 0xe2ffffff) | in disas_thumb2_insn()
7462 if ((insn & 0xff100000) == 0xf9000000) { in disas_thumb2_insn()
7464 * T32 encodings 0b1111_1001_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq in disas_thumb2_insn()
7466 * A32 encodings 0b1111_0100_ppp0_qqqq_qqqq_qqqq_qqqq_qqqq in disas_thumb2_insn()
7468 uint32_t a32_insn = (insn & 0x00ffffff) | 0xf4000000; in disas_thumb2_insn()
7478 * top nibble. The t32 encoding requires 0xe in the top nibble. in disas_thumb2_insn()
7484 ((insn >> 28) == 0xe && disas_vfp(s, insn))) { in disas_thumb2_insn()
7522 dc->condjmp = 0; in arm_tr_init_disas_context()
7534 * * if CONDEXEC[3:0] != 0b0000 : CONDEXEC is IT bits in arm_tr_init_disas_context()
7535 * * if CONDEXEC[3:0] == 0b0000 : CONDEXEC is ICI or ECI bits in arm_tr_init_disas_context()
7536 * In all cases CONDEXEC == 0 means "not in IT block or restartable in arm_tr_init_disas_context()
7539 dc->eci = dc->condexec_mask = dc->condexec_cond = 0; in arm_tr_init_disas_context()
7541 if (condexec & 0xf) { in arm_tr_init_disas_context()
7542 dc->condexec_mask = (condexec & 0xf) << 1; in arm_tr_init_disas_context()
7554 dc->user = (dc->current_el == 0); in arm_tr_init_disas_context()
7592 * SS_ACTIVE == 0: in arm_tr_init_disas_context()
7602 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending) in arm_tr_init_disas_context()
7666 store_cpu_field_constant(0, condexec_bits); in arm_tr_tb_start()
7689 tcg_gen_insn_start(pc_arg, condexec_bits, 0); in arm_tr_insn_start()
7697 if (dc->base.pc_next >= 0xffff0000) { in arm_check_kernelpage()
7722 gen_swstep_exception(dc, 0, 0); in arm_check_ss_active()
7737 dc->condjmp = 0; in arm_post_translate_insn()
7801 if ((insn & 0xffffff00) == 0xbe00) { in thumb_insn_is_unconditional()
7806 if ((insn & 0xffffffc0) == 0xba80 && arm_dc_feature(s, ARM_FEATURE_V8) && in thumb_insn_is_unconditional()
7822 if (insn == 0xe97fe97f && arm_dc_feature(s, ARM_FEATURE_V8) && in thumb_insn_is_unconditional()
7843 assert((dc->base.pc_next & 1) == 0); in thumb_tr_translate_insn()
7867 gen_exception_insn(dc, 0, EXCP_UDEF, syn_illegalstate()); in thumb_tr_translate_insn()
7910 * Conditionally skip the insn. Note that both 0xe and 0xf mean in thumb_tr_translate_insn()
7911 * "always"; 0xf is not "never". in thumb_tr_translate_insn()
7913 if (cond < 0x0e) { in thumb_tr_translate_insn()
7926 dc->condexec_cond = ((dc->condexec_cond & 0xe) | in thumb_tr_translate_insn()
7928 dc->condexec_mask = (dc->condexec_mask << 1) & 0x1f; in thumb_tr_translate_insn()
7929 if (dc->condexec_mask == 0) { in thumb_tr_translate_insn()
7930 dc->condexec_cond = 0; in thumb_tr_translate_insn()
7941 dc->condjmp = 0; in thumb_tr_translate_insn()
7942 gen_exception_insn(dc, 0, EXCP_INVSTATE, syn_uncategorized()); in thumb_tr_translate_insn()
8036 tcg_gen_exit_tb(NULL, 0); in arm_tr_tb_stop()
8047 tcg_gen_exit_tb(NULL, 0); in arm_tr_tb_stop()