Lines Matching +full:0 +full:x40e
33 #clock-cells = <0>;
40 #clock-cells = <0>;
48 #size-cells = <0>;
53 reg = <0x0 0x100>;
73 reg = <0x0 0x101>;
88 reg = <0x0 0x102>;
103 reg = <0x0 0x103>;
115 CPU4: cpu@0 {
118 reg = <0x0 0x0>;
138 reg = <0x0 0x1>;
153 reg = <0x0 0x2>;
168 reg = <0x0 0x3>;
221 PWR_CPU_SLEEP_0: cpu-sleep-0-0 {
224 arm,psci-suspend-param = <0x40000002>;
230 PWR_CPU_SLEEP_1: cpu-sleep-0-1 {
233 arm,psci-suspend-param = <0x40000003>;
240 PERF_CPU_SLEEP_0: cpu-sleep-1-0 {
243 arm,psci-suspend-param = <0x40000002>;
252 arm,psci-suspend-param = <0x40000003>;
259 PWR_CLUSTER_SLEEP_0: cluster-sleep-0-0 {
262 arm,psci-suspend-param = <0x400000F2>;
269 PWR_CLUSTER_SLEEP_1: cluster-sleep-0-1 {
272 arm,psci-suspend-param = <0x400000F3>;
279 PWR_CLUSTER_SLEEP_2: cluster-sleep-0-2 {
282 arm,psci-suspend-param = <0x400000F4>;
289 PERF_CLUSTER_SLEEP_0: cluster-sleep-1-0 {
292 arm,psci-suspend-param = <0x400000F2>;
302 arm,psci-suspend-param = <0x400000F3>;
312 arm,psci-suspend-param = <0x400000F4>;
330 reg = <0x0 0x80000000 0x0 0x0>;
370 mboxes = <&apcs_glb 0>;
436 reg = <0x0 0x85600000 0x0 0x100000>;
441 reg = <0x0 0x85700000 0x0 0x100000>;
446 reg = <0x0 0x85800000 0x0 0x600000>;
452 reg = <0x0 0x85e00000 0x0 0x200000>;
460 reg = <0 0x86000000 0 0x200000>;
465 reg = <0x0 0x86200000 0x0 0x3300000>;
470 reg = <0x0 0x8ac00000 0x0 0x7e00000>;
475 reg = <0x0 0x92a00000 0x0 0x1e00000>;
480 reg = <0x0 0x94800000 0x0 0x200000>;
485 reg = <0x0 0x94a00000 0x0 0x100000>;
490 reg = <0x0 0x9f800000 0x0 0x800000>;
495 reg = <0x0 0xf6000000 0x0 0x800000>;
500 reg = <0x0 0xf6800000 0x0 0x1400000>;
506 reg = <0x0 0xfed00000 0x0 0xa00000>;
522 qcom,local-pid = <0>;
542 qcom,local-pid = <0>;
557 soc@0 {
560 ranges = <0 0 0 0xffffffff>;
568 reg = <0x00100000 0x94000>;
577 reg = <0x00778000 0x7000>;
582 reg = <0x00780000 0x621c>;
587 reg = <0x243 0x1>;
592 reg = <0x41a2 0x1>;
599 reg = <0x00793000 0x1000>;
606 reg = <0x01008000 0x78000>;
615 reg = <0x010ac000 0x4>;
620 reg = <0x01500000 0x10000>;
629 reg = <0x01626000 0x7090>;
638 reg = <0x016c0000 0x40000>;
686 reg = <0x01704000 0xc100>;
706 reg = <0x01745000 0xa010>;
716 reg = <0x010ae000 0x1000>, /* TM */
717 <0x010ad000 0x1000>; /* SROT */
727 reg = <0x01f40000 0x20000>;
733 reg = <0x01f60000 0x20000>;
738 reg = <0x03100000 0x400000>,
739 <0x03500000 0x400000>,
740 <0x03900000 0x400000>;
744 gpio-ranges = <&tlmm 0 0 114>;
1034 reg = <0x05000000 0x40000>;
1054 iommus = <&kgsl_smmu 0>;
1072 opp-supported-hw = <0xa2>;
1078 opp-supported-hw = <0xff>;
1084 opp-supported-hw = <0xff>;
1090 opp-supported-hw = <0xff>;
1096 opp-supported-hw = <0xff>;
1102 opp-supported-hw = <0xff>;
1108 opp-supported-hw = <0xff>;
1116 reg = <0x05040000 0x10000>;
1154 reg = <0x05065000 0x9038>;
1167 reg = <0x05100000 0x40000>;
1198 reg = <0x00290000 0x10000>;
1203 reg = <0x0800f000 0x1000>,
1204 <0x08400000 0x1000000>,
1205 <0x09400000 0x1000000>,
1206 <0x0a400000 0x220000>,
1207 <0x0800a000 0x3000>;
1211 qcom,ee = <0>;
1212 qcom,channel = <0>;
1214 #size-cells = <0>;
1221 reg = <0x0a8f8800 0x400>;
1257 reg = <0x0a800000 0xc8d0>;
1270 snps,hird-threshold = /bits/ 8 <0>;
1276 reg = <0x0c012000 0x180>;
1277 #phy-cells = <0>;
1290 reg = <0x0c014000 0x180>;
1291 #phy-cells = <0>;
1304 reg = <0x0c084000 0x1000>;
1320 <&gnoc 0 &cnoc 28>;
1325 pinctrl-0 = <&sdc2_state_on>;
1357 reg = <0x0c0c4000 0x1000>,
1358 <0x0c0c5000 0x1000>,
1359 <0x0c0c8000 0x8000>;
1373 <&gnoc 0 &cnoc 27>;
1377 pinctrl-0 = <&sdc1_state_on>;
1412 reg = <0x0c2f8800 0x400>;
1438 reg = <0x0c200000 0xc8d0>;
1447 snps,hird-threshold = /bits/ 8 <0>;
1453 reg = <0x0c8c0000 0x40000>;
1472 <&mdss_dsi0_phy 0>,
1473 <0>,
1474 <0>,
1475 <0>,
1476 <0>;
1481 reg = <0x0c900000 0x1000>,
1482 <0x0c9b0000 0x1040>;
1508 reg = <0x0c901000 0x89000>;
1512 interrupts = <0>;
1529 <&gnoc 0 &mnoc 17>;
1533 iommus = <&mmss_smmu 0>;
1539 #size-cells = <0>;
1541 port@0 {
1542 reg = <0>;
1583 reg = <0x0c994000 0x400>;
1594 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1622 #size-cells = <0>;
1624 port@0 {
1625 reg = <0>;
1641 reg = <0x0c994400 0x100>,
1642 <0x0c994500 0x300>,
1643 <0x0c994800 0x188>;
1649 #phy-cells = <0>;
1659 reg = <0x0c144000 0x1f000>;
1664 qcom,ee = <0>;
1672 reg = <0x0c16f000 0x200>;
1677 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
1680 pinctrl-0 = <&blsp1_uart1_default>;
1687 reg = <0x0c170000 0x1000>;
1695 pinctrl-0 = <&blsp1_uart2_default>;
1701 reg = <0x0c175000 0x600>;
1712 pinctrl-0 = <&i2c1_default>;
1715 #size-cells = <0>;
1721 reg = <0x0c176000 0x600>;
1732 pinctrl-0 = <&i2c2_default>;
1735 #size-cells = <0>;
1741 reg = <0x0c177000 0x600>;
1752 pinctrl-0 = <&i2c3_default>;
1755 #size-cells = <0>;
1761 reg = <0x0c178000 0x600>;
1772 pinctrl-0 = <&i2c4_default>;
1775 #size-cells = <0>;
1781 reg = <0x0c184000 0x1f000>;
1786 qcom,ee = <0>;
1794 reg = <0x0c1af000 0x200>;
1799 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
1802 pinctrl-0 = <&blsp2_uart1_default>;
1809 reg = <0x0c1b5000 0x600>;
1820 pinctrl-0 = <&i2c5_default>;
1823 #size-cells = <0>;
1829 reg = <0x0c1b6000 0x600>;
1840 pinctrl-0 = <&i2c6_default>;
1843 #size-cells = <0>;
1849 reg = <0x0c1b7000 0x600>;
1860 pinctrl-0 = <&i2c7_default>;
1863 #size-cells = <0>;
1869 reg = <0x0c1b8000 0x600>;
1880 pinctrl-0 = <&i2c8_default>;
1883 #size-cells = <0>;
1889 reg = <0x146bf000 0x1000>;
1894 ranges = <0 0x146bf000 0x1000>;
1898 reg = <0x94c 0xc8>;
1904 reg = <0x0ca00020 0x10>,
1905 <0x0ca30000 0x100>,
1906 <0x0ca30400 0x100>,
1907 <0x0ca30800 0x100>,
1908 <0x0ca30c00 0x100>,
1909 <0x0c824000 0x1000>,
1910 <0x0ca00120 0x4>,
1911 <0x0c825000 0x1000>,
1912 <0x0ca00124 0x4>,
1913 <0x0c826000 0x1000>,
1914 <0x0ca00128 0x4>,
1915 <0x0ca31000 0x500>,
1916 <0x0ca10000 0x1000>,
1917 <0x0ca14000 0x1000>;
2038 iommus = <&mmss_smmu 0xc00>,
2039 <&mmss_smmu 0xc01>,
2040 <&mmss_smmu 0xc02>,
2041 <&mmss_smmu 0xc03>;
2048 #size-cells = <0>;
2055 #size-cells = <0>;
2056 reg = <0x0ca0c000 0x1000>;
2072 pinctrl-0 = <&cci0_default &cci1_default>;
2076 cci_i2c0: i2c-bus@0 {
2077 reg = <0>;
2080 #size-cells = <0>;
2087 #size-cells = <0>;
2093 reg = <0x0cc00000 0xff000>;
2099 interconnects = <&gnoc 0 &mnoc 13>,
2103 iommus = <&mmss_smmu 0x400>,
2104 <&mmss_smmu 0x401>,
2105 <&mmss_smmu 0x40a>,
2106 <&mmss_smmu 0x407>,
2107 <&mmss_smmu 0x40e>,
2108 <&mmss_smmu 0x40f>,
2109 <&mmss_smmu 0x408>,
2110 <&mmss_smmu 0x409>,
2111 <&mmss_smmu 0x40b>,
2112 <&mmss_smmu 0x40c>,
2113 <&mmss_smmu 0x40d>,
2114 <&mmss_smmu 0x410>,
2115 <&mmss_smmu 0x421>,
2116 <&mmss_smmu 0x428>,
2117 <&mmss_smmu 0x429>,
2118 <&mmss_smmu 0x42b>,
2119 <&mmss_smmu 0x42c>,
2120 <&mmss_smmu 0x42d>,
2121 <&mmss_smmu 0x411>,
2122 <&mmss_smmu 0x431>;
2144 reg = <0x0cd00000 0x40000>;
2189 reg = <0x15700000 0x4040>;
2193 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2207 qcom,smem-states = <&adsp_smp2p_out 0>;
2222 #size-cells = <0>;
2235 #size-cells = <0>;
2246 #size-cells = <0>;
2257 #sound-dai-cells = <0>;
2266 reg = <0x17900000 0xe000>;
2279 reg = <0x17911000 0x1000>;
2289 reg = <0x17920000 0x1000>;
2293 frame-number = <0>;
2296 reg = <0x17921000 0x1000>,
2297 <0x17922000 0x1000>;
2303 reg = <0x17923000 0x1000>;
2310 reg = <0x17924000 0x1000>;
2317 reg = <0x17925000 0x1000>;
2324 reg = <0x17926000 0x1000>;
2331 reg = <0x17927000 0x1000>;
2338 reg = <0x17928000 0x1000>;
2345 reg = <0x17a00000 0x10000>, /* GICD */
2346 <0x17b00000 0x100000>; /* GICR * 8 */
2353 redistributor-stride = <0x0 0x20000>;
2366 thermal-sensors = <&tsens 0>;
2536 interrupts = <GIC_PPI 1 0xf08>,
2537 <GIC_PPI 2 0xf08>,
2538 <GIC_PPI 3 0xf08>,
2539 <GIC_PPI 0 0xf08>;