35 #define BANK_USRSYS 0
78 FIELD(V7M_CONTROL, NPRIV, 0, 1)
84 FIELD(V7M_EXCRET, ES, 0, 1)
94 #define EXC_RETURN_MIN_MAGIC 0xff000000
98 #define FNC_RETURN_MIN_MAGIC 0xfefffffe
101 FIELD(DBGWCR, E, 0, 1)
177 #define MDCR_HPMN     (0x1fU)
184 #define TTBCR_N      (7U << 0) /* TTBCR.EAE==0 */
185 #define TTBCR_T0SZ   (7U << 0) /* TTBCR.EAE==1 */
200 FIELD(VTCR, T0SZ, 0, 6)
219 #define HCRX_ENAS0    (1ULL << 0)
238  * Depending on the value of HCR_EL2.E2H, bits 0 and 1
240  * bit 0 or bit 10. We use _E2H1 and _E2H0 suffixes to
243 FIELD(CNTHCTL, EL0PCTEN_E2H1, 0, 1)
245 FIELD(CNTHCTL, EL1PCTEN_E2H0, 0, 1)
275 #define M_FAKE_FSR_NSC_EXEC 0xf /* NS executing in S&NSC memory */
276 #define M_FAKE_FSR_SFAULT 0xe /* SecureFault INVTRAN, INVEP or AUVIOL */
398         env->sp_el[0] = env->xregs[31];  in aarch64_save_sp()
407         env->xregs[31] = env->sp_el[0];  in aarch64_restore_sp()
421     env->pstate = deposit32(env->pstate, 0, 1, imm);  in update_spsel()
613         return 0;  in arm_fi_to_sfsc()
615         fsc = fi->level == 1 ? 0x3 : 0x6;  in arm_fi_to_sfsc()
618         fsc = 0x1;  in arm_fi_to_sfsc()
621         fsc = fi->level == 1 ? 0xd : 0xf;  in arm_fi_to_sfsc()
624         fsc = fi->level == 1 ? 0x9 : 0xb;  in arm_fi_to_sfsc()
627         fsc = fi->level == 1 ? 0x5 : 0x7;  in arm_fi_to_sfsc()
630         fsc = 0x8 | (fi->ea << 12);  in arm_fi_to_sfsc()
633         fsc = fi->level == 1 ? 0xc : 0xe;  in arm_fi_to_sfsc()
637         fsc = 0x409;  in arm_fi_to_sfsc()
640         fsc = fi->level == 1 ? 0x40c : 0x40e;  in arm_fi_to_sfsc()
643         fsc = 0x408;  in arm_fi_to_sfsc()
646         fsc = 0x406 | (fi->ea << 12);  in arm_fi_to_sfsc()
649         fsc = 0x2;  in arm_fi_to_sfsc()
652         fsc = 0x400;  in arm_fi_to_sfsc()
655         fsc = 0x404;  in arm_fi_to_sfsc()
658         fsc = 0x405;  in arm_fi_to_sfsc()
661         fsc = 0x4;  in arm_fi_to_sfsc()
664         fsc = 0x0;  in arm_fi_to_sfsc()
694         return 0;  in arm_fi_to_lfsc()
697         if (fi->level < 0) {  in arm_fi_to_lfsc()
698             fsc = 0b101001;  in arm_fi_to_lfsc()
704         assert(fi->level >= 0 && fi->level <= 3);  in arm_fi_to_lfsc()
705         fsc = 0b001000 | fi->level;  in arm_fi_to_lfsc()
708         assert(fi->level >= 0 && fi->level <= 3);  in arm_fi_to_lfsc()
709         fsc = 0b001100 | fi->level;  in arm_fi_to_lfsc()
713         if (fi->level < 0) {  in arm_fi_to_lfsc()
714             fsc = 0b101011;  in arm_fi_to_lfsc()
716             fsc = 0b000100 | fi->level;  in arm_fi_to_lfsc()
720         fsc = 0x10 | (fi->ea << 12);  in arm_fi_to_lfsc()
724         if (fi->level < 0) {  in arm_fi_to_lfsc()
725             fsc = 0b010011;  in arm_fi_to_lfsc()
727             fsc = 0b010100 | fi->level;  in arm_fi_to_lfsc()
732         fsc = 0x18;  in arm_fi_to_lfsc()
736         if (fi->level < 0) {  in arm_fi_to_lfsc()
737             fsc = 0b011011;  in arm_fi_to_lfsc()
739             fsc = 0b011100 | fi->level;  in arm_fi_to_lfsc()
743         fsc = 0x19;  in arm_fi_to_lfsc()
746         fsc = 0x11 | (fi->ea << 12);  in arm_fi_to_lfsc()
749         fsc = 0x21;  in arm_fi_to_lfsc()
752         fsc = 0x22;  in arm_fi_to_lfsc()
755         fsc = 0x30;  in arm_fi_to_lfsc()
758         fsc = 0x31;  in arm_fi_to_lfsc()
761         fsc = 0x34;  in arm_fi_to_lfsc()
764         fsc = 0x35;  in arm_fi_to_lfsc()
768         if (fi->level < 0) {  in arm_fi_to_lfsc()
769             fsc = 0b100011;  in arm_fi_to_lfsc()
771             fsc = 0b100100 | fi->level;  in arm_fi_to_lfsc()
775         fsc = 0b101000;  in arm_fi_to_lfsc()
792      * usually use this to indicate AXI bus Decode error (0) or  in arm_extabort_type()
877  * Secure PL1&0 (i.e. mmu indexes E3, E30_0, E30_3_PAN), but it is
1109     case 0:  in v7m_cpacr_pass()
1110     case 2: /* UNPREDICTABLE: we treat like 0 */  in v7m_cpacr_pass()
1136     return cpu_mode_names[psr & 0xf];  in aarch32_mode_name()
1382     sctlr &= (el == 0 ? SCTLR_ATA0 : SCTLR_ATA);  in allocation_tag_access_enabled()
1383     return sctlr != 0;  in allocation_tag_access_enabled()
1424  * @access_type: 0 for read, 1 for write, 2 for execute
1425  * @memop: memory operation feeding this access, or 0 for none
1453  * @access_type: 0 for read, 1 for write, 2 for execute
1454  * @memop: memory operation feeding this access, or 0 for none
1484 FIELD(PREDDESC, OPRSZ, 0, 6)
1495 FIELD(MTEDESC, MIDX,  0, 4)
1510  * @desc: MTEDESC descriptor word (0 means no MTE checks)
1527  * @desc: MTEDESC descriptor word (0 means no MTE checks)
1583     bool match = ((ptr_tag + bit55) & 0xf) == 0;  in tcma_check()
1598     ptr &= sextract64(ptr, 0, 56);  in useronly_clean_ptr()
1606     int64_t clean_ptr = sextract64(ptr, 0, 56);  in useronly_maybe_clean_ptr()
1607     if (tbi_check(desc, clean_ptr < 0)) {  in useronly_maybe_clean_ptr()
1616     ECI_NONE = 0, /* No completed beats */
1626 #define PMCRN_MASK  0xf800
1628 #define PMCRLP  0x80
1629 #define PMCRLC  0x40
1630 #define PMCRDP  0x20
1631 #define PMCRX   0x10
1632 #define PMCRD   0x8
1633 #define PMCRC   0x4
1634 #define PMCRP   0x2
1635 #define PMCRE   0x1
1642 #define PMXEVTYPER_P          0x80000000
1643 #define PMXEVTYPER_U          0x40000000
1644 #define PMXEVTYPER_NSK        0x20000000
1645 #define PMXEVTYPER_NSU        0x10000000
1646 #define PMXEVTYPER_NSH        0x08000000
1647 #define PMXEVTYPER_M          0x04000000
1648 #define PMXEVTYPER_MT         0x02000000
1649 #define PMXEVTYPER_EVTCOUNT   0x0000ffff
1655 #define PMCCFILTR             0xf8000000
1733     return arm_is_el2_enabled(env) ? env->cp15.mdcr_el2 : 0;  in arm_mdcr_el2_eff()
1817  * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2).