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/openbmc/u-boot/arch/arm/dts/
H A Dk3-am65.dtsi59 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
60 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
61 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
62 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
63 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
65 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
66 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
67 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
68 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
69 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j7200.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xc000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xc000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
113 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j721e.dtsi25 #size-cells = <0>;
39 cpu0: cpu@0 {
41 reg = <0x000>;
44 i-cache-size = <0xC000>;
47 d-cache-size = <0x8000>;
55 reg = <0x001>;
58 i-cache-size = <0xC000>;
61 d-cache-size = <0x8000>;
72 cache-size = <0x100000>;
114 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
H A Dk3-j784s4.dtsi26 #size-cells = <0>;
65 cpu0: cpu@0 {
67 reg = <0x000>;
70 i-cache-size = <0xc000>;
73 d-cache-size = <0x8000>;
81 reg = <0x001>;
84 i-cache-size = <0xc000>;
87 d-cache-size = <0x8000>;
95 reg = <0x002>;
98 i-cache-size = <0xc000>;
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsram.h57 #define OMAP2_SRAM_PA 0x40200000
58 #define OMAP3_SRAM_PA 0x40200000
/openbmc/u-boot/include/configs/
H A Domap3_igep00x0.h16 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
19 #define CONFIG_SPL_TEXT_BASE 0x40200000
39 "stdin=serial\0" \
40 "stdout=serial\0" \
41 "stderr=serial\0"
45 "scriptaddr=0x87E00000\0" \
46 "pxefile_addr_r=0x87F00000\0"
49 func(MMC, mmc, 0)
66 "echo WARNING: Could not determine device tree to use; fi; \0"
107 #define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
[all …]
H A Domap3_evm.h23 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
26 #define CONFIG_SPL_TEXT_BASE 0x40200000
49 #define CONFIG_ENV_OFFSET 0x260000
50 #define CONFIG_ENV_ADDR 0x260000
54 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
69 "run mmcboot\0"
81 "fi\0"
86 func(MMC, mmc, 0) \
87 func(LEGACY_MMC, legacy_mmc, 0) \
88 func(UBIFS, ubifs, 0) \
[all …]
H A Ddevkit8000.h23 * header. That is 0x800FFFC0--0x80100000 should not be used for any
27 #define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/
28 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
30 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
31 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
49 #define CONFIG_DM9000_BASE 0x2c000000
51 #define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
63 #define CONFIG_JFFS2_PART_OFFSET 0x680000
64 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
77 "loadaddr=0x82000000\0" \
[all …]
H A Domap3_logic.h19 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in
23 #define CONFIG_SPL_TEXT_BASE 0x40200000
33 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */
67 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
68 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
69 "mmcdev=0\0" \
70 "mmcroot=/dev/mmcblk0p2 rw\0" \
71 "mmcrootfstype=ext4 rootwait\0" \
72 "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \
73 "nandrootfstype=ubifs rootwait\0" \
[all …]
H A Domap3_overo.h12 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
15 #define CONFIG_SPL_TEXT_BASE 0x40200000
53 "bootdir=/boot\0" \
54 "bootfile=zImage\0" \
55 "usbtty=cdc_acm\0" \
56 "console=ttyO2,115200n8\0" \
57 "mpurate=auto\0" \
58 "optargs=\0" \
59 "vram=12M\0" \
60 "dvimode=1024x768MR-16@60\0" \
[all …]
H A Dqemu-arm.h13 #define CONFIG_SYS_SDRAM_BASE 0x40000000
24 #define CONFIG_ENV_ADDR 0x4000000
28 func(USB, usb, 0) \
29 func(SCSI, scsi, 0) \
30 func(VIRTIO, virtio, 0) \
37 "fdt_high=0xffffffff\0" \
38 "initrd_high=0xffffffff\0" \
39 "fdt_addr=0x40000000\0" \
40 "scriptaddr=0x40200000\0" \
41 "pxefile_addr_r=0x40300000\0" \
[all …]
H A Domap3_beagle.h18 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
21 #define CONFIG_SPL_TEXT_BASE 0x40200000
43 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
45 #define CONFIG_ENV_OFFSET 0x260000
46 #define CONFIG_ENV_ADDR 0x260000
50 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000
75 "run mmcboot\0"
87 "fi\0"
92 func(MMC, mmc, 0) \
93 func(LEGACY_MMC, legacy_mmc, 0) \
[all …]
H A Dtricorder.h22 * header. That is 0x800FFFC0--0x80100000 should not be used for any
81 #define CONFIG_ENV_OFFSET 0x120000 /* env start */
82 #define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */
88 #define CONFIG_LOADADDR 0x82000000
91 "console=ttyO2,115200n8\0" \
92 "mmcdev=0\0" \
93 "vram=3M\0" \
94 "defaultdisplay=lcd\0" \
95 "kernelopts=mtdoops.mtddev=3\0" \
96 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
[all …]
H A Dsniper.h46 #define CONFIG_SYS_SDRAM_BASE 0x80000000
67 #define CONFIG_SPL_TEXT_BASE 0x40200000
70 #define CONFIG_SPL_BSS_START_ADDR 0x80000000
72 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
105 "kernel_addr_r=0x82000000\0" \
106 "loadaddr=0x82000000\0" \
107 "fdt_addr_r=0x88000000\0" \
108 "fdtaddr=0x88000000\0" \
109 "ramdisk_addr_r=0x88080000\0" \
110 "pxefile_addr_r=0x80100000\0" \
[all …]
/openbmc/u-boot/arch/arm/mach-imx/imx8m/
H A Dimximage.cfg11 LOADER spl/u-boot-spl-ddr.bin 0x7E1000
12 SECOND_LOADER u-boot.itb 0x40200000 0x60000
/openbmc/u-boot/configs/
H A Dimx8mq_evk_defconfig3 CONFIG_SYS_TEXT_BASE=0x40200000
4 CONFIG_SYS_MALLOC_F_LEN=0x2000
9 CONFIG_FIT_EXTERNAL_OFFSET=0x3000
26 CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dcorstone1000-mps3.dts18 reg = <0x40100000 0x10000>;
27 reg = <0x40200000 0x100000>;
/openbmc/linux/arch/powerpc/platforms/cell/spufs/
H A Dspu_restore_dump.h_shipped7 0x40800000,
8 0x409ff801,
9 0x24000080,
10 0x24fd8081,
11 0x1cd80081,
12 0x33001180,
13 0x42034003,
14 0x33800284,
15 0x1c010204,
16 0x40200000,
[all …]
H A Dspu_save_crt0.S18 .space SIZEOF_SPU_SPILL_REGS, 0x0
24 stqa $0, regs_spill + 0
47 .balignl 16, 0x40200000
49 stqd $16, 0($3)
53 andi $5, $4, 0x7F
62 il $0, 0
64 stqd $0, 0($SP)
74 brsl $0, main
78 * stop-and-signal with code=0.
84 stop 0x0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnxp,isp1760.yaml61 reg = <0x40200000 0x100000>;
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8540p.dtsi184 linux,pci-domain = <0>;
201 reg = <0x0 0x01c10000 0x0 0x3000>,
202 <0x0 0x40000000 0x0 0xf1d>,
203 <0x0 0x40000f20 0x0 0xa8>,
204 <0x0 0x40001000 0x0 0x1000>,
205 <0x0 0x40100000 0x0 0x100000>;
208 ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
209 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
216 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
217 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/u-boot/doc/SPL/
H A DREADME.omap332 SRAM: 0x40200000 - 0x4020FFFF
33 DDR1: 0x80000000 - 0xBFFFFFFF
36 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
37 0x4020E000 - 0x4020FFFC: Area for the SPL stack.
38 0x80000000 - 0x8007FFFF: Area for the SPL BSS.
39 0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot
40 0x80208000 - 0x80307FFF: malloc() pool available to SPL.
43 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
44 0x4020E000 - 0x4020FFFC: Area for the SPL stack.
45 0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dregs-uart.h9 #define FFUART_BASE 0x40100000
10 #define BTUART_BASE 0x40200000
11 #define STUART_BASE 0x40700000
12 #define HWUART_BASE 0x41600000
43 #define IER_RAVIE (1 << 0)
50 #define IIR_IP (1 << 0)
56 #define FCR_TRFIFOE (1 << 0)
57 #define FCR_ITL_1 0
69 #define LCR_WLS0 (1 << 0)
78 #define LSR_DR (1 << 0)
[all …]

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